i86_as.1 3.3 KB

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  1. .\" $Header$
  2. .TH I86_AS 1
  3. .ad
  4. .SH NAME
  5. i86_as \- assembler for Intel 8086
  6. .SH SYNOPSIS
  7. /usr/em/lib/i86_as [options] argument ...
  8. .SH DESCRIPTION
  9. This assembler is made with the general framework
  10. described in \fIuni_ass\fP(6).
  11. .SH SYNTAX
  12. .IP segments
  13. An address on the Intel 8086 consists of two pieces:
  14. a segment number and an offset. A memory address is computed as
  15. the segment number shifted left 4 bits + the offset.
  16. Assembly language addresses only give the offset, with the exception of
  17. the address of an inter-segment jump or call (see `addressing modes' below).
  18. For each segment type (.org, .text, .data, or .bss) the segment number
  19. must be given with the .sbase pseudo-instruction.
  20. The syntax is:
  21. .br
  22. .sbase <segment-id> expression
  23. .br
  24. with segment-id one of .org, .text, .data, or .bss.
  25. Example:
  26. .br
  27. .sbase .text 0x1000
  28. .IP registers
  29. The Intel 8086 has the following 16-bit registers:
  30. .br
  31. Four general registers: ax (accumulator), bx (base), cx (count), and dx (data).
  32. The upper halves and lower halves of these registers are separately
  33. addressable as ah, bh, ch, dh, and al, bl, cl, dl respectively.
  34. .br
  35. Two pointer registers: sp (stack pointer) and bp (base pointer).
  36. .br
  37. Two index registers: si (source index) and di (destination index).
  38. .br
  39. Four segment registers: cs (code), ds (data), ss (stack), and es (extra).
  40. .IP "addressing modes"
  41. .nf
  42. .ta 8 16 24 32 40 48
  43. syntax meaning
  44. expr the value of `expr' is immediate data or
  45. an address offset. There is no special
  46. notation for immediate data.
  47. register one of the aforementioned general registers
  48. or their upper or lower halves, or one of the
  49. four segment registers.
  50. (expr) the value of expr is the address of the operand.
  51. (reg)
  52. expr (reg) the value of `expr' (if present) + the contents of
  53. `reg' (which must be a pointer or an index register)
  54. is the address of the operand.
  55. (preg) (ireg)
  56. expr (preg) (ireg)
  57. the value of `expr' (if present) + the contents of
  58. `preg' (which must be a pointer register) + the
  59. contents of `ireg' (which must be an index register)
  60. is the address of the operand.
  61. The next addressing mode is only allowed with the instructions
  62. "callf" or "jmpf".
  63. expr : expr the value of the first `expr' is a segment number,
  64. the value of the second `expr' is an address offset.
  65. The (absolute) address of the operand is computed
  66. as described above.
  67. .fi
  68. .IP instructions
  69. Each time an address is computed the assembler decide which segment register
  70. to use. You can override the assembler's choice by prefixing the instruction
  71. with one of eseg, cseg, sseg, or dseg; these prefixes indicate that the
  72. assembler should choose es, cs, ss, or ds instead.
  73. .SH "SEE ALSO"
  74. uni_ass(6),
  75. ack(1),
  76. .br
  77. MCS-86 assembly language reference manual, 1978, Intel Corporation
  78. .SH EXAMPLE
  79. .nf
  80. .ta 8 16 24 32 40 48
  81. An example of Intel 8086 assembly language:
  82. _panic:
  83. push bp
  84. mov bp,sp
  85. .data
  86. _35:
  87. .word 24944
  88. .word 26990
  89. .word 14947
  90. .word 32
  91. .text
  92. call _disable
  93. mov ax,_35
  94. push ax
  95. call _str
  96. pop si
  97. push 4(bp)
  98. call _str
  99. pop si
  100. call _nlcr
  101. call _exit
  102. mov sp,bp
  103. pop bp
  104. ret
  105. .extern _nopanic
  106. _nopanic:
  107. push bp
  108. mov bp,sp
  109. .data
  110. _38:
  111. .word 28526
  112. .word 24944
  113. .word 26990
  114. .word 14947
  115. .word 32
  116. .text
  117. mov ax,_38
  118. push ax
  119. call _str
  120. pop si
  121. push 4(bp)
  122. call _str
  123. pop si
  124. push 6(bp)
  125. call _octal
  126. pop si
  127. mov sp,bp
  128. pop bp
  129. ret
  130. .fi