table 194 KB

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  1. /*
  2. * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
  3. * See the copyright notice in the ACK home directory, in the file "Copyright".
  4. */
  5. rscid = "$Id$"
  6. /********************************
  7. * *
  8. * 68000, 68010 and 68020 *
  9. * back end table *
  10. * *
  11. ********************************/
  12. #include <whichone.h>
  13. #if TBL68881 && ! TBL68020
  14. Something very wrong here!
  15. #endif
  16. #if WORD_SIZE!=2 && WORD_SIZE!=4
  17. Something very wrong here!
  18. #endif
  19. #if TBL68020
  20. #define SYNTAX_68020 1
  21. #endif
  22. /* #define FANCY_MODES 1
  23. /* On the M68020, there are some real fancy addressing modes.
  24. Their use makes the code a bit shorter, but also much slower.
  25. The FANCY_MODES #define enables the use of these addressing
  26. modes.
  27. */
  28. #define small(x) ((x)>=1 && (x)<=8)
  29. #define directadd(x) (small(x) || (x)>128)
  30. #define directsub(x) (directadd(0-x))
  31. #define nicesize(x) ((x)==1||(x)==2||(x)==4||(x)==8)
  32. #define low8(x) ((x) & 0377)
  33. #define low16(x) ((x) & 0177777)
  34. #define in_1(x) sfit(x,8)
  35. #define in_2(x) sfit(x,16)
  36. EM_WSIZE = WORD_SIZE
  37. EM_PSIZE = 4
  38. EM_BSIZE = 8
  39. SL = 8
  40. TIMEFACTOR = 1/2
  41. PROPERTIES
  42. D_REG /* data registers */
  43. A_REG(4) /* address registers */
  44. DD_REG /* allocatable D_REG, may not be a register variable */
  45. AA_REG(4) /* allocatable A_REG, may not be a register variable */
  46. RD_REG /* data register, register var */
  47. RA_REG(4) /* address register, register var */
  48. #if WORD_SIZE==2
  49. D_REG4(4) /* data register, 4 bytes */
  50. DD_REG4(4) /* allocatable D_REG, 4 bytes */
  51. #else
  52. #define D_REG4 D_REG
  53. #define DD_REG4 DD_REG
  54. #endif
  55. #if TBL68881
  56. FS_REG(4) /* floating point register */
  57. FD_REG(8) /* double floating point register */
  58. #endif
  59. REGISTERS
  60. d0, d1, d2 :D_REG, DD_REG.
  61. d3, d4, d5, d6, d7 :D_REG, RD_REG regvar.
  62. #if WORD_SIZE==2
  63. dl0("d0")=d0, dl1("d1")=d1, dl2("d2")=d2 :D_REG4, DD_REG4.
  64. #else
  65. #define dl0 d0
  66. #define dl1 d1
  67. #define dl2 d2
  68. #endif
  69. a0, a1 :A_REG, AA_REG.
  70. a2, a3, a4, a5 :A_REG, RA_REG regvar(reg_pointer).
  71. lb ("a6"), sp :A_REG. /* localbase and stack pointer */
  72. #if TBL68881
  73. F0 ("fp0"), F1 ("fp1"), F2 ("fp2"), F3 ("fp3"), F4 ("fp4"), F5 ("fp5"),
  74. F6 ("fp6"), F7 ("fp7") :FS_REG.
  75. fp0=F0,fp1=F1,fp2=F2,fp3=F3,fp4=F4,fp5=F5,fp6=F6,fp7=F7
  76. :FD_REG.
  77. #endif
  78. TOKENS
  79. /* Not all addressing modes available on the MC68020 are used in this
  80. * table. E.g (Dn), data register indirect is not used. Compared to
  81. * (An), address register indirect, (Dn) requires two more bytes and
  82. * several more clock cycles. Using (Dn) is even more expensive in
  83. * time than first moving Dn to an address register An, and then using
  84. * (An). For this kind of reasons several addressing modes are
  85. * not used in this table.
  86. *
  87. * Cost in bytes may sometimes be incorrect. Several effective addresses
  88. * use displacements that can occupy either 2 or 4 bytes. These are not
  89. * considered different TOKENS in this table.
  90. *
  91. * Data registers are the only registers used as index registers in this
  92. * table; address registers are only used to hold addresses.
  93. *
  94. * For the m68k2 and m68k4 table: the MC68000 and MC68010 have two
  95. * modes that use displacements (offsets) of limited size:
  96. * - offset(A_REG, Index_reg), where offset is only 8 bits, and
  97. * - offset(A_REG), where offset can only be 16 bits.
  98. * To make sure that no output is given with offsets too large, two
  99. * extra tokens are declared: t_regAregXcon and t_regAcon. These are
  100. * used as addresses to these modes. Whenever the displacements become
  101. * too large, they are transformed into different tokens.
  102. *
  103. * Sometimes some TOKENS are used with displacements (offsets) of 0.
  104. * It would have been possible to provide separate TOKENS for these, in
  105. * case the assembler doesn't handle zero offsets optimally. This
  106. * however would mean a very large amount of extra TOKENS and SETS for
  107. * a very small profit in code bytes, so we won't do that.
  108. *
  109. * To prevent the TOKENS list from getting too unreadable, #ifdefs are
  110. * used to form three parts:
  111. * (i) the common part;
  112. * (ii) the m68k2 and m68k4 part;
  113. * (iii) the m68020 part;
  114. */
  115. /* Part (i) */
  116. zero_const = {INT num;} WORD_SIZE cost(0,0) "#" num .
  117. small_const = {INT num;} WORD_SIZE cost(0,0) "#" num .
  118. bconst = {INT num;} WORD_SIZE cost(0,0) "#" num .
  119. const = {INT num;} WORD_SIZE cost(4,4) "#" num .
  120. #if WORD_SIZE==2
  121. /* ??? "string+const */
  122. zero_const4 = {INT num;} 4 cost(0,0) "#" num .
  123. small_const4 = {INT num;} 4 cost(0,0) "#" num .
  124. bconst4 = {INT num;} 4 cost(0,0) "#" num .
  125. const4 = {ADDR num;} 4 cost(4,4) "#" num .
  126. #endif
  127. indirect4 = {A_REG reg;} 4 cost(0,4) "(" reg ")" .
  128. post_inc4 = {A_REG reg;} 4 cost(0,4) "(" reg ")+" .
  129. pre_dec4 = {A_REG reg;} 4 cost(0,5) "-(" reg ")" .
  130. dreg4 = {D_REG4 reg;} 4 cost(0,0) reg .
  131. areg = {A_REG reg;} 4 cost(0,0) reg .
  132. dreg2 = {D_REG reg;} WORD_SIZE cost(0,0) reg .
  133. indirect2 = {A_REG reg;} WORD_SIZE cost(0,4) "(" reg ")" .
  134. post_inc2 = {A_REG reg;} WORD_SIZE cost(0,4) "(" reg ")+" .
  135. pre_dec2 = {A_REG reg;} WORD_SIZE cost(0,5) "-(" reg ")" .
  136. dreg1 = {D_REG reg;} WORD_SIZE cost(0,0) reg .
  137. indirect1 = {A_REG reg;} WORD_SIZE cost(0,4) "(" reg ")" .
  138. post_inc1 = {A_REG reg;} WORD_SIZE cost(0,4) "(" reg ")+" .
  139. pre_dec1 = {A_REG reg;} WORD_SIZE cost(0,5) "-(" reg ")" .
  140. ext_addr = {ADDR bd;} 4 cost(4,5) "#" bd .
  141. llabel = {ADDR bd;} 4 cost(2,0) bd .
  142. slabel = {ADDR bd;} 4 cost(0,0) bd .
  143. /* check this out */
  144. extend1 = {D_REG reg;} WORD_SIZE cost(0,0) reg .
  145. #if WORD_SIZE==2
  146. extend1_4 = {D_REG4 reg;} 4 cost(0,0) reg .
  147. #else
  148. #define extend1_4 extend1
  149. #endif
  150. extend2 = {D_REG4 reg;} 4 cost(0,0) reg .
  151. #ifndef SYNTAX_68020
  152. /* Part (ii) in m68k2/4 syntax */
  153. absolute4 = {ADDR bd;} 4 cost(4,8) bd .
  154. offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) bd "(" reg ")" .
  155. index_off4 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,7)
  156. bd "(" reg "," xreg ".l)" .
  157. absolute2 = {ADDR bd;} WORD_SIZE cost(4,6) bd .
  158. offsetted2 = {A_REG reg; INT bd;} WORD_SIZE cost(2,4) bd "(" reg ")" .
  159. index_off2 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} WORD_SIZE cost(2,5)
  160. bd "(" reg "," xreg ".l)" .
  161. absolute1 = {ADDR bd;} WORD_SIZE cost(4,6) bd .
  162. offsetted1 = {A_REG reg; INT bd;} WORD_SIZE cost(2,4) bd "(" reg ")" .
  163. index_off1 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} WORD_SIZE cost(2,5)
  164. bd "(" reg "," xreg ".l)" .
  165. LOCAL = {INT bd;} WORD_SIZE cost(2,6) bd "(a6)" .
  166. #if WORD_SIZE==2
  167. /* pointers may go into DLOCAL's */
  168. DLOCAL = {INT bd;} 4 cost(2,6) bd "(a6)" .
  169. #endif
  170. local_addr = {INT bd;} 4 cost(2,6) bd "(a6)" .
  171. regAcon = {A_REG reg; INT bd;} 4 cost(2,6) bd "(" reg ")" .
  172. regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8)
  173. bd "(" reg "," xreg ".l)" .
  174. /* note: in the m68k[24] version %sc always equals 1 */
  175. #endif
  176. #ifdef SYNTAX_68020
  177. /* Part (ii) in m68020 syntax */
  178. absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
  179. offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
  180. index_off4 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(4,9)
  181. "(" bd "," reg "," xreg ".l*" sc ")" .
  182. absolute2 = {ADDR bd;} WORD_SIZE cost(4,7) "(" bd ")" .
  183. offsetted2 = {A_REG reg; INT bd;} WORD_SIZE cost(2,6) "(" bd "," reg ")" .
  184. index_off2 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} WORD_SIZE cost(4,9)
  185. "(" bd "," reg "," xreg ".l*" sc ")" .
  186. absolute1 = {ADDR bd;} WORD_SIZE cost(4,7) "(" bd ")" .
  187. offsetted1 = {A_REG reg; INT bd;} WORD_SIZE cost(2,6) "(" bd "," reg ")" .
  188. index_off1 = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} WORD_SIZE cost(4,9)
  189. "(" bd "," reg "," xreg ".l*" sc ")" .
  190. LOCAL = {INT bd;} WORD_SIZE cost(2,6) "(" bd ",a6)" .
  191. #if WORD_SIZE==2
  192. /* pointers may go into DLOCAL's */
  193. DLOCAL = {INT bd;} 4 cost(2,6) "(" bd ",a6)" .
  194. #endif
  195. local_addr = {INT bd;} 4 cost(2,3) "(" bd ",a6)" .
  196. regAcon = {A_REG reg; INT bd;} 4 cost(2,3) "(" bd "," reg ")" .
  197. regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,7)
  198. "(" bd "," reg "," xreg ".l*" sc ")" .
  199. #endif
  200. #ifdef TBL68020
  201. /* Part (iii) */
  202. abs_index4 = {INT sc; D_REG4 xreg; ADDR bd;} 4 cost(6,9)
  203. "(" bd "," xreg ".l*" sc ")" .
  204. OFF_off4 = {A_REG reg; INT bd; ADDR od;} 4 cost(6,19)
  205. "([" bd "," reg "]," od ")" .
  206. OFF_indoff4 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} 4 cost(6,19)
  207. "([" bd "," reg "]," xreg ".l*" sc "," od ")" .
  208. INDOFF_off4 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} 4 cost(6,19)
  209. "([" bd "," reg "," xreg ".l*" sc "]," od ")" .
  210. ABS_off4 = {ADDR bd; ADDR od;} 4 cost(8,22) "([" bd "]," od ")" .
  211. ABS_indoff4 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} 4 cost(8,22)
  212. "([" bd "]," xreg ".l*" sc "," od ")" .
  213. ABSIND_off4 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} 4 cost(8,22)
  214. "([" bd "," xreg ".l*" sc "]," od ")" .
  215. abs_index2 = {INT sc; D_REG4 xreg; ADDR bd;} WORD_SIZE cost(6,9)
  216. "(" bd "," xreg ".l*" sc ")" .
  217. OFF_off2 = {A_REG reg; INT bd; ADDR od;} WORD_SIZE cost(6,19)
  218. "([" bd "," reg "]," od ")" .
  219. OFF_indoff2 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} WORD_SIZE cost(6,19)
  220. "([" bd "," reg "]," xreg ".l*" sc "," od ")" .
  221. INDOFF_off2 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} WORD_SIZE cost(6,19)
  222. "([" bd "," reg "," xreg ".l*" sc "]," od ")" .
  223. ABS_off2 = {ADDR bd; ADDR od;} WORD_SIZE cost(8,22) "([" bd "]," od ")" .
  224. ABS_indoff2 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} WORD_SIZE cost(8,22)
  225. "([" bd "]," xreg ".l*" sc "," od ")" .
  226. ABSIND_off2 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} WORD_SIZE cost(8,22)
  227. "([" bd "," xreg ".l*" sc "]," od ")" .
  228. abs_index1 = {INT sc; D_REG4 xreg; ADDR bd;} WORD_SIZE cost(6,9)
  229. "(" bd "," xreg ".l*" sc ")" .
  230. OFF_off1 = {A_REG reg; INT bd; ADDR od;} WORD_SIZE cost(6,19)
  231. "([" bd "," reg "]," od ")" .
  232. OFF_indoff1 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} WORD_SIZE cost(6,19)
  233. "([" bd "," reg "]," xreg ".l*" sc "," od ")" .
  234. INDOFF_off1 = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} WORD_SIZE cost(6,19)
  235. "([" bd "," reg "," xreg ".l*" sc "]," od ")" .
  236. ABS_off1 = {ADDR bd; ADDR od;} WORD_SIZE cost(8,22) "([" bd "]," od ")" .
  237. ABS_indoff1 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} WORD_SIZE cost(8,22)
  238. "([" bd "]," xreg ".l*" sc "," od ")" .
  239. ABSIND_off1 = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} WORD_SIZE cost(8,22)
  240. "([" bd "," xreg ".l*" sc "]," od ")" .
  241. ILOCAL = {INT bd;} WORD_SIZE cost(4,16) "([" bd ",a6])" .
  242. off_con = {A_REG reg; INT bd; ADDR od;} 4 cost(6,18)
  243. "([" bd "," reg "]," od ")".
  244. off_regXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} 4 cost(6,18)
  245. "([" bd "," reg "]," xreg ".l*" sc "," od ")" .
  246. indoff_con = {A_REG reg; D_REG4 xreg; INT sc; INT bd; ADDR od;} 4 cost(6,18)
  247. "([" bd "," reg "," xreg ".l*" sc "]," od ")" .
  248. abs_con = {ADDR bd; ADDR od;} 4 cost(8,21) "([" bd "]," od ")" .
  249. abs_regXcon = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} 4 cost(8,21)
  250. "([" bd "]," xreg ".l*" sc "," od ")" .
  251. absind_con = {INT sc; D_REG4 xreg; ADDR bd; ADDR od;} 4 cost(8,21)
  252. "([" bd "," xreg ".l*" sc "]," od ")" .
  253. ext_regX = {INT sc; D_REG4 xreg; ADDR bd;} 4 cost(6,15)
  254. "(" bd "," xreg ".l*" sc ")" .
  255. regX = {INT sc; D_REG4 xreg;} 4 cost(2,7) "(" xreg ".l*" sc ")" .
  256. DREG_pair = {D_REG4 reg1; D_REG4 reg2;} 8 cost(2,0) reg1 ":" reg2 .
  257. #define t_regAregXcon regAregXcon
  258. #define t_regAcon regAcon
  259. #else /* TBL68020 */
  260. t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
  261. t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
  262. #endif
  263. #if WORD_SIZE!=2
  264. #define DLOCAL LOCAL
  265. #endif
  266. SETS
  267. /* The SETS list cannot be kept as 'readable' as the TOKENS
  268. * list because cgg is one pass.
  269. * We makes use of the fact that sets are indeed sets. Thus
  270. * D_REG + D_REG4 == D_REG, when the wordsize is 4.
  271. */
  272. sconsts = small_const + bconst .
  273. consts = const + sconsts + zero_const.
  274. #if WORD_SIZE!=2
  275. #define small_const4 small_const
  276. #define zero_const4 zero_const
  277. #define bconst4 bconst
  278. #define const4 const
  279. #define sconsts4 sconsts
  280. #define consts4 consts
  281. #else
  282. sconsts4 = small_const4 + bconst4 .
  283. consts4 = const4 + sconsts4 + zero_const4.
  284. #endif
  285. #ifndef TBL68020
  286. /* A m68k2/m68k4 part */
  287. data4 = D_REG4 + DLOCAL + consts4 + post_inc4 + pre_dec4 +
  288. indirect4 + offsetted4 + index_off4 + absolute4 +
  289. ext_addr + dreg4 .
  290. memory4 = data4 - D_REG4 - dreg4 .
  291. control4 = indirect4 + offsetted4 + index_off4 + absolute4 +
  292. DLOCAL.
  293. alterable4 = data4 + A_REG - consts4 - ext_addr .
  294. any4 = data4 + A_REG . /* all four above together */
  295. #if WORD_SIZE==2
  296. data2 = D_REG + LOCAL + dreg2 + post_inc2 + pre_dec2 +
  297. indirect2 + offsetted2 + index_off2 + absolute2 +
  298. consts .
  299. memory2 = data2 - D_REG - dreg2 .
  300. control2 = indirect2 + offsetted2 + index_off2 + absolute2 + LOCAL.
  301. #else
  302. data2 = dreg2 + post_inc2 + pre_dec2 + indirect2 +
  303. offsetted2 + index_off2 + absolute2 + consts .
  304. memory2 = data2 - dreg2 .
  305. control2 = indirect2 + offsetted2 + index_off2 + absolute2 .
  306. #endif
  307. alterable2 = data2 + D_REG - consts .
  308. any2 = data2 + D_REG .
  309. data1 = dreg1 + post_inc1 + pre_dec1 + indirect1 +
  310. offsetted1 + index_off1 + absolute1 + consts .
  311. memory1 = data1 - dreg1 .
  312. control1 = indirect1 + offsetted1 + index_off1 + absolute1 .
  313. alterable1 = data1 + D_REG - consts .
  314. any1 = data1 + D_REG .
  315. #else /* TBL68020 */
  316. data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
  317. offsetted4 + OFF_off4 + OFF_indoff4 +
  318. INDOFF_off4 + dreg4 +
  319. ABS_off4 + ABS_indoff4 + ABSIND_off4 +
  320. absolute4 + abs_index4 + consts4 + ext_addr +
  321. DLOCAL
  322. #if WORD_SIZE!=2
  323. + ILOCAL
  324. #endif
  325. .
  326. memory4 = data4 - D_REG4 - dreg4 .
  327. control4 = memory4 - (post_inc4 + pre_dec4 + consts4 + ext_addr).
  328. alterable4 = data4 + A_REG - consts - ext_addr .
  329. any4 = data4 + A_REG . /* all four above together */
  330. #if WORD_SIZE==2
  331. data2 = D_REG + LOCAL+ ILOCAL+
  332. dreg2 + indirect2 + post_inc2 + pre_dec2 + index_off2 +
  333. offsetted2 + OFF_off2 + OFF_indoff2 +
  334. INDOFF_off2 +
  335. ABS_off2 + ABS_indoff2 + ABSIND_off2 +
  336. absolute2 + abs_index2 + consts .
  337. memory2 = data2 - D_REG - dreg2 .
  338. #else
  339. data2 = dreg2 + indirect2 + post_inc2 + pre_dec2 + index_off2 +
  340. offsetted2 + OFF_off2 + OFF_indoff2 +
  341. INDOFF_off2 +
  342. ABS_off2 + ABS_indoff2 + ABSIND_off2 +
  343. absolute2 + abs_index2 + consts .
  344. memory2 = data2 - dreg2 .
  345. #endif
  346. control2 = memory2 - (post_inc2 + pre_dec2 + consts ) .
  347. alterable2 = data2 + D_REG - consts .
  348. any2 = data2 + D_REG. /* all four above together */
  349. data1 = dreg1 + indirect1 + post_inc1 + pre_dec1 + index_off1 +
  350. offsetted1 + OFF_off1 + OFF_indoff1 +
  351. INDOFF_off1 +
  352. ABS_off1 + ABS_indoff1 + ABSIND_off1 +
  353. absolute1 + abs_index1 + consts .
  354. memory1 = data1 - dreg1 .
  355. control1 = memory1 - (post_inc1 + pre_dec1 + consts ) .
  356. alterable1 = data1 + D_REG - consts .
  357. any1 = data1 + D_REG. /* all four above together */
  358. #endif /* TBL68020 */
  359. /* This is a common part */
  360. #if WORD_SIZE==2
  361. /* Not any4, since any is used in 'with' and not in 'kills' */
  362. any = any2 + any1 .
  363. #else
  364. any = any4 + any2 + any1 .
  365. #endif
  366. control = control4 + control2 + control1 .
  367. indirect = indirect4 + indirect2 + indirect1 .
  368. offsetted = offsetted4 + offsetted2 + offsetted1 .
  369. index_off = index_off4 + index_off2 + index_off1 .
  370. absolute = absolute4 + absolute2 + absolute1 .
  371. pre_post = pre_dec4 + pre_dec2 + pre_dec1 +
  372. post_inc4 + post_inc2 + post_inc1 .
  373. #ifndef TBL68020
  374. /* A m68k2/m68k4 part */
  375. regind_addr = regAcon + regAregXcon + t_regAcon + t_regAregXcon .
  376. address = ext_addr + local_addr + regAcon + regAregXcon .
  377. all_regind = indirect + offsetted + pre_post + index_off +
  378. regind_addr + areg .
  379. all_indir = all_regind .
  380. allexceptcon = ALL - ( D_REG + A_REG + consts + dreg2 + dreg1 +
  381. local_addr + ext_addr + regAcon + regAregXcon +
  382. t_regAcon + t_regAregXcon ) .
  383. use_index = index_off4 + index_off2 + index_off1 .
  384. #else /* TBL68020 */
  385. reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
  386. memind4 = reg_memind4 +
  387. ABS_off4 + ABS_indoff4 .
  388. reg_memind2 = OFF_off2 + OFF_indoff2 + INDOFF_off2 .
  389. memind2 = reg_memind2 +
  390. ABS_off2 + ABS_indoff2 .
  391. reg_memind1 = OFF_off1 + OFF_indoff1 + INDOFF_off1 .
  392. memind1 = reg_memind1 +
  393. ABS_off1 + ABS_indoff1 .
  394. reg_memind = reg_memind4 + reg_memind2 + reg_memind1 .
  395. memind = memind4 + memind2 + memind1 .
  396. regind_addr = regAcon + regAregXcon +
  397. off_con + off_regXcon +
  398. indoff_con .
  399. address = regind_addr +
  400. ext_addr + local_addr +
  401. abs_con + abs_regXcon +
  402. absind_con +
  403. ext_regX .
  404. all_regind = indirect + offsetted + index_off + pre_post +
  405. reg_memind + regind_addr + areg .
  406. all_indir = all_regind + memind + ILOCAL .
  407. allexceptcon = ALL - ( D_REG + A_REG + consts + dreg2 + dreg1 +
  408. local_addr + ext_addr + regAcon + regAregXcon + ext_regX ) .
  409. use_index4 = index_off4 + abs_index4 +
  410. OFF_indoff4 + INDOFF_off4 +
  411. ABS_indoff4 + ABSIND_off4 .
  412. use_index2 = index_off2 + abs_index2 +
  413. OFF_indoff2 + INDOFF_off2 +
  414. ABS_indoff2 + ABSIND_off2 .
  415. use_index1 = index_off1 + abs_index1 +
  416. OFF_indoff1 + INDOFF_off1 +
  417. ABS_indoff1 + ABSIND_off1 .
  418. use_indaddr = regAregXcon +
  419. off_regXcon + indoff_con +
  420. abs_regXcon + absind_con +
  421. ext_regX .
  422. use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
  423. #endif /* TBL68020 */
  424. /* A common part */
  425. posextern = absolute + all_indir .
  426. #if WORD_SIZE==2
  427. genreg2 = D_REG .
  428. #define genreg genreg2
  429. #else
  430. #define genreg genreg4
  431. #endif
  432. genreg4 = D_REG4 + A_REG.
  433. label = llabel + slabel .
  434. immediate4 = consts4 + ext_addr .
  435. #if WORD_SIZE==2
  436. immediate2 = consts .
  437. #endif
  438. conreg4 = D_REG4 + immediate4 .
  439. conreg2 = dreg2 + consts + D_REG .
  440. conreg1 = dreg1 + consts + D_REG .
  441. #if WORD_SIZE==2
  442. conreg = conreg1 + conreg2 .
  443. #else
  444. conreg = conreg1 + conreg2 + conreg4 .
  445. #endif
  446. shconreg = D_REG + small_const .
  447. datalt4 = data4 * alterable4 .
  448. datalt2 = data2 * alterable2 .
  449. datalt1 = data1 * alterable1 .
  450. datalt = datalt4 + datalt2 + datalt1 .
  451. memalt4 = memory4 * alterable4 .
  452. memalt2 = memory2 * alterable2 .
  453. memalt1 = memory1 * alterable1 .
  454. #ifndef TBL68020
  455. /* A m68k2/m68k4 part */
  456. imm_cmp4 = alterable4 - A_REG .
  457. imm_cmp2 = alterable2 + D_REG .
  458. imm_cmp1 = datalt1 + D_REG .
  459. test_set4 = datalt4 + extend2 + extend1_4 .
  460. #if WORD_SIZE==2
  461. test_set2 = datalt2 + extend1 .
  462. #else
  463. test_set2 = datalt2 .
  464. #endif
  465. test_set1 = datalt1 .
  466. #else /* TBL68020 */
  467. imm_cmp4 = any4 - immediate4 - A_REG .
  468. imm_cmp2 = any2 - consts .
  469. imm_cmp1 = any1 - consts .
  470. test_set4 = any4 - immediate4 + extend2 + extend1_4 .
  471. #if WORD_SIZE==2
  472. test_set2 = data2 + extend1 - immediate2 .
  473. #else
  474. test_set2 = data2 - consts .
  475. #endif
  476. test_set1 = data1 - consts .
  477. #endif /* TBL68020 */
  478. test_set = test_set4 + test_set2 + test_set1 .
  479. #ifndef TBL68020
  480. t_address = address + t_regAregXcon + t_regAcon .
  481. #else /* TBL68020 */
  482. #define t_address address
  483. #endif /* TBL68020 */
  484. #if TBL68881
  485. freg = FD_REG + FS_REG .
  486. store4 = any4 + FS_REG .
  487. #else
  488. store4 = any4 .
  489. #endif
  490. #if WORD_SIZE==2
  491. dups2 = genreg2 .
  492. #endif
  493. dups4 = genreg4 .
  494. #include "instrmacs.h"
  495. INSTRUCTIONS
  496. /* Since the 68000 , the 68010 and the 68020 instruction sets are rather
  497. * extensive, especially because e.g. 'add.l' and 'add.w' are
  498. * considered different instructions, only those instructions are
  499. * listed here that are used in the rest of this table.
  500. *
  501. * Instruction timing cost cannot be accurately given, nor the timing
  502. * cost for getting operands. Detailed information about this can be
  503. * found in the "MC68020 User's Manual", section 9, about instruction
  504. * timing. The cost used in this table are 'worst case' cost, as
  505. * mentioned in section 9 of the user's manual. Furthermore, the
  506. * timing information for the 68k[24] and the 68020 differ, which
  507. * means that the 68k[24] will not always have the best code
  508. * possible.
  509. *
  510. * The first few instructions had to be added because register
  511. * variables are used. The LOCALs below are register variables.
  512. * One may not conclude that these operations are also allowed
  513. * on LOCALs that are not register variables.
  514. * The cost have been adapted, but are not accurate; when 'real'
  515. * LOCALs are used the cost are very inaccurate.
  516. */
  517. add_i ADD_I any_int:ro, LOCAL:rw:cc cost(0,0).
  518. sub_i SUB_I any_int:ro, LOCAL:rw:cc cost(0,0).
  519. lea address:ro, DLOCAL:wo cost(0,0).
  520. sh "illegal" shconreg+LOCAL:ro, LOCAL:rw:cc cost(0,0).
  521. xxx "illegal" data4:ro, LOCAL:rw:cc cost(0,0).
  522. xxx "illegal" LOCAL:ro, alterable4:rw:cc cost(0,0).
  523. #if WORD_SIZE==2
  524. /* divs_w "divs.w" data2:ro, LOCAL:rw:cc cost(0,56). */
  525. /* divu_w "divu.w" data2:ro, LOCAL:rw:cc cost(0,44). */
  526. muls_w "muls.w" data2:ro, LOCAL:rw:cc cost(0,28).
  527. mulu_w "mulu.w" data2:ro, LOCAL:rw:cc cost(0,28).
  528. #endif
  529. #if TBL68020 && WORD_SIZE!=2
  530. divs_l "divs.l" data4:ro, LOCAL:rw:cc cost(0,90).
  531. divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
  532. muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
  533. mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
  534. #endif /* TBL68020 */
  535. #if WORD_SIZE==2
  536. add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
  537. #else
  538. add_l "add.l" any4:ro, D_REG+LOCAL:rw:cc cost(2,3).
  539. #endif
  540. add_l "add.l" any4:ro, A_REG+DLOCAL+areg:rw cost(2,3).
  541. add_l "add.l" conreg4:ro, alterable4:rw:cc cost(2,6).
  542. #if WORD_SIZE==2
  543. add_w "add.w" any2:ro, D_REG+LOCAL:rw:cc cost(2,3).
  544. add_w "add.w" conreg2:ro, alterable2:rw:cc cost(2,6).
  545. #endif
  546. and_l "and.l" data4:ro, D_REG4:rw:cc cost(2,3).
  547. and_l "and.l" D_REG4:ro, memalt4:rw:cc cost(2,6).
  548. and_l "and.l" consts4:ro, datalt4:rw:cc cost(2,6).
  549. #if WORD_SIZE==2
  550. and_w "and.w" data2:ro, D_REG:rw:cc cost(2,3).
  551. and_w "and.w" D_REG:ro, memalt2:rw:cc cost(2,6).
  552. and_w "and.w" consts:ro, datalt2:rw:cc cost(2,6).
  553. #endif
  554. asl_l "asl.l" shconreg:ro, D_REG4:rw:cc cost(2,5).
  555. asl "asl #1," memalt2:rw:cc cost(2,4).
  556. asr_l "asr.l" shconreg:ro, D_REG4:rw:cc cost(2,4).
  557. asr "asr #1," memalt2:rw:cc cost(2,4).
  558. #if WORD_SIZE==2
  559. asl_w "asl.w" shconreg:ro, D_REG:rw:cc cost(2,5).
  560. asr_w "asr.w" shconreg:ro, D_REG:rw:cc cost(2,4).
  561. #endif
  562. bclr const:ro, D_REG:rw kills:cc cost(2,4).
  563. bra label cost(2,5).
  564. bcc label cost(2,5).
  565. bcs label cost(2,5).
  566. beq label cost(2,5).
  567. bge label cost(2,5).
  568. bgt label cost(2,5).
  569. bhi label cost(2,5).
  570. ble label cost(2,5).
  571. bls label cost(2,5).
  572. blt label cost(2,5).
  573. bmi label cost(2,5).
  574. bne label cost(2,5).
  575. bpl label cost(2,5).
  576. bvc label cost(2,5).
  577. bvs label cost(2,5).
  578. bset conreg2:ro, D_REG+D_REG4:rw kills :cc cost(2,4).
  579. btst conreg2:ro, any1:rw kills :cc cost(2,3).
  580. /* Check dreg[21] for m68020 and m68k2 */
  581. clr_l "clr.l" D_REG4+dreg4:wo:cc cost(2,3).
  582. clr_l "clr.l" memalt4:wo:cc cost(2,6).
  583. clr_w "clr.w" D_REG+dreg2:wo:cc cost(2,2).
  584. clr_w "clr.w" memalt2:wo:cc cost(2,4).
  585. clr_b "clr.b" D_REG+dreg1:wo:cc cost(2,2).
  586. clr_b "clr.b" memalt1:wo:cc cost(2,4).
  587. cmp_l "cmp.l" any4:ro, genreg4:ro kills :cc cost(2,3).
  588. cmp_l "cmp.l" post_inc4:ro, post_inc4:ro kills :cc cost(2,2).
  589. cmp_l "cmp.l" immediate4:ro, imm_cmp4:ro kills :cc cost(2,2).
  590. #if WORD_SIZE==2
  591. cmp_w "cmp.w" any2+extend2:ro, D_REG+dreg2+extend2:ro kills :cc cost(2,2).
  592. #else
  593. cmp_w "cmp.w" any2+extend2:ro, dreg2+extend2:ro kills :cc cost(2,2).
  594. #endif
  595. cmp_w "cmp.w" post_inc2:ro, post_inc2:ro kills :cc cost(2,2).
  596. cmp_w "cmp.w" consts:ro, imm_cmp2:ro kills :cc cost(2,2).
  597. cmp_b "cmp.b" any1+extend1+extend1_4:ro, dreg1+extend1+extend1_4:ro kills :cc cost(2,3).
  598. cmp_b "cmp.b" post_inc1:ro, post_inc1:ro kills :cc cost(2,2).
  599. cmp_b "cmp.b" consts:ro, imm_cmp1:ro kills :cc cost(2,2).
  600. dbf D_REG4:rw, label cost(2,5).
  601. eor_l "eor.l" conreg4:ro, datalt4:rw:cc cost(2,6).
  602. #if WORD_SIZE==2
  603. eor_w "eor.w" conreg2:ro, datalt2:rw:cc cost(2,4).
  604. #endif
  605. /* in the next two instructions: LOCAL only allowed if register var */
  606. ext_l "ext.l" D_REG+LOCAL+D_REG4:rw:cc cost(2,2).
  607. ext_w "ext.w" D_REG+LOCAL+D_REG4:rw:cc cost(2,2).
  608. jmp address+control4 cost(2,0).
  609. jsr address+control4 kills :cc d0 d1 d2 a0 a1 cost(2,3).
  610. lea address+control4:ro, A_REG+areg:wo cost(2,0).
  611. /*
  612. lsl_l "lsl.l" shconreg:ro, D_REG:rw:cc cost(2,4).
  613. lsl "lsl #1," memalt2:rw:cc cost(2,4).
  614. */
  615. lsr_l "lsr.l" shconreg:ro, D_REG4:rw:cc cost(2,4).
  616. #if WORD_SIZE==2
  617. lsr_w "lsr.w" shconreg:ro, D_REG:rw:cc cost(2,4).
  618. #endif
  619. lsr "lsr #1," memalt2:rw:cc cost(2,4).
  620. /* move_l does not set the condition codes if the destination is an
  621. address register!
  622. */
  623. move_l "move.l" any4:ro, A_REG+areg:wo cost(2,2).
  624. move_l "move.l" any4:ro, alterable4+dreg4-(areg+A_REG):wo:cc cost(2,2).
  625. #if WORD_SIZE==2
  626. move_l "move.l" sconsts:ro, D_REG+dreg2:wo:cc cost(2,2).
  627. /*
  628. move_l "move.l" any2:ro, alterable4+dreg4-(areg+A_REG):wo:cc cost(2,2).
  629. */
  630. move_w "move.w" any2:ro, alterable2+dreg2:wo:cc cost(2,2).
  631. move_b "move.b" any1:ro, alterable1+dreg2:wo:cc cost(2,2).
  632. #else
  633. move_w "move.w" any2:ro, alterable2+dreg4:wo:cc cost(2,2).
  634. move_b "move.b" any1:ro, alterable1+dreg4:wo:cc cost(2,2).
  635. #endif
  636. neg_b "neg.b" D_REG:rw:cc cost(2,3).
  637. neg_w "neg.w" D_REG:rw:cc cost(2,3).
  638. neg_l "neg.l" D_REG4:rw:cc cost(2,3).
  639. neg_l "neg.l" memory4:rw:cc cost(2,6).
  640. #if WORD_SIZE==2
  641. neg_w "neg.w" memory2:rw:cc cost(2,6).
  642. #endif
  643. not_l "not.l" D_REG4:rw:cc cost(2,3).
  644. not_l "not.l" memory4:rw:cc cost(2,6).
  645. #if WORD_SIZE==2
  646. not_w "not.w" D_REG:rw:cc cost(2,3).
  647. not_w "not.w" memory2:rw:cc cost(2,6).
  648. #endif
  649. or_l "or.l" data4:ro, D_REG4:rw:cc cost(2,3).
  650. or_l "or.l" D_REG4:ro, memalt4:rw:cc cost(2,6).
  651. or_l "or.l" consts4:ro, datalt4:rw:cc cost(2,6).
  652. #if WORD_SIZE==2
  653. or_w "or.w" data2:ro, D_REG:rw:cc cost(2,3).
  654. or_w "or.w" D_REG:ro, memalt2:rw:cc cost(2,6).
  655. or_w "or.w" consts:ro, datalt2:rw:cc cost(2,6).
  656. #endif
  657. rol_l "rol.l" shconreg:ro, D_REG4:rw:cc cost(2,4).
  658. rol "rol #1," memalt2:rw:cc cost(2,4).
  659. ror_l "ror.l" shconreg:ro, D_REG4:rw:cc cost(2,4).
  660. ror "ror #1," memalt2:rw:cc cost(2,4).
  661. #if WORD_SIZE==2
  662. rol_w "rol.w" shconreg:ro, D_REG:rw:cc cost(2,4).
  663. ror_w "ror.w" shconreg:ro, D_REG:rw:cc cost(2,4).
  664. #endif
  665. roxl "roxl #1," memalt2:rw:cc cost(2,4).
  666. roxr "roxr #1," memalt2:rw:cc cost(2,4).
  667. sne datalt1:rw cost(2,3).
  668. sub_l "sub.l" any4:ro, D_REG4:rw:cc cost(2,3).
  669. sub_l "sub.l" any4+areg:ro, A_REG+areg:rw cost(2,3).
  670. sub_l "sub.l" conreg4:ro, alterable4:rw:cc cost(2,6).
  671. #if WORD_SIZE==2
  672. sub_w "sub.w" any2:ro, D_REG+LOCAL:rw:cc cost(2,3).
  673. sub_w "sub.w" conreg2:ro, alterable2:rw:cc cost(2,6).
  674. /* On a swap, we only want the lower part of D_REG, so don't set cc */
  675. swap D_REG:rw kills :cc cost(2,2).
  676. #endif
  677. tst_l "tst.l" test_set4:ro:cc cost(2,3).
  678. tst_w "tst.w" test_set2+extend2:ro:cc cost(2,3).
  679. tst_b "tst.b" test_set1+extend1+extend1_4:ro:cc cost(2,3).
  680. unlk A_REG cost(2,6).
  681. bxx "illegal" label cost(2,5).
  682. sxx "illegal" any_int:wo cost(2,5).
  683. #if WORD_SIZE==2
  684. s4xx "illegal" any4:wo cost(2,5).
  685. xxx "illegal" any4+any2:ro, any4+any2:rw:cc cost(2,3).
  686. bit "illegal" control4+control2:rw:cc cost(2,6).
  687. #else
  688. xxx "illegal" any4:ro, any4:rw:cc cost(2,3).
  689. bit "illegal" control4:rw:cc cost(2,6).
  690. #endif
  691. sh "illegal" shconreg:ro, D_REG:rw:cc cost(2,4).
  692. shw "illegal" control2:rw:cc cost(2,4).
  693. #if WORD_SIZE==2
  694. divs_w "divs.w" data2:ro, D_REG:rw:cc cost(0,56).
  695. divu_w "divu.w" data2:ro, D_REG:rw:cc cost(0,44).
  696. muls_w "muls.w" data2:ro, D_REG:rw:cc cost(0,28).
  697. mulu_w "mulu.w" data2:ro, D_REG:rw:cc cost(0,28).
  698. #endif
  699. #ifdef TBL68020
  700. cmp2_l "cmp2.l" address+control4:ro, genreg4:ro kills :cc cost(2,18).
  701. divs_l "divs.l" data4:ro, D_REG4:rw:cc cost(2,90).
  702. divu_l "divu.l" data4:ro, D_REG4:rw:cc cost(2,78).
  703. divsl_l "divsl.l" data4:ro, DREG_pair:rw kills :cc cost(2,90).
  704. divul_l "divul.l" data4:ro, DREG_pair:rw kills :cc cost(2,78).
  705. pea address+control4+regX cost(2,4).
  706. #if WORD_SIZE==2
  707. cmp2_w "cmp2.w" address+control2:ro, genreg2:ro kills :cc cost(2,18).
  708. extb_l "extb.l" extend1_4+D_REG4:rw:cc cost(2,4).
  709. muls_l "muls.l" data4:ro, D_REG4:rw:cc cost(2,44).
  710. mulu_l "mulu.l" data4:ro, D_REG4:rw:cc cost(2,44).
  711. #else
  712. /* in the next instruction: LOCAL only allowed if register var */
  713. extb_l "extb.l" extend1_4+D_REG+LOCAL:rw:cc cost(2,4).
  714. muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
  715. mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
  716. #endif
  717. #else /* TBL68020 */
  718. pea address+control4 cost(2,4).
  719. #endif /* TBL68020 */
  720. /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  721. * Extra pseudo instruction; it just kills a D_REG;
  722. * it is necessary with long divides where remainders are important;
  723. * see also: 'pat rmi' and 'pat rmu'
  724. * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
  725. killreg "! kill" D_REG+D_REG4+A_REG:wo cost(0,0).
  726. killcc "! killcc" kills :cc cost(0,0).
  727. #if TBL68881
  728. /* These descriptions are not very accurate, because we have no
  729. other 8-byte objects in the table.
  730. */
  731. fmove_s "fmove.s" data4:ro, freg:wo cost(4,100).
  732. fmove_s "fmove.s" freg:ro, data4:wo cost(4,100).
  733. fmove_d "fmove.d" freg:ro, data4:wo cost(4,100).
  734. fmove_d "fmove.d" data4:ro, freg:ro cost(4,100).
  735. fmove_l "fmove.l" freg:ro, D_REG:wo cost(4,100).
  736. fmove_l "fmove.l" data4:ro, freg:wo cost(4,100).
  737. fmove freg:ro,freg:wo cost(4,100).
  738. fadd_s "fadd.s" data4:ro, freg:rw cost(4,100).
  739. fadd_d "fadd.d" data4:ro, freg:rw cost(4,100).
  740. fsub_s "fsub.s" data4:ro, freg:rw cost(4,100).
  741. fsub_d "fsub.d" data4:ro, freg:rw cost(4,100).
  742. fsub freg:ro, freg:rw cost(4,100).
  743. fmul freg:ro, freg:rw cost(4,100).
  744. fmul_s "fmul.s" data4:ro, freg:rw cost(4,100).
  745. fmul_d "fmul.d" data4:ro, freg:rw cost(4,100).
  746. fdiv freg:ro, freg:rw cost(4,100).
  747. fdiv_s "fdiv.s" data4:ro, freg:rw cost(4,100).
  748. fdiv_d "fdiv.d" data4:ro, freg:rw cost(4,100).
  749. fcmp freg:ro, freg:ro cost(4,100).
  750. fbeq label:ro cost(4,4).
  751. fblt label:ro cost(4,4).
  752. fmovecr const:ro, freg:rw cost(4,100).
  753. fabs freg:rw cost(4,100).
  754. fneg freg:rw cost(4,100).
  755. fgetman freg:rw cost(4,100).
  756. fintrz freg:ro, freg:wo cost(4,100).
  757. fgetexp freg:ro, freg:wo cost(4,100).
  758. fsub_l "fsub.l" const:ro, freg:rw cost(4,100).
  759. #endif
  760. MOVES
  761. from consts %num==0 to D_REG4+dreg4
  762. gen clr_l %2
  763. #if WORD_SIZE==2
  764. from zero_const4 %num==0 to A_REG+areg
  765. gen sub_l %2,%2
  766. from zero_const4 %num==0 to D_REG4+dreg4
  767. gen clr_l %2
  768. #endif
  769. from consts %num==0 to A_REG+areg
  770. gen sub_l %2,%2
  771. #if WORD_SIZE==2
  772. from consts %num==0 to D_REG+dreg2
  773. gen clr_w %2
  774. from sconsts to D_REG+dreg2
  775. gen move_l %1,%2 /* uses moveq */
  776. from consts to D_REG4+dreg4
  777. gen move_l {const4, %1.num},%2
  778. #endif
  779. #if WORD_SIZE==2
  780. from sconsts4+zero_const4 %num==0 to memalt4
  781. #else
  782. from consts %num==0 to memalt4
  783. #endif
  784. gen clr_l %2
  785. from consts %num==0 to memalt2
  786. gen clr_w %2
  787. from consts %num==0 to memalt1
  788. gen clr_b %2
  789. from consts to memalt1
  790. gen move_b {const, low8(%1.num)}, %2
  791. #if WORD_SIZE!=2
  792. from consts to memalt2
  793. gen move_w {const, low16(%1.num)}, %2
  794. #endif
  795. from regAcon %bd==0 to A_REG+areg
  796. gen move_l %1.reg, %2
  797. #ifndef TBL68020
  798. from t_regAregXcon sfit(%bd, 8) to A_REG+areg
  799. gen lea {regAregXcon, %1.reg, %1.xreg, 1, %1.bd}, %2
  800. from t_regAregXcon to A_REG+areg
  801. gen lea {regAregXcon, %1.reg, %1.xreg, 1, 0}, %2
  802. add_l {const4, %1.bd}, %2
  803. from t_regAcon sfit(%bd, 16) to A_REG+areg
  804. gen lea {regAcon, %1.reg, %1.bd}, %2
  805. from t_regAcon to A_REG+areg
  806. gen move_l %1.reg, %2
  807. add_l {const4, %1.bd}, %2
  808. #endif /* TBL68020 */
  809. from address - ext_addr to A_REG+areg
  810. gen lea %1, %2
  811. #if WORD_SIZE==2
  812. from ext_addr to A_REG+areg
  813. gen lea {absolute4, %1.bd}, %2
  814. #endif
  815. from any4 to areg+A_REG
  816. gen move_l %1, %2
  817. from any4 to alterable4-(areg+A_REG)
  818. gen move_l %1, %2
  819. from any2 to alterable2
  820. gen move_w %1, %2
  821. from any1 to alterable1
  822. gen move_b %1, %2
  823. #if WORD_SIZE!=2
  824. from any4-sconsts4 to A_REG+areg
  825. gen move_l %1, %2
  826. from any2 to dreg4
  827. gen clr_l %2
  828. move_w %1, %2
  829. #endif
  830. from any1 to dreg_int
  831. gen clr_i %2
  832. move_b %1, %2
  833. #if WORD_SIZE==2
  834. from any1 to dreg2
  835. gen clr_w %2
  836. move_b %1, %2
  837. #endif
  838. #if TBL68881
  839. from data4 to FS_REG
  840. gen fmove_s %1, %2
  841. from FS_REG to datalt4
  842. gen fmove_s %1, %2
  843. #endif
  844. TESTS
  845. /* For the 68020 and m68k4, the extend1_4 will be extend1 */
  846. to test test_set4-(extend2+extend1+extend1_4)
  847. gen tst_l %1
  848. to test test_set2+extend2
  849. gen tst_w %1
  850. to test test_set1+extend1+extend1_4
  851. gen tst_b %1
  852. STACKINGRULES
  853. #if WORD_SIZE!=2
  854. from consts %num==0 to STACK
  855. gen clr_l {pre_dec4, sp}
  856. #else
  857. from zero_const4 to STACK
  858. gen clr_l {pre_dec4, sp}
  859. from consts %num==0 to STACK
  860. gen clr_w {pre_dec2, sp}
  861. #endif
  862. #ifndef TBL68020
  863. from t_regAregXcon sfit(%bd, 8) to STACK
  864. gen pea {regAregXcon, %1.reg, %1.xreg, 1, %1.bd}
  865. from t_regAregXcon to STACK
  866. gen pea {regAregXcon, %1.reg, %1.xreg, 1, 0}
  867. add_l {const4, %1.bd}, {indirect4, sp}
  868. from t_regAcon sfit(%bd, 16) to STACK
  869. gen pea {regAcon, %1.reg, %1.bd}
  870. from t_regAcon to STACK
  871. gen move_l %1.reg, {pre_dec4, sp}
  872. add_l {const4, %1.bd}, {indirect4, sp}
  873. #endif /* TBL68020 */
  874. from A_REG to STACK
  875. gen pea {indirect4, %1}
  876. from address - ext_addr to STACK
  877. gen pea %1
  878. from ext_addr to STACK
  879. gen pea {absolute4, %1.bd}
  880. #if WORD_SIZE!=2
  881. from consts to STACK
  882. gen pea {absolute4, %1.num}
  883. #else
  884. from sconsts4 to STACK
  885. gen pea {absolute4, %1.num}
  886. from const4 to STACK
  887. gen pea {absolute4, %1.num}
  888. #endif
  889. from any4 to STACK
  890. gen move_l %1, {pre_dec4, sp}
  891. #if WORD_SIZE!=2
  892. from any2 to STACK
  893. uses DD_REG
  894. gen clr_l %a
  895. move_w %1, {dreg2, %a}
  896. move_l %a, {pre_dec4, sp}
  897. from any2 to STACK
  898. gen clr_l {pre_dec4, sp}
  899. move_w %1, {offsetted2, sp, 2}
  900. #else
  901. from any2 to STACK
  902. gen move_w %1, {pre_dec2, sp}
  903. #endif
  904. from data1 to STACK
  905. uses DD_REG
  906. #if WORD_SIZE!=2
  907. gen clr_l %a
  908. move_b %1, {dreg1, %a}
  909. move_l %a, {pre_dec4, sp}
  910. #else
  911. gen clr_w %a
  912. move_b %1, {dreg1, %a}
  913. move_w %a, {pre_dec2, sp}
  914. #endif
  915. from data1 to STACK
  916. #if WORD_SIZE!=2
  917. gen clr_l {pre_dec4, sp}
  918. move_b %1, {offsetted1, sp, 3}
  919. #else
  920. gen clr_w {pre_dec2, sp}
  921. move_b %1, {offsetted1, sp, 1}
  922. #endif
  923. from extend2 to STACK
  924. gen ext_l %1.reg
  925. move_l %1.reg,{pre_dec4, sp}
  926. from extend1_4 to STACK
  927. #ifdef TBL68020
  928. gen extb_l %1.reg
  929. #else
  930. gen ext_w %1.reg
  931. ext_l %1.reg
  932. #endif
  933. move_l %1.reg,{pre_dec4, sp}
  934. #if WORD_SIZE==2
  935. from extend1 to STACK
  936. gen ext_w %1.reg
  937. move_w %1.reg,{pre_dec2, sp}
  938. #endif
  939. #ifdef TBL68020
  940. from regX to STACK
  941. gen pea %1
  942. #endif /* TBL68020 */
  943. /* This last stackingrule is never used: whenever regX is put on
  944. * the fakestack, some em-instuctions are left that remove it
  945. * immediately. However cgg complained about not having a
  946. * stackingrule for regX, so here it is
  947. */
  948. #if TBL68881
  949. from FS_REG to STACK
  950. gen fmove_s %1,{pre_dec4,sp}
  951. from FD_REG to STACK
  952. gen fmove_d %1,{pre_dec4,sp}
  953. #endif
  954. COERCIONS
  955. from STACK
  956. uses DD_REG4
  957. gen move_l {post_inc4, sp}, %a
  958. yields %a
  959. #if WORD_SIZE==2
  960. from STACK
  961. uses DD_REG
  962. gen move_w {post_inc2,sp}, %a
  963. yields %a
  964. #endif
  965. from STACK
  966. uses AA_REG
  967. gen move_l {post_inc4, sp}, %a
  968. yields %a
  969. #ifdef TBL68881
  970. from STACK
  971. uses FS_REG
  972. gen fmove_s {post_inc4, sp}, %a
  973. yields %a
  974. from STACK
  975. uses FD_REG
  976. gen fmove_d {post_inc4, sp}, %a
  977. yields %a
  978. #endif
  979. #ifndef TBL68020
  980. from t_regAregXcon sfit(%bd, 8)
  981. yields {regAregXcon, %1.reg, %1.xreg, 1, %1.bd}
  982. from t_regAregXcon
  983. uses AA_REG=%1.reg
  984. gen add_l {const4, %1.bd}, %a
  985. yields {regAregXcon, %a, %1.xreg, 1, 0}
  986. /*
  987. * The following coercions are necessary because the code generator
  988. * must be able to make the token from the real stack, otherwise the
  989. * coercion will not be made. Unfortunatly, inside a coercion, we are only
  990. * allowed to allocate 1 register, which means that there is no way to make
  991. * a regAregXcon from the stack, which, in its turn, means that the other
  992. * coercions will not be taken.
  993. *
  994. /*from STACK
  995. uses AA_REG, DD_REG4 = {zero_const4, 0}
  996. gen move_l {post_inc4, sp}, %a
  997. yields {regAregXcon, %a, %b, 1, 0}
  998. */
  999. from STACK
  1000. uses AA_REG
  1001. gen move_l {post_inc4, sp}, %a
  1002. yields {regAcon, %a, 0}
  1003. from t_regAcon sfit(%bd, 16)
  1004. yields {regAcon, %1.reg, %1.bd}
  1005. from t_regAcon
  1006. uses reusing %1, AA_REG=%1.reg
  1007. gen add_l {const4, %1.bd}, %a
  1008. yields %a
  1009. #endif /* TBL68020 */
  1010. #if WORD_SIZE==2
  1011. from regAregXcon %bd==0 && %sc==1
  1012. uses reusing %1, AA_REG = %1.reg
  1013. gen add_l {dreg4,%1.xreg},%a
  1014. yields %a
  1015. from regAregXcon %sc==1
  1016. uses reusing %1, AA_REG = %1.reg
  1017. gen add_l {dreg4, %1.xreg}, %a
  1018. yields {regAcon, %a, %1.bd}
  1019. #endif
  1020. #if WORD_SIZE==2
  1021. from sconsts
  1022. uses DD_REG4={const4, %1.num} /* uses moveq */
  1023. yields %a.1
  1024. #endif
  1025. #if WORD_SIZE==2
  1026. from any2
  1027. uses reusing %1, DD_REG = %1 yields %a
  1028. #endif
  1029. from any4
  1030. uses reusing %1, DD_REG4 = %1
  1031. yields %a
  1032. from any4
  1033. uses reusing %1, AA_REG = %1
  1034. yields %a
  1035. from t_address
  1036. uses reusing %1, AA_REG = %1
  1037. yields %a
  1038. #if TBL68881
  1039. from data4
  1040. uses reusing %1, FS_REG = %1
  1041. yields %a
  1042. #endif
  1043. from memory2
  1044. uses DD_REG
  1045. #if WORD_SIZE!=2
  1046. = {zero_const, 0}
  1047. #endif
  1048. gen move_w %1, %a yields %a
  1049. from memory1
  1050. uses DD_REG = {zero_const, 0}
  1051. gen move_b %1, %a yields %a
  1052. from memory2
  1053. uses DD_REG
  1054. gen move_w %1, %a yields {dreg2, %a}
  1055. from memory1
  1056. uses DD_REG
  1057. gen move_b %1, %a yields {dreg1, %a}
  1058. from extend2
  1059. gen ext_l %1.reg yields %1.reg
  1060. #if WORD_SIZE==2
  1061. from extend1
  1062. gen ext_w %1.reg yields %1.reg
  1063. #endif
  1064. from extend1_4
  1065. #ifdef TBL68020
  1066. gen extb_l %1.reg
  1067. #else
  1068. gen ext_w %1.reg
  1069. ext_l %1.reg
  1070. #endif
  1071. yields %1.reg
  1072. PATTERNS
  1073. /********************************
  1074. * First some longer patterns *
  1075. ********************************/
  1076. pat lol sbi stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1077. with any_int
  1078. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1079. gen sub_i %1, {LOCAL, $1}
  1080. neg_i {LOCAL, $1}
  1081. pat lol sbi stl $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_pointer
  1082. with conreg_int-bconst
  1083. kills all_indir, LOCAL %bd==$1
  1084. gen sub_i %1, {LOCAL, $1}
  1085. neg_i {LOCAL, $1}
  1086. pat lol sbu stl $1==$3 && $2==WORD_SIZE
  1087. leaving lol $1 sbi WORD_SIZE stl $1
  1088. pat lil sbi sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
  1089. with conreg_int-bconst
  1090. kills allexceptcon
  1091. gen sub_i %1, {indirect_int, regvar($1, reg_pointer)}
  1092. neg_i {indirect_int, regvar($1, reg_pointer)}
  1093. pat lil sbi sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
  1094. with conreg_int-bconst
  1095. kills allexceptcon
  1096. uses AA_REG = {DLOCAL, $1}
  1097. gen sub_i %1, {indirect_int, %a}
  1098. neg_i {indirect_int, %a}
  1099. pat lil sbu sil $1==$3 && $2==WORD_SIZE
  1100. leaving lil $1 sbi WORD_SIZE sil $1
  1101. proc lolrbitstl example lol ngi stl
  1102. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1103. gen bit* {LOCAL, $1}
  1104. pat lol ngi stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1105. call lolrbitstl(NEG_I)
  1106. pat lol com stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1107. call lolrbitstl(NOT_I)
  1108. proc lolbitstl example lol ngi stl
  1109. kills all_indir, LOCAL %bd==$1
  1110. gen bit* {LOCAL, $1}
  1111. pat lol ngi stl $1==$3 && $2==WORD_SIZE call lolbitstl(NEG_I)
  1112. pat lol com stl $1==$3 && $2==WORD_SIZE call lolbitstl(NOT_I)
  1113. #if WORD_SIZE==2
  1114. proc ldlbitsdl example ldl ngi sdl
  1115. kills all_indir, DLOCAL %bd==$1
  1116. gen bit* {DLOCAL, $1}
  1117. pat ldl ngi sdl $1==$3 && $2==4 call ldlbitsdl("neg.l")
  1118. pat ldl com sdl $1==$3 && $2==4 call ldlbitsdl("not.l")
  1119. #endif
  1120. proc loebitste example loe ngi ste
  1121. kills posextern
  1122. gen bit* {absolute_int, $1}
  1123. pat loe ngi ste $1==$3 && $2==WORD_SIZE call loebitste(NEG_I)
  1124. pat loe com ste $1==$3 && $2==WORD_SIZE call loebitste(NOT_I)
  1125. #if WORD_SIZE==2
  1126. proc ldebitsde example lde ngi sde
  1127. kills posextern
  1128. gen bit* {absolute4, $1}
  1129. pat lde ngi sde $1==$3 && $2==4 call ldebitsde("neg.l")
  1130. pat lde com sde $1==$3 && $2==4 call ldebitsde("not.l")
  1131. #endif
  1132. proc lilrbitsil example lil ngi sil
  1133. kills allexceptcon
  1134. gen bit* {indirect_int, regvar($1, reg_pointer)}
  1135. pat lil ngi sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
  1136. call lilrbitsil(NEG_I)
  1137. pat lil com sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
  1138. call lilrbitsil(NOT_I)
  1139. pat lil dec sil $1==$3 && inreg($1)==reg_pointer
  1140. call lilrbitsil(DEC)
  1141. pat lil inc sil $1==$3 && inreg($1)==reg_pointer
  1142. call lilrbitsil(INC)
  1143. proc lilbitsil example lil ngi sil
  1144. kills allexceptcon
  1145. #if TBL68020
  1146. gen bit* {ILOCAL, $1}
  1147. #else
  1148. uses AA_REG = {DLOCAL, $1}
  1149. gen bit* {indirect_int, %a}
  1150. #endif
  1151. pat lil ngi sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
  1152. call lilbitsil(NEG_I)
  1153. pat lil com sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
  1154. call lilbitsil(NOT_I)
  1155. pat lil dec sil $1==$3 && inreg($1)!=reg_any
  1156. call lilbitsil(DEC)
  1157. pat lil inc sil $1==$3 && inreg($1)!=reg_any
  1158. call lilbitsil(INC)
  1159. proc lolcshstl example lol loc sli stl
  1160. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1161. gen sh* {small_const, $2}, {LOCAL, $1}
  1162. pat lol loc sli stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
  1163. call lolcshstl(ASL_I)
  1164. pat lol loc sri stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
  1165. call lolcshstl(ASR_I)
  1166. pat lol loc slu stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
  1167. call lolcshstl(ASL_I)
  1168. pat lol loc sru stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
  1169. call lolcshstl(LSR_I)
  1170. pat lol loc rol stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
  1171. call lolcshstl(ROL_I)
  1172. pat lol loc ror stl $1==$4 && small($2) && $3==WORD_SIZE && inreg($1)==reg_any
  1173. call lolcshstl(ROR_I)
  1174. proc lolrshstl example lol lol sli stl
  1175. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1176. gen sh* {LOCAL, $2}, {LOCAL, $1}
  1177. pat lol lol sli stl $1==$4 && inreg($1)==reg_any && $3==WORD_SIZE
  1178. && inreg($2)==reg_any
  1179. call lolrshstl(ASL_I)
  1180. pat lol lol slu stl $1==$4 && inreg($1)==reg_any && $3==WORD_SIZE
  1181. && inreg($2)==reg_any
  1182. call lolrshstl(ASL_I)
  1183. pat lol lol sri stl $1==$4 && inreg($1)==reg_any && $3==WORD_SIZE
  1184. && inreg($2)==reg_any
  1185. call lolrshstl(ASR_I)
  1186. pat lol lol sru stl $1==$4 && inreg($1)==reg_any && $3==WORD_SIZE
  1187. && inreg($2)==reg_any
  1188. call lolrshstl(LSR_I)
  1189. pat lol lol rol stl $1==$4 && inreg($2)==reg_any && $3==WORD_SIZE
  1190. && inreg($1)==reg_any
  1191. call lolrshstl(ROL_I)
  1192. pat lol lol ror stl $1==$4 && inreg($2)==reg_any && $3==WORD_SIZE
  1193. && inreg($1)==reg_any
  1194. call lolrshstl(ROR_I)
  1195. #if WORD_SIZE!=2
  1196. proc lil1shlsil example lil loc sli sil /* only left */
  1197. kills allexceptcon
  1198. gen shw* {offsetted2, regvar($1, reg_pointer), 2}
  1199. roxl {indirect2, regvar($1, reg_pointer)}
  1200. pat lil loc sli sil $1==$4 && $2==1 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1201. call lil1shlsil("asl #1,")
  1202. pat lil loc slu sil $1==$4 && $2==1 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1203. call lil1shlsil("asl #1,")
  1204. proc lil1shrsil example lil loc sli sil /* only right */
  1205. kills allexceptcon
  1206. gen shw* {indirect2, regvar($1, reg_pointer)}
  1207. roxr {offsetted2, regvar($1, reg_pointer), 2}
  1208. pat lil loc sri sil $1==$4 && $2==1 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1209. call lil1shrsil("asr #1,")
  1210. pat lil loc sru sil $1==$4 && $2==1 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1211. call lil1shrsil("lsr #1,")
  1212. #endif
  1213. pat LLP lof inc LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1214. kills allexceptcon
  1215. gen add_i {const, 1}, {offsetted_int, regvar($1, reg_pointer), $2}
  1216. pat LLP lof dec LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1217. kills allexceptcon
  1218. gen sub_i {const, 1}, {offsetted_int, regvar($1, reg_pointer), $2}
  1219. /* the patterns with adp should use add_l */
  1220. pat LLP LFP adp LLP SFP $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1221. kills allexceptcon
  1222. gen add_l {const4, $3}, {offsetted4, regvar($1, reg_pointer), $2}
  1223. pat LEP LFP adp LEP SFP $1==$4 && $2==$5
  1224. kills allexceptcon
  1225. #if TBL68020 && FANCY_MODES
  1226. gen add_l {const4, $3}, {ABS_off4, $1, $2}
  1227. #else
  1228. uses AA_REG={absolute4, $1}
  1229. gen add_l {const4, $3}, {offsetted4, %a, $2}
  1230. #endif
  1231. pat LEP loi adp LEP sti $1==$4 && $2==4 && $5==4
  1232. kills allexceptcon
  1233. #if TBL68020 && FANCY_MODES
  1234. gen add_l {const4, $3}, {ABS_off4, $1, 0}
  1235. #else
  1236. uses AA_REG={absolute4, $1}
  1237. gen add_l {const4, $3}, {indirect4, %a}
  1238. #endif
  1239. #if WORD_SIZE!=2
  1240. pat lil lof adp lil stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1241. kills allexceptcon
  1242. #if TBL68020 && FANCY_MODES
  1243. gen add_l {const4, $3}, {OFF_off4, regvar($1, reg_pointer), 0, $2}
  1244. #else
  1245. uses AA_REG={indirect4, regvar($1, reg_pointer)}
  1246. gen add_l {const4, $3}, {offsetted4, %a, $2}
  1247. #endif
  1248. pat lil loi adp lil sti $1==$4 && $2==4 && $5==4 && inreg($1)==reg_pointer
  1249. kills allexceptcon
  1250. #if TBL68020 && FANCY_MODES
  1251. gen add_l {const4, $3}, {OFF_off4, regvar($1, reg_pointer), 0, 0}
  1252. #else
  1253. uses AA_REG={indirect4, regvar($1, reg_pointer)}
  1254. gen add_l {const4, $3}, {indirect4, %a}
  1255. #endif
  1256. #endif /* WORD_SIZE==2 */
  1257. pat lol inl $1==$2 && inreg($1)==reg_any
  1258. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1259. uses DD_REG = {LOCAL, $1}
  1260. gen add_i {const, 1}, {LOCAL, $1}
  1261. killreg %a
  1262. yields %a
  1263. pat lol del $1==$2 && inreg($1)==reg_any
  1264. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1265. uses DD_REG = {LOCAL, $1}
  1266. gen sub_i {const, 1}, {LOCAL, $1}
  1267. killreg %a
  1268. yields %a
  1269. /* the following rules are for unsigneds, since del and inl work on ints */
  1270. pat lol loc lol adu stl $1==$3 && $3==$5 && $4==WORD_SIZE && inreg($1)==reg_any
  1271. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1272. uses DD_REG = {LOCAL, $1}
  1273. gen add_i {const, $2}, {LOCAL, $1}
  1274. killreg %a
  1275. yields %a
  1276. pat lol loc lol adu stl $1==$3 && $3==$5 && $4==WORD_SIZE
  1277. kills all_indir, LOCAL %bd==$1
  1278. uses DD_REG = {LOCAL, $1}
  1279. gen add_i {const, $2}, {LOCAL, $1}
  1280. killreg %a
  1281. yields %a
  1282. pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE && inreg($1)==reg_any
  1283. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1284. uses DD_REG = {LOCAL, $1}
  1285. gen sub_i {const, $3}, {LOCAL, $1}
  1286. killreg %a
  1287. yields %a
  1288. pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
  1289. kills all_indir, LOCAL %bd==$1
  1290. uses DD_REG = {LOCAL, $1}
  1291. gen sub_i {const, $3}, {LOCAL, $1}
  1292. killreg %a
  1293. yields %a
  1294. pat loe loc loe adu ste $1==$3 && $3==$5 && $4==WORD_SIZE
  1295. kills posextern
  1296. uses DD_REG = {absolute_int, $1}
  1297. gen add_i {const,$2}, {absolute_int, $1}
  1298. killreg %a
  1299. yields %a
  1300. pat loe dup loc sbu ste $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
  1301. kills posextern
  1302. uses DD_REG = {absolute_int, $1}
  1303. gen sub_i {const,$3}, {absolute_int, $1}
  1304. killreg %a
  1305. yields %a
  1306. pat lil loc lil adu sil $1==$3 && $3==$5 && $4==WORD_SIZE
  1307. && inreg($1)==reg_pointer
  1308. kills allexceptcon
  1309. uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
  1310. gen add_i {const, $2}, {indirect_int, regvar($1, reg_pointer)}
  1311. killreg %a
  1312. yields %a
  1313. pat lil dup loc sbu sil $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
  1314. && inreg($1)==reg_pointer
  1315. kills allexceptcon
  1316. uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
  1317. gen sub_i {const, $3}, {indirect_int, regvar($1, reg_pointer)}
  1318. killreg %a
  1319. yields %a
  1320. proc lolxxstl example lol and stl
  1321. with data_int-bconst
  1322. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1323. gen xxx* %1, {LOCAL, $1}
  1324. pat lol adi stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1325. call lolxxstl(ADD_I)
  1326. pat lol adu stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1327. call lolxxstl(ADD_I)
  1328. pat lol and stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1329. call lolxxstl(AND_I)
  1330. pat lol ior stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1331. call lolxxstl(OR_I)
  1332. pat lol xor stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1333. with conreg_int-bconst
  1334. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1335. gen eor_i %1, {LOCAL, $1}
  1336. #if TBL68020 || WORD_SIZE==2
  1337. pat lol mli stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1338. with data_int
  1339. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1340. gen muls_i %1, {LOCAL, $1}
  1341. pat lol mlu stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
  1342. with data_int
  1343. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1344. gen mulu_i %1, {LOCAL, $1}
  1345. #endif /* TBL68020 */
  1346. proc lolxxxstl example lol adi stl
  1347. with conreg_int-bconst
  1348. kills all_indir, LOCAL %bd==$1
  1349. gen xxx* %1, {LOCAL, $1}
  1350. pat lol adi stl $1==$3 && $2==WORD_SIZE call lolxxxstl(ADD_I)
  1351. pat lol adu stl $1==$3 && $2==WORD_SIZE call lolxxxstl(ADD_I)
  1352. pat lol and stl $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_pointer
  1353. call lolxxxstl(AND_I)
  1354. pat lol ior stl $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_pointer
  1355. call lolxxxstl(OR_I)
  1356. pat lol xor stl $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_pointer
  1357. call lolxxxstl(EOR_I)
  1358. #if WORD_SIZE==2
  1359. proc ldlxxxsdl example lol adi stl
  1360. with conreg4-bconst4
  1361. kills all_indir, DLOCAL %bd==$1
  1362. gen xxx* %1, {DLOCAL, $1}
  1363. pat ldl adi sdl $1==$3 && $2==4 call ldlxxxsdl("add.l")
  1364. pat ldl adu sdl $1==$3 && $2==4 call ldlxxxsdl("add.l")
  1365. pat ldl and sdl $1==$3 && $2==4 && inreg($1)!=reg_pointer
  1366. call ldlxxxsdl("and.l")
  1367. pat ldl ior sdl $1==$3 && $2==4 && inreg($1)!=reg_pointer
  1368. call ldlxxxsdl("or.l")
  1369. pat ldl xor sdl $1==$3 && $2==4 && inreg($1)!=reg_pointer
  1370. call ldlxxxsdl("eor.l")
  1371. #endif
  1372. proc lilxxsil example lil and sil
  1373. with conreg_int-bconst
  1374. kills allexceptcon
  1375. gen xxx* %1, {indirect_int, regvar($1, reg_pointer)}
  1376. pat lil adi sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
  1377. call lilxxsil(ADD_I)
  1378. pat lil adu sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
  1379. call lilxxsil(ADD_I)
  1380. pat lil and sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
  1381. call lilxxsil(AND_I)
  1382. pat lil ior sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
  1383. call lilxxsil(OR_I)
  1384. pat lil xor sil $1==$3 && $2==WORD_SIZE && inreg($1)==reg_pointer
  1385. call lilxxsil(EOR_I)
  1386. #if WORD_SIZE!=2
  1387. pat lil ads sil $1==$3 && $2==4 && inreg($1)==reg_pointer
  1388. call lilxxsil("add.l")
  1389. #endif
  1390. proc lilxxxsil example lil adi sil
  1391. with conreg_int-bconst
  1392. kills allexceptcon
  1393. #if TBL68020
  1394. gen xxx* %1, {ILOCAL, $1}
  1395. #else
  1396. uses AA_REG = {DLOCAL, $1}
  1397. gen xxx* %1, {indirect_int, %a}
  1398. #endif
  1399. pat lil adi sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
  1400. call lilxxxsil(ADD_I)
  1401. pat lil adu sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
  1402. call lilxxxsil(ADD_I)
  1403. pat lil and sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
  1404. call lilxxxsil(AND_I)
  1405. pat lil ior sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
  1406. call lilxxxsil(OR_I)
  1407. pat lil xor sil $1==$3 && $2==WORD_SIZE && inreg($1)!=reg_any
  1408. call lilxxxsil(EOR_I)
  1409. #if WORD_SIZE!=2
  1410. pat lil ads sil $1==$3 && $2==4 && inreg($1)!=reg_any
  1411. call lilxxxsil("add.l")
  1412. #endif
  1413. proc loexxxste example loe adi ste
  1414. with conreg_int-bconst
  1415. kills posextern
  1416. gen xxx* %1, {absolute_int, $1}
  1417. pat loe adi ste $1==$3 && $2==WORD_SIZE call loexxxste(ADD_I)
  1418. pat loe adu ste $1==$3 && $2==WORD_SIZE call loexxxste(ADD_I)
  1419. pat loe and ste $1==$3 && $2==WORD_SIZE call loexxxste(AND_I)
  1420. pat loe ior ste $1==$3 && $2==WORD_SIZE call loexxxste(OR_I)
  1421. pat loe xor ste $1==$3 && $2==WORD_SIZE call loexxxste(EOR_I)
  1422. #if WORD_SIZE!=2
  1423. pat loe ads ste $1==$3 && $2==4 call loexxxste("add.l")
  1424. #endif
  1425. #if WORD_SIZE==2
  1426. proc ldexxxsde example lde adi sde
  1427. with conreg4-bconst4
  1428. kills posextern
  1429. gen xxx* %1, {absolute4, $1}
  1430. pat lde adi sde $1==$3 && $2==4 call ldexxxsde("add.l")
  1431. pat lde adu sde $1==$3 && $2==4 call ldexxxsde("add.l")
  1432. pat lde and sde $1==$3 && $2==4 call ldexxxsde("and.l")
  1433. pat lde ior sde $1==$3 && $2==4 call ldexxxsde("or.l")
  1434. pat lde xor sde $1==$3 && $2==4 call ldexxxsde("eor.l")
  1435. #endif
  1436. proc lollilxxxstl example lol lil adi stl
  1437. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1438. gen xxx* {indirect_int, regvar($2, reg_pointer)}, {LOCAL, $1}
  1439. pat lol lil adi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1440. && inreg($2)==reg_pointer
  1441. call lollilxxxstl(ADD_I)
  1442. pat lol lil adu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1443. && inreg($2)==reg_pointer
  1444. call lollilxxxstl(ADD_I)
  1445. pat lol lil sbi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1446. && inreg($2)==reg_pointer
  1447. call lollilxxxstl(SUB_I)
  1448. pat lol lil sbu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1449. && inreg($2)==reg_pointer
  1450. call lollilxxxstl(SUB_I)
  1451. pat lol lil and stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1452. && inreg($2)==reg_pointer
  1453. call lollilxxxstl(AND_I)
  1454. pat lol lil ior stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1455. && inreg($2)==reg_pointer
  1456. call lollilxxxstl(OR_I)
  1457. proc lollfixxxstl example lol LLP lof adi stl
  1458. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1459. gen xxx* {offsetted_int, regvar($2, reg_pointer), $3}, {LOCAL, $1}
  1460. pat lol LLP lof adi stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
  1461. && inreg($2)==reg_pointer
  1462. call lollfixxxstl(ADD_I)
  1463. pat lol LLP lof adu stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
  1464. && inreg($2)==reg_pointer
  1465. call lollfixxxstl(ADD_I)
  1466. pat lol LLP lof sbi stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
  1467. && inreg($2)==reg_pointer
  1468. call lollfixxxstl(SUB_I)
  1469. pat lol LLP lof sbu stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
  1470. && inreg($2)==reg_pointer
  1471. call lollfixxxstl(SUB_I)
  1472. pat lol LLP lof and stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
  1473. && inreg($2)==reg_pointer
  1474. call lollfixxxstl(AND_I)
  1475. pat lol LLP lof ior stl $1==$5 && $4==WORD_SIZE && inreg($1)==reg_any
  1476. && inreg($2)==reg_pointer
  1477. call lollfixxxstl(OR_I)
  1478. proc lolfrxlolf example LLP lof and LLP stf
  1479. with conreg_int-bconst
  1480. kills allexceptcon
  1481. gen xxx* %1, {offsetted_int, regvar($1, reg_pointer), $2}
  1482. pat LLP lof adi LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1483. && inreg($1)==reg_pointer
  1484. call lolfrxlolf(ADD_I)
  1485. pat LLP lof adu LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1486. && inreg($1)==reg_pointer
  1487. call lolfrxlolf(ADD_I)
  1488. pat LLP lof and LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1489. && inreg($1)==reg_pointer
  1490. call lolfrxlolf(AND_I)
  1491. pat LLP lof ior LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1492. && inreg($1)==reg_pointer
  1493. call lolfrxlolf(OR_I)
  1494. pat LLP lof xor LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1495. && inreg($1)==reg_pointer
  1496. call lolfrxlolf(EOR_I)
  1497. #if WORD_SIZE!=2
  1498. pat LLP lof ads LLP stf $1==$4 && $2==$5 && $3==4
  1499. && inreg($1)==reg_pointer
  1500. call lolfrxlolf("add.l")
  1501. #endif
  1502. proc lolfxxlolf example LLP lof and LLP stf
  1503. with conreg_int-bconst
  1504. kills allexceptcon
  1505. #if TBL68020 && FANCY_MODES
  1506. gen xxx* %1, {OFF_off_int, lb, $1, $2}
  1507. #else
  1508. uses AA_REG={DLOCAL, $1}
  1509. gen xxx* %1, {offsetted_int, %a, $2}
  1510. #endif
  1511. pat LLP lof adi LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1512. call lolfxxlolf(ADD_I)
  1513. pat LLP lof adu LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1514. call lolfxxlolf(ADD_I)
  1515. pat LLP lof and LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1516. call lolfxxlolf(AND_I)
  1517. pat LLP lof ior LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1518. call lolfxxlolf(OR_I)
  1519. pat LLP lof xor LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1520. call lolfxxlolf(EOR_I)
  1521. #if WORD_SIZE!=2
  1522. pat LLP lof ads LLP stf $1==$4 && $2==$5 && $3==4
  1523. call lolfxxlolf("add.l")
  1524. #endif
  1525. #if WORD_SIZE!=2
  1526. proc lilfxxlilf example lil lof and lil stf
  1527. with conreg_int-bconst
  1528. kills allexceptcon
  1529. #if TBL68020 && FANCY_MODES
  1530. gen xxx* %1, {OFF_off4, regvar($1, reg_pointer), 0, $2}
  1531. #else
  1532. uses AA_REG={indirect4, regvar($1, reg_pointer)}
  1533. gen xxx* %1, {offsetted_int, %a, $2}
  1534. #endif
  1535. pat lil lof adi lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
  1536. call lilfxxlilf("add.l")
  1537. pat lil lof adu lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
  1538. call lilfxxlilf("add.l")
  1539. pat lil lof and lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
  1540. call lilfxxlilf("and.l")
  1541. pat lil lof ior lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
  1542. call lilfxxlilf("or.l")
  1543. pat lil lof xor lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
  1544. call lilfxxlilf("eor.l")
  1545. pat lil lof ads lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
  1546. call lilfxxlilf("add.l")
  1547. #endif
  1548. proc lefxxxsef example loe lof and loe stf
  1549. with conreg_int-bconst
  1550. kills allexceptcon
  1551. #if TBL68020 && FANCY_MODES
  1552. gen xxx* %1, {ABS_off_int, $1, $2}
  1553. #else
  1554. uses AA_REG={absolute4, $1}
  1555. gen xxx* %1, {offsetted_int, %a, $2}
  1556. #endif
  1557. pat LEP lof adi LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1558. call lefxxxsef(ADD_I)
  1559. pat LEP lof adu LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1560. call lefxxxsef(ADD_I)
  1561. pat LEP lof and LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1562. call lefxxxsef(AND_I)
  1563. pat LEP lof ior LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1564. call lefxxxsef(OR_I)
  1565. pat LEP lof xor LEP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1566. call lefxxxsef(EOR_I)
  1567. #if WORD_SIZE!=2
  1568. pat LEP lof ads LEP stf $1==$4 && $2==$5 && $3==4
  1569. call lefxxxsef("add.l")
  1570. #endif
  1571. /* lil gets a word, not necessarily a pointer */
  1572. #if WORD_SIZE!=2
  1573. proc lilixxlili example lil loi and lil sti
  1574. with conreg_int-bconst
  1575. kills allexceptcon
  1576. #if TBL68020 && FANCY_MODES
  1577. gen xxx* %1, {OFF_off4, regvar($1, reg_pointer), 0, 0}
  1578. #else
  1579. uses AA_REG={indirect4, regvar($1, reg_pointer)}
  1580. gen xxx* %1, {indirect4, %a}
  1581. #endif
  1582. pat lil loi adi lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
  1583. && inreg($1)==reg_pointer
  1584. call lilixxlili("add.l")
  1585. pat lil loi adu lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
  1586. && inreg($1)==reg_pointer
  1587. call lilixxlili("add.l")
  1588. pat lil loi and lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
  1589. && inreg($1)==reg_pointer
  1590. call lilixxlili("and.l")
  1591. pat lil loi ior lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
  1592. && inreg($1)==reg_pointer
  1593. call lilixxlili("or.l")
  1594. pat lil loi xor lil sti $1==$4 && $2==$3 && $2==$5 && $2==4
  1595. && inreg($1)==reg_pointer
  1596. call lilixxlili("eor.l")
  1597. pat lil loi ads lil sti $1==$4 && $2==$3 && $2==$5 && $3==4
  1598. && inreg($1)==reg_pointer
  1599. call lilixxlili("add.l")
  1600. #endif
  1601. proc leixxxsei example loe loi and loe sti
  1602. with conreg_int-bconst
  1603. kills allexceptcon
  1604. #if TBL68020 && FANCY_MODES
  1605. gen xxx* %1, {ABS_off_int, $1, 0}
  1606. #else
  1607. uses AA_REG={absolute4, $1}
  1608. gen xxx* %1, {indirect_int, %a}
  1609. #endif
  1610. pat LEP loi adi LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
  1611. call leixxxsei(ADD_I)
  1612. pat LEP loi adu LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
  1613. call leixxxsei(ADD_I)
  1614. pat LEP loi and LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
  1615. call leixxxsei(AND_I)
  1616. pat LEP loi ior LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
  1617. call leixxxsei(OR_I)
  1618. pat LEP loi xor LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
  1619. call leixxxsei(EOR_I)
  1620. #if WORD_SIZE!=2
  1621. pat LEP loi ads LEP sti $1==$4 && $2==$3 && $2==$5 && $2==4
  1622. call leixxxsei("add.l")
  1623. #endif
  1624. proc lofruxxsof example LLP lof inc LLP stf
  1625. kills allexceptcon
  1626. gen bit* {offsetted_int, regvar($1, reg_pointer), $2}
  1627. pat LLP lof inc LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1628. call lofruxxsof(INC)
  1629. pat LLP lof dec LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1630. call lofruxxsof(DEC)
  1631. pat LLP lof ngi LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1632. && $3==WORD_SIZE
  1633. call lofruxxsof(NEG_I)
  1634. pat LLP lof com LLP stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1635. && $3==WORD_SIZE
  1636. call lofruxxsof(NOT_I)
  1637. proc lofuxxsof example LLP lof inc LLP stf
  1638. kills allexceptcon
  1639. #if TBL68020 && FANCY_MODES
  1640. gen bit* {OFF_off_int, lb, $1, $2}
  1641. #else
  1642. uses AA_REG={DLOCAL,$1}
  1643. gen bit* {offsetted_int,%a,$2}
  1644. #endif
  1645. pat LLP lof inc LLP stf $1==$4 && $2==$5
  1646. call lofuxxsof(INC)
  1647. pat LLP lof dec LLP stf $1==$4 && $2==$5
  1648. call lofuxxsof(DEC)
  1649. pat LLP lof ngi LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1650. call lofuxxsof(NEG_I)
  1651. pat LLP lof com LLP stf $1==$4 && $2==$5 && $3==WORD_SIZE
  1652. call lofuxxsof(NOT_I)
  1653. #if WORD_SIZE!=2
  1654. proc lifuxxsif example lil lof inc lil stf
  1655. kills allexceptcon
  1656. #if TBL68020 && FANCY_MODES
  1657. gen bit* {OFF_off4, regvar($1, reg_pointer), 0, $2}
  1658. #else
  1659. uses AA_REG={indirect4, regvar($1, reg_pointer)}
  1660. gen bit* {offsetted4,%a,$2}
  1661. #endif
  1662. pat lil lof inc lil stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1663. call lifuxxsif("add.l #1,")
  1664. pat lil lof dec lil stf $1==$4 && $2==$5 && inreg($1)==reg_pointer
  1665. call lifuxxsif("sub.l #1,")
  1666. pat lil lof ngi lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
  1667. call lifuxxsif("neg.l")
  1668. pat lil lof com lil stf $1==$4 && $2==$5 && $3==4 && inreg($1)==reg_pointer
  1669. call lifuxxsif("not.l")
  1670. #endif
  1671. #if WORD_SIZE!=2
  1672. proc liiuxxsii example lil loi inc lil sti
  1673. kills allexceptcon
  1674. #if TBL68020 && FANCY_MODES
  1675. gen bit* {OFF_off4, regvar($1, reg_pointer), 0, 0}
  1676. #else
  1677. uses AA_REG={indirect4, regvar($1, reg_pointer)}
  1678. gen bit* {indirect4, %a}
  1679. #endif
  1680. pat lil loi inc lil sti $1==$4 && $2==4 && $5==4 && inreg($1)==reg_pointer
  1681. call liiuxxsii("add.l #1,")
  1682. pat lil loi dec lil sti $1==$4 && $2==4 && $5==4 && inreg($1)==reg_pointer
  1683. call liiuxxsii("sub.l #1,")
  1684. pat lil loi ngi lil sti $1==$4 && $2==4 && $5==4 && $3==4 && inreg($1)==reg_pointer
  1685. call liiuxxsii("neg.l")
  1686. pat lil loi com lil sti $1==$4 && $2==4 && $5==4 && $3==4 && inreg($1)==reg_pointer
  1687. call liiuxxsii("not.l")
  1688. #endif
  1689. proc lefuxxsef example loe lof inc loe stf
  1690. kills allexceptcon
  1691. #if TBL68020 && FANCY_MODES
  1692. gen bit* {ABS_off_int, $1, $2}
  1693. #else
  1694. uses AA_REG={absolute4, $1}
  1695. gen bit* {offsetted_int, %a, $2}
  1696. #endif
  1697. pat LEP lof inc LEP stf $1==$4 && $2==$5
  1698. call lefuxxsef(INC)
  1699. pat LEP lof dec LEP stf $1==$4 && $2==$5
  1700. call lefuxxsef(DEC)
  1701. pat LEP lof ngi LEP stf $1==$4 && $2==$5 && $3==4
  1702. call lefuxxsef(NEG_I)
  1703. pat LEP lof com LEP stf $1==$4 && $2==$5 && $3==4
  1704. call lefuxxsef(NOT_I)
  1705. proc leiuxxsei example loe loi inc loe sti
  1706. kills allexceptcon
  1707. #if TBL68020 && FANCY_MODES
  1708. gen bit* {ABS_off_int, $1, 0}
  1709. #else
  1710. uses AA_REG={absolute4, $1}
  1711. gen bit* {indirect_int, %a}
  1712. #endif
  1713. pat LEP loi inc LEP sti $1==$4 && $2==$5 && $2==WORD_SIZE
  1714. call leiuxxsei(INC)
  1715. pat LEP loi dec LEP sti $1==$4 && $2==$5 && $2==WORD_SIZE
  1716. call leiuxxsei(DEC)
  1717. pat LEP loi ngi LEP sti $1==$4 && $2==$3 && $2==$5 && $2==WORD_SIZE
  1718. call leiuxxsei(NEG_I)
  1719. pat LEP loi com LEP sti $1==$4 && $2==$3 && 2==$5 && $2==WORD_SIZE
  1720. call leiuxxsei(NOT_I)
  1721. proc lolcxxstl example lol loc and stl
  1722. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1723. gen xxx* {const, $2}, {LOCAL, $1}
  1724. /*
  1725. pat lol loc adi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1726. call lolcxxstl(ADD_I)
  1727. pat lol loc adu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1728. call lolcxxstl(ADD_I)
  1729. peephole optimizer replaces these
  1730. */
  1731. pat lol loc sbi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1732. call lolcxxstl(SUB_I)
  1733. pat lol loc sbu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1734. call lolcxxstl(SUB_I)
  1735. /*
  1736. pat lol loc and stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1737. call lolcxxstl(AND_I)
  1738. pat lol loc ior stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1739. call lolcxxstl(OR_I)
  1740. pat lol loc xor stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1741. call lolcxxstl(EOR_I)
  1742. peephole optimizer replaces these
  1743. */
  1744. #if TBL68020 || WORDSIZE==2
  1745. #if WORD_SIZE==4
  1746. pat lol loc dvi stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1747. call lolcxxstl(DIVS_I)
  1748. pat lol loc dvu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1749. call lolcxxstl(DIVU_I)
  1750. #endif
  1751. pat lol loc mli stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1752. call lolcxxstl(MULS_I)
  1753. pat lol loc mlu stl $1==$4 && $3==WORD_SIZE && inreg($1)==reg_any
  1754. call lolcxxstl(MULU_I)
  1755. #endif
  1756. proc lolcxxxstl example lol loc adi stl
  1757. kills all_indir, LOCAL %bd==$1
  1758. gen xxx* {const, $2}, {LOCAL, $1}
  1759. /*
  1760. pat lol loc adi stl $1==$4 && $3==WORD_SIZE call lolcxxxstl(ADD_I)
  1761. pat lol loc adu stl $1==$4 && $3==WORD_SIZE call lolcxxxstl(ADD_I)
  1762. peephole optimizer replaces these
  1763. */
  1764. pat lol loc sbi stl $1==$4 && $3==WORD_SIZE call lolcxxxstl(SUB_I)
  1765. pat lol loc sbu stl $1==$4 && $3==WORD_SIZE call lolcxxxstl(SUB_I)
  1766. /*
  1767. pat lol loc and stl $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_pointer
  1768. call lolcxxxstl(AND_I)
  1769. pat lol loc ior stl $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_pointer
  1770. call lolcxxxstl(OR_I)
  1771. pat lol loc xor stl $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_pointer
  1772. call lolcxxxstl(EOR_I)
  1773. peephole optimizer replaces these
  1774. */
  1775. #if WORD_SIZE==2
  1776. proc ldlcxxxsdl example ldl ldc adi sdl
  1777. kills all_indir, DLOCAL %bd==$1
  1778. gen xxx* {const4, $2}, {DLOCAL, $1}
  1779. pat ldl ldc sbi sdl $1==$4 && $3==4 call ldlcxxxsdl("sub.l")
  1780. pat ldl ldc sbu sdl $1==$4 && $3==4 call ldlcxxxsdl("sub.l")
  1781. #endif
  1782. proc lilcxxsil example lil loc and sil
  1783. kills allexceptcon
  1784. gen xxx* {const, $2}, {indirect_int, regvar($1, reg_pointer)}
  1785. pat lil loc adi sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1786. call lilcxxsil(ADD_I)
  1787. pat lil loc adu sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1788. call lilcxxsil(ADD_I)
  1789. pat lil loc sbi sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1790. call lilcxxsil(SUB_I)
  1791. pat lil loc sbu sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1792. call lilcxxsil(SUB_I)
  1793. pat lil loc and sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1794. call lilcxxsil(AND_I)
  1795. pat lil loc ior sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1796. call lilcxxsil(OR_I)
  1797. pat lil loc xor sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
  1798. call lilcxxsil(EOR_I)
  1799. proc lilcxxxsil example lil loc adi sil
  1800. kills allexceptcon
  1801. #if TBL68020
  1802. gen xxx* {const, $2}, {ILOCAL, $1}
  1803. #else
  1804. uses AA_REG = {DLOCAL, $1}
  1805. gen xxx* {const, $2}, {indirect_int, %a}
  1806. #endif
  1807. pat lil loc adi sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
  1808. call lilcxxxsil(ADD_I)
  1809. pat lil loc adu sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
  1810. call lilcxxxsil(ADD_I)
  1811. pat lil loc sbi sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
  1812. call lilcxxxsil(SUB_I)
  1813. pat lil loc sbu sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
  1814. call lilcxxxsil(SUB_I)
  1815. pat lil loc and sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
  1816. call lilcxxxsil(AND_I)
  1817. pat lil loc ior sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
  1818. call lilcxxxsil(OR_I)
  1819. pat lil loc xor sil $1==$4 && $3==WORD_SIZE && inreg($1)!=reg_any
  1820. call lilcxxxsil(EOR_I)
  1821. proc loecxxxste example loe loc adi ste
  1822. kills posextern
  1823. gen xxx* {const, $2}, {absolute4, $1}
  1824. /*
  1825. pat loe loc adi ste $1==$4 && $3==WORD_SIZE call loecxxxste(ADD_I)
  1826. pat loe loc adu ste $1==$4 && $3==WORD_SIZE call loecxxxste(ADD_I)
  1827. peephole optimizer replaces these
  1828. */
  1829. pat loe loc sbi ste $1==$4 && $3==WORD_SIZE call loecxxxste(SUB_I)
  1830. pat loe loc sbu ste $1==$4 && $3==WORD_SIZE call loecxxxste(SUB_I)
  1831. /*
  1832. pat loe loc and ste $1==$4 && $3==WORD_SIZE call loecxxxste(AND_I)
  1833. pat loe loc ior ste $1==$4 && $3==WORD_SIZE call loecxxxste(OR_I)
  1834. pat loe loc xor ste $1==$4 && $3==WORD_SIZE call loecxxxste(EOR_I)
  1835. peephole optimizer replaces these
  1836. */
  1837. proc lolrxxstl example lol lol and stl
  1838. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  1839. gen xxx* {LOCAL, $2}, {LOCAL, $1}
  1840. /*
  1841. pat lol lol adi stl $1==$4 && $3==WORD_SIZE
  1842. && inreg($1)==reg_any && inreg($2)==reg_any
  1843. call lolrxxstl(ADD_I)
  1844. pat lol lol adu stl $1==$4 && $3==WORD_SIZE
  1845. && inreg($1)==reg_any && inreg($2)==reg_any
  1846. call lolrxxstl(ADD_I)
  1847. peephole optimizer replaces these
  1848. */
  1849. pat lol lol sbi stl $1==$4 && $3==WORD_SIZE
  1850. && inreg($1)==reg_any && inreg($2)==reg_any
  1851. call lolrxxstl(SUB_I)
  1852. pat lol lol sbu stl $1==$4 && $3==WORD_SIZE
  1853. && inreg($1)==reg_any && inreg($2)==reg_any
  1854. call lolrxxstl(SUB_I)
  1855. /*
  1856. pat lol lol and stl $1==$4 && $3==WORD_SIZE
  1857. && inreg($1)==reg_any && inreg($2)==reg_any
  1858. call lolrxxstl(AND_I)
  1859. pat lol lol ior stl $1==$4 && $3==WORD_SIZE
  1860. && inreg($1)==reg_any && inreg($2)==reg_any
  1861. call lolrxxstl(OR_I)
  1862. pat lol lol xor stl $1==$4 && $3==WORD_SIZE
  1863. && inreg($1)==reg_any && inreg($2)==reg_any
  1864. call lolrxxstl(EOR_I)
  1865. peephole optimizer replaces these
  1866. */
  1867. proc lolrxxxstl example lol lol adi stl
  1868. kills all_indir, LOCAL %bd==$1
  1869. gen xxx* {LOCAL, $2}, {LOCAL, $1}
  1870. /*
  1871. pat lol lol adi stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1872. call lolrxxxstl(ADD_I)
  1873. pat lol lol adu stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1874. call lolrxxxstl(ADD_I)
  1875. peephole optimizer replaces these
  1876. */
  1877. #if WORD_SIZE!=2
  1878. pat lol lol ads stl $1==$4 && $3==4 && inreg($2)==reg_any
  1879. call lolrxxxstl("add.l")
  1880. #endif
  1881. pat lol lol sbi stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1882. call lolrxxxstl(SUB_I)
  1883. pat lol lol sbu stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1884. call lolrxxxstl(SUB_I)
  1885. /*
  1886. pat lol lol and stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any && inreg($1)!=reg_pointer
  1887. call lolrxxxstl(AND_I)
  1888. pat lol lol ior stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any &&
  1889. inreg($1)!=reg_pointer
  1890. call lolrxxxstl(OR_I)
  1891. pat lol lol xor stl $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any &&
  1892. inreg($1)!=reg_pointer
  1893. call lolrxxxstl(EOR_I)
  1894. peephole optimizer replaces these
  1895. */
  1896. proc lilrxxsil example lil lol and sil
  1897. kills allexceptcon
  1898. gen xxx* {LOCAL, $2}, {indirect_int, regvar($1, reg_pointer)}
  1899. pat lil lol adi sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
  1900. inreg($2)==reg_any
  1901. call lilrxxsil(ADD_I)
  1902. pat lil lol adu sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
  1903. inreg($2)==reg_any
  1904. call lilrxxsil(ADD_I)
  1905. pat lil lol sbi sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
  1906. inreg($2)==reg_any
  1907. call lilrxxsil(SUB_I)
  1908. pat lil lol sbu sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
  1909. inreg($2)==reg_any
  1910. call lilrxxsil(SUB_I)
  1911. pat lil lol and sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
  1912. inreg($2)==reg_any
  1913. call lilrxxsil(AND_I)
  1914. pat lil lol ior sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
  1915. inreg($2)==reg_any
  1916. call lilrxxsil(OR_I)
  1917. pat lil lol xor sil $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer &&
  1918. inreg($2)==reg_any
  1919. call lilrxxsil(EOR_I)
  1920. #if WORD_SIZE!=2
  1921. pat lil lol ads sil $1==$4 && $3==4 && inreg($1)==reg_pointer &&
  1922. inreg($2)==reg_any
  1923. call lilrxxsil("add.l")
  1924. #endif
  1925. proc lilrxxxsil example lil lol adi sil
  1926. kills allexceptcon
  1927. #if TBL68020
  1928. gen xxx* {LOCAL, $2}, {ILOCAL, $1}
  1929. #else
  1930. uses AA_REG = {DLOCAL, $1}
  1931. gen xxx* {LOCAL, $2}, {indirect_int, %a}
  1932. #endif
  1933. pat lil lol adi sil $1==$4 && $3==WORD_SIZE
  1934. && inreg($2)==reg_any && inreg($1)!=reg_any
  1935. call lilrxxxsil(ADD_I)
  1936. pat lil lol adu sil $1==$4 && $3==WORD_SIZE
  1937. && inreg($2)==reg_any && inreg($1)!=reg_any
  1938. call lilrxxxsil(ADD_I)
  1939. pat lil lol sbi sil $1==$4 && $3==WORD_SIZE
  1940. && inreg($2)==reg_any && inreg($1)!=reg_any
  1941. call lilrxxxsil(SUB_I)
  1942. pat lil lol sbu sil $1==$4 && $3==WORD_SIZE
  1943. && inreg($2)==reg_any && inreg($1)!=reg_any
  1944. call lilrxxxsil(SUB_I)
  1945. pat lil lol and sil $1==$4 && $3==WORD_SIZE
  1946. && inreg($2)==reg_any && inreg($1)!=reg_any
  1947. call lilrxxxsil(AND_I)
  1948. pat lil lol ior sil $1==$4 && $3==WORD_SIZE
  1949. && inreg($2)==reg_any && inreg($1)!=reg_any
  1950. call lilrxxxsil(OR_I)
  1951. pat lil lol xor sil $1==$4 && $3==WORD_SIZE
  1952. && inreg($2)==reg_any && inreg($1)!=reg_any
  1953. call lilrxxxsil(EOR_I)
  1954. #if WORD_SIZE!=2
  1955. pat lil lol ads sil $1==$4 && $3==4 && inreg($2)==reg_any && inreg($1)!=reg_any
  1956. call lilrxxxsil("add.l")
  1957. #endif
  1958. proc loerxxxste example loe lol adi ste
  1959. kills posextern
  1960. gen xxx* {LOCAL, $2}, {absolute_int, $1}
  1961. pat loe lol adi ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1962. call loerxxxste(ADD_I)
  1963. pat loe lol adu ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1964. call loerxxxste(ADD_I)
  1965. pat loe lol sbi ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1966. call loerxxxste(SUB_I)
  1967. pat loe lol sbu ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1968. call loerxxxste(SUB_I)
  1969. pat loe lol and ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1970. call loerxxxste(AND_I)
  1971. pat loe lol ior ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1972. call loerxxxste(OR_I)
  1973. pat loe lol xor ste $1==$4 && $3==WORD_SIZE && inreg($2)==reg_any
  1974. call loerxxxste(EOR_I)
  1975. #if WORD_SIZE!=2
  1976. pat loe lol ads ste $1==$4 && $3==4 && inreg($2)==reg_any
  1977. call loerxxxste("add.l")
  1978. #endif
  1979. proc xxxstl example adi stl
  1980. with any_int-RD_REG-dreg_int any-RD_REG-dreg_int
  1981. kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
  1982. gen move %2,{dreg_int, regvar($2)}
  1983. xxx* %1,{LOCAL,$2}
  1984. with exact any_int-RD_REG-dreg_int STACK
  1985. kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
  1986. gen move_i {post_inc_int, sp}, {dreg_int, regvar($2)}
  1987. xxx* %1,{LOCAL,$2}
  1988. pat adi stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(ADD_I)
  1989. pat adu stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(ADD_I)
  1990. pat sbi stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(SUB_I)
  1991. pat sbu stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(SUB_I)
  1992. pat and stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(AND_I)
  1993. pat ior stl $1==WORD_SIZE && inreg($2)==reg_any call xxxstl(OR_I)
  1994. pat xor stl $1==WORD_SIZE && inreg($2)==reg_any
  1995. with D_REG any_int
  1996. kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
  1997. gen move %2,{dreg_int, regvar($2)}
  1998. eor_i %1,{dreg_int, regvar($2)}
  1999. pat ads SLP $1==4 && inreg($2)==reg_pointer
  2000. with any4-areg-RA_REG any4+address-areg-RA_REG
  2001. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2002. gen move %2,{areg,regvar($2,reg_pointer)}
  2003. add_l %1,{areg,regvar($2,reg_pointer)}
  2004. #ifdef TBL68020
  2005. with regX any4+address-areg-RA_REG
  2006. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2007. gen move %2,{areg,regvar($2,reg_pointer)}
  2008. move {regAregXcon, regvar($2,reg_pointer), %1.xreg, %1.sc, 0},{areg,regvar($2,reg_pointer)}
  2009. with exact regX STACK
  2010. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2011. gen move_l {post_inc4, sp},{areg,regvar($2,reg_pointer)}
  2012. move {regAregXcon, regvar($2,reg_pointer), %1.xreg, %1.sc, 0},{areg,regvar($2,reg_pointer)}
  2013. with exact regX regAcon
  2014. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2015. gen move {regAregXcon, %2.reg, %1.xreg, %1.sc, %2.bd},{areg,regvar($2,reg_pointer)}
  2016. with exact regX local_addr
  2017. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2018. gen move {regAregXcon, lb, %1.xreg, %1.sc, %2.bd},{areg,regvar($2,reg_pointer)}
  2019. #ifdef FANCY_MODES
  2020. with exact regX indirect4
  2021. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2022. gen move {off_regXcon, %2.reg, %1.xreg,%1.sc,0,0},{areg,regvar($2,reg_pointer)}
  2023. with exact regX offsetted4
  2024. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2025. gen move {off_regXcon, %2.reg, %1.xreg, %1.sc, %2.bd, 0},{areg,regvar($2,reg_pointer)}
  2026. with exact regX LOCAL
  2027. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2028. gen move {off_regXcon, lb, %1.xreg, %1.sc, %2.bd, 0},{areg,regvar($2,reg_pointer)}
  2029. with exact regX off_con
  2030. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2031. gen move {off_regXcon, %2.reg, %1.xreg,%1.sc,%2.bd,%2.od},{areg,regvar($2,reg_pointer)}
  2032. with exact regX ext_addr
  2033. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2034. gen move{ext_regX, %1.sc, %1.xreg, %2.bd},{areg,regvar($2,reg_pointer)}
  2035. with exact regX absolute4
  2036. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2037. gen move {abs_regXcon, %1.sc, %1.xreg, %2.bd, 0},{areg,regvar($2,reg_pointer)}
  2038. with exact regX abs_con
  2039. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2040. gen move {abs_regXcon, %1.sc, %1.xreg, %2.bd, %2.od},{areg,regvar($2,reg_pointer)}
  2041. with exact indirect4 ext_addr
  2042. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2043. gen move {off_con, %1.reg, 0, %2.bd},{areg,regvar($2,reg_pointer)}
  2044. with exact offsetted4 ext_addr
  2045. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2046. gen move {off_con, %1.reg, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
  2047. with exact LOCAL ext_addr
  2048. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2049. gen move {off_con, lb, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
  2050. with exact index_off4 ext_addr
  2051. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2052. gen move {indoff_con, %1.reg, %1.xreg, %1.sc,%1.bd,%2.bd},{areg,regvar($2,reg_pointer)}
  2053. with exact absolute4 ext_addr
  2054. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2055. gen move {abs_con, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
  2056. with exact abs_index4 ext_addr
  2057. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2058. gen move {absind_con, %1.sc, %1.xreg, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
  2059. with exact indirect4 ext_regX
  2060. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2061. gen move {off_regXcon, %1.reg, %2.xreg, %2.sc, 0, %2.bd},{areg,regvar($2,reg_pointer)}
  2062. with exact offsetted4 ext_regX
  2063. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2064. gen move {off_regXcon, %1.reg, %2.xreg,%2.sc,%1.bd,%2.bd},{areg,regvar($2,reg_pointer)}
  2065. with exact LOCAL ext_regX
  2066. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2067. gen move {off_regXcon, lb, %2.xreg, %2.sc, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
  2068. with exact absolute4 ext_regX
  2069. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2070. gen move {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd},{areg,regvar($2,reg_pointer)}
  2071. #endif /* FANCY_MODES */
  2072. #endif /* TBL68020 */
  2073. proc xxxdupstl example adi dup stl
  2074. with any_int-RD_REG-dreg_int any-RD_REG-dreg_int
  2075. kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
  2076. gen move %2,{dreg_int, regvar($3)}
  2077. xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
  2078. with exact any_int-RD_REG-dreg_int STACK
  2079. kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
  2080. gen move_i {post_inc_int, sp}, {dreg_int, regvar($3)}
  2081. xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
  2082. pat adi dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
  2083. call xxxdupstl(ADD_I)
  2084. pat adu dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
  2085. call xxxdupstl(ADD_I)
  2086. pat sbi dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
  2087. call xxxdupstl(SUB_I)
  2088. pat sbu dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
  2089. call xxxdupstl(SUB_I)
  2090. pat and dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
  2091. call xxxdupstl(AND_I)
  2092. pat ior dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
  2093. call xxxdupstl(OR_I)
  2094. /*
  2095. pat xor dup stl $1==$2 && $2==WORD_SIZE && inreg($3)==reg_any
  2096. call xxxdupstl(EOR_I)
  2097. incorrect for eor.l !!!
  2098. */
  2099. pat dup stl $1==WORD_SIZE && inreg($2)==reg_any
  2100. with any_int
  2101. kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
  2102. gen move %1,{dreg_int, regvar($2,reg_any)}
  2103. yields {LOCAL, $2}
  2104. pat dup stl $1==4 && inreg($2)==reg_pointer
  2105. with any4
  2106. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2107. gen move_l %1,{areg, regvar($2, reg_pointer)}
  2108. yields {DLOCAL, $2}
  2109. pat dup LLP sti LLP adp SLP zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2110. $2==$4 && $2==$6 && $3==1 && $5==1
  2111. with any1
  2112. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2113. gen move_b %1,{post_inc1, regvar($2,reg_pointer)}
  2114. bne {llabel, $7}
  2115. pat dup LLP sti LLP adp SLP zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2116. $2==$4 && $2==$6 && $3==1 && $5==1
  2117. with any1
  2118. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2119. gen move_b %1,{post_inc1, regvar($2,reg_pointer)}
  2120. beq {llabel, $7}
  2121. /* Normally, LLP sti wth word size will be optimized to sil */
  2122. pat dup LLP sti LLP adp SLP zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2123. $2==$4 && $2==$6 && $3==2 && $5==2
  2124. with any2
  2125. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2126. gen move_w %1,{post_inc2, regvar($2,reg_pointer)}
  2127. bne {llabel, $7}
  2128. pat dup LLP sti LLP adp SLP zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2129. $2==$4 && $2==$6 && $3==2 && $5==2
  2130. with any2
  2131. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2132. gen move_w %1,{post_inc2, regvar($2,reg_pointer)}
  2133. beq {llabel, $7}
  2134. #if WORD_SIZE!=2
  2135. /* m68k2 can't do zne/zeq on 4-byte */
  2136. pat dup LLP sti LLP adp SLP zne $1==4 && inreg($2)==reg_pointer &&
  2137. $2==$4 && $2==$6 && $3==4 && $5==4
  2138. with any4
  2139. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2140. gen move_l %1,{post_inc4, regvar($2,reg_pointer)}
  2141. bne {llabel, $7}
  2142. pat dup LLP sti LLP adp SLP zeq $1==4 && inreg($2)==reg_pointer &&
  2143. $2==$4 && $2==$6 && $3==4 && $5==4
  2144. with any4
  2145. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2146. gen move_l %1,{post_inc4, regvar($2,reg_pointer)}
  2147. beq {llabel, $7}
  2148. #endif
  2149. pat dup sil LLP adp SLP zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2150. $2==$3 && $3==$5 && $4==WORD_SIZE
  2151. with any_int
  2152. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2153. gen move_i %1,{post_inc_int, regvar($2, reg_pointer)}
  2154. bne {llabel, $6}
  2155. pat dup sil LLP adp SLP zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2156. $2==$3 && $3==$5 && $4==WORD_SIZE
  2157. with any_int
  2158. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2159. gen move_i %1,{post_inc_int, regvar($2, reg_pointer)}
  2160. beq {llabel, $6}
  2161. pat sil lil LLP adp SLP zne $1==$2 && $2==$3 && $3==$5 && $4==WORD_SIZE
  2162. && inreg($1)==reg_pointer
  2163. with any_int
  2164. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2165. gen move_i %1,{post_inc_int, regvar($1,reg_pointer)}
  2166. bne {llabel, $6}
  2167. pat sil lil LLP adp SLP zeq $1==$2 && $2==$3 && $3==$5 && $4==WORD_SIZE
  2168. && inreg($1)==reg_pointer
  2169. with any_int
  2170. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2171. gen move_i %1,{post_inc_int, regvar($1,reg_pointer)}
  2172. beq {llabel, $6}
  2173. pat dup LLP adp SLP LLP sti zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2174. $2==$4 && $4==$5 && $6==1 && $4==(0-1)
  2175. with any1
  2176. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2177. gen move_b %1,{pre_dec1, regvar($2,reg_pointer)}
  2178. bne {llabel, $7}
  2179. pat dup LLP adp SLP LLP sti zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2180. $2==$4 && $4==$5 && $6==1 && $4==(0-1)
  2181. with any1
  2182. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2183. gen move_b %1,{pre_dec1, regvar($2,reg_pointer)}
  2184. beq {llabel, $7}
  2185. #if WORD_SIZE!=2
  2186. pat dup LLP adp SLP LLP sti zne $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2187. $2==$4 && $4==$5 && $6==2 && $4==(0-2)
  2188. with any2
  2189. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2190. gen move_w %1,{pre_dec2, regvar($2,reg_pointer)}
  2191. bne {llabel, $7}
  2192. pat dup LLP adp SLP LLP sti zeq $1==WORD_SIZE && inreg($2)==reg_pointer &&
  2193. $2==$4 && $4==$5 && $6==2 && $4==(0-2)
  2194. with any2
  2195. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2196. gen move_w %1,{pre_dec2, regvar($2,reg_pointer)}
  2197. beq {llabel, $7}
  2198. #endif
  2199. #if WORD_SIZE!=2
  2200. pat dup lol adp stl lol sti zne $1==4 && inreg($2)==reg_pointer &&
  2201. $2==$4 && $4==$5 && $6==4 && $4==(0-4)
  2202. with any4
  2203. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2204. gen move_l %1,{pre_dec4, regvar($2,reg_pointer)}
  2205. bne {llabel, $7}
  2206. pat dup lol adp stl lol sti zeq $1==4 && inreg($2)==reg_pointer &&
  2207. $2==$4 && $4==$5 && $6==4 && $4==(0-4)
  2208. with any4
  2209. kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
  2210. gen move_l %1,{pre_dec4, regvar($2,reg_pointer)}
  2211. beq {llabel, $7}
  2212. #endif
  2213. pat LLP ads SLP $1==$3 && $2==4 && inreg($1)==reg_pointer
  2214. with data4-sconsts
  2215. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2216. gen add_l %1, {DLOCAL, $1}
  2217. pat lil dup inc sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
  2218. kills allexceptcon
  2219. uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
  2220. gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
  2221. killreg %a
  2222. yields %a
  2223. pat lil dup dec sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
  2224. kills allexceptcon
  2225. uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
  2226. gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
  2227. killreg %a
  2228. yields %a
  2229. pat LLP LFP dup adp LLP SFP sti $3==4 && $1==$5 && $2==$6 && inreg($1)==reg_pointer && $7 <= 4
  2230. with conreg
  2231. kills allexceptcon
  2232. uses AA_REG = {offsetted4, regvar($1, reg_pointer), $2}
  2233. gen add_l {const4, $4}, {offsetted4, regvar($1, reg_pointer), $2}
  2234. killreg %a
  2235. yields %1 %a leaving sti $7
  2236. pat LLP LFP dup adp LLP SFP $3==4 && $1==$5 && $2==$6 && inreg($1)==reg_pointer
  2237. kills allexceptcon
  2238. uses AA_REG = {offsetted4, regvar($1, reg_pointer), $2}
  2239. gen add_l {const4, $4}, {offsetted4, regvar($1, reg_pointer), $2}
  2240. killreg %a
  2241. yields %a
  2242. pat LLP LFP dup adp LLP SFP sti $3==4 && $1==$5 && $2==$6 && $7 <= 4
  2243. with conreg
  2244. kills allexceptcon
  2245. uses AA_REG = {DLOCAL, $1}, AA_REG
  2246. gen move_l {offsetted4, %a, $2}, %b
  2247. add_l {const4, $4}, {offsetted4, %a, $2}
  2248. yields %1 %b leaving sti $7
  2249. pat LLP LFP dup adp LLP SFP $3==4 && $1==$5 && $2==$6
  2250. kills allexceptcon
  2251. uses AA_REG = {DLOCAL, $1}, AA_REG
  2252. gen move_l {offsetted4, %a, $2}, %b
  2253. add_l {const4, $4}, {offsetted4, %a, $2}
  2254. yields %b
  2255. pat LEP LFP dup adp LEP SFP sti $3==4 && $1==$5 && $2==$6 && $7 <= 4
  2256. with conreg
  2257. kills allexceptcon
  2258. uses AA_REG = {absolute4, $1}, AA_REG
  2259. gen move_l {offsetted4, %a, $2}, %b
  2260. add_l {const4, $4}, {offsetted4, %a, $2}
  2261. yields %1 %b leaving sti $7
  2262. pat LEP LFP dup adp LEP SFP $3==4 && $1==$5 && $2==$6
  2263. kills allexceptcon
  2264. uses AA_REG = {absolute4, $1}, AA_REG
  2265. gen move_l {offsetted4, %a, $2}, %b
  2266. add_l {const4, $4}, {offsetted4, %a, $2}
  2267. yields %b
  2268. #if WORD_SIZE!=2
  2269. pat lil lof dup adp lil stf sti $3==4 && $1==$5 && $2==$6 && inreg($1)==reg_pointer && $7 <= 4
  2270. with conreg
  2271. kills allexceptcon
  2272. uses AA_REG = {indirect4, regvar($1, reg_pointer)}, AA_REG
  2273. gen move_l {offsetted4, %a, $2}, %b
  2274. add_l {const4, $4}, {offsetted4, %a, $2}
  2275. yields %1 %b leaving sti $7
  2276. pat lil lof dup adp lil stf $3==4 && $1==$5 && $2==$6 && inreg($1)==reg_pointer
  2277. kills allexceptcon
  2278. uses AA_REG = {indirect4, regvar($1, reg_pointer)}, AA_REG
  2279. gen move_l {offsetted4, %a, $2}, %b
  2280. add_l {const4, $4}, {offsetted4, %a, $2}
  2281. yields %b
  2282. #endif /* WORD_SIZE==2 */
  2283. pat LEP loi dup adp LEP sti sti $3==4 && $1==$5 && $2==4 && $6==4 && $7 <= 4
  2284. with conreg
  2285. kills allexceptcon
  2286. uses AA_REG = {absolute4, $1}, AA_REG
  2287. gen move_l {indirect4, %a}, %b
  2288. add_l {const4, $4}, {indirect4, %a}
  2289. yields %1 %b leaving sti $7
  2290. pat LEP loi dup adp LEP sti $3==4 && $1==$5 && $2==4 && $6==4
  2291. kills allexceptcon
  2292. uses AA_REG = {absolute4, $1}, AA_REG
  2293. gen move_l {indirect4, %a}, %b
  2294. add_l {const4, $4}, {indirect4, %a}
  2295. yields %b
  2296. #if WORD_SIZE!=2
  2297. pat lil loi dup adp lil sti sti $3==4 && $1==$5 && $2==4 && $6==4 && $7 <= 4
  2298. with conreg
  2299. kills allexceptcon
  2300. uses AA_REG = {indirect4, regvar($1, reg_pointer)}, AA_REG
  2301. gen move_l {indirect4, %a}, %b
  2302. add_l {const4, $4}, {indirect4, %a}
  2303. yields %1 %b leaving sti $7
  2304. pat lil loi dup adp lil sti $3==4 && $1==$5 && $2==4 && $6==4
  2305. kills allexceptcon
  2306. uses AA_REG = {indirect4, regvar($1, reg_pointer)}, AA_REG
  2307. gen move_l {indirect4, %a}, %b
  2308. add_l {const4, $4}, {indirect4, %a}
  2309. yields %b
  2310. #endif
  2311. pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 < 0
  2312. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2313. gen sub_l {const4,0-$3},{DLOCAL,$1}
  2314. yields {DLOCAL,$1} {ext_addr, $5+$3}
  2315. leaving cmu 4
  2316. pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 > 0
  2317. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2318. gen add_l {const4,$3},{DLOCAL,$1}
  2319. yields {DLOCAL,$1} {ext_addr, $5+$3}
  2320. leaving cmu 4
  2321. pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==4 && $5==4 &&
  2322. inreg($1)==reg_pointer
  2323. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2324. yields {post_inc4, regvar($1, reg_pointer)}
  2325. pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
  2326. leaving LLP $1 loi $5 LLP $4 adp $3 SLP $4
  2327. pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
  2328. inreg($1)==reg_pointer
  2329. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2330. yields {post_inc1, regvar($1, reg_pointer)}
  2331. /* Normally, LLP loi will be optimized to lil */
  2332. pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==2 && $4==2 &&
  2333. inreg($1)==reg_pointer
  2334. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2335. yields {post_inc2, regvar($1, reg_pointer)}
  2336. pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==4 && $4==4 &&
  2337. inreg($1)==reg_pointer
  2338. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2339. yields {post_inc4, regvar($1, reg_pointer)}
  2340. pat lil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
  2341. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2342. yields {post_inc_int, regvar($1, reg_pointer)}
  2343. pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
  2344. leaving LLP $1 sti $5 LLP $4 adp $3 SLP $4
  2345. pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
  2346. inreg($1)==reg_pointer
  2347. with any1
  2348. kills allexceptcon, regvar($1, reg_pointer)
  2349. gen move %1, {post_inc1, regvar($1, reg_pointer)}
  2350. /* Normally, LLP sti will ve optimzed into sil */
  2351. pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==2 && $4==2 &&
  2352. inreg($1)==reg_pointer
  2353. with any2
  2354. kills allexceptcon, regvar($1, reg_pointer)
  2355. gen move %1, {post_inc2, regvar($1, reg_pointer)}
  2356. pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==4 && $4==4 &&
  2357. inreg($1)==reg_pointer
  2358. with any4
  2359. kills allexceptcon, regvar($1, reg_pointer)
  2360. gen move %1, {post_inc4, regvar($1, reg_pointer)}
  2361. pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==WORD_SIZE && $5==WORD_SIZE &&
  2362. inreg($1)==reg_pointer
  2363. with any_int-sconsts
  2364. kills allexceptcon, regvar($1, reg_pointer)
  2365. gen move %1, {post_inc_int, regvar($1, reg_pointer)}
  2366. pat sil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
  2367. with any_int-sconsts
  2368. kills allexceptcon, regvar($1, reg_pointer)
  2369. gen move %1, {post_inc_int, regvar($1, reg_pointer)}
  2370. pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
  2371. inreg($1)==reg_pointer
  2372. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2373. yields {pre_dec1, regvar($1, reg_pointer)}
  2374. /* Normally, LLP loi will be optimized to lil */
  2375. pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-2 && $5==2 &&
  2376. inreg($1)==reg_pointer
  2377. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2378. yields {pre_dec2, regvar($1, reg_pointer)}
  2379. pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-4 && $5==4 &&
  2380. inreg($1)==reg_pointer
  2381. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2382. yields {pre_dec4, regvar($1, reg_pointer)}
  2383. pat LLP adp SLP lil $1==$3 && $1==$4 && $2==0-WORD_SIZE &&
  2384. inreg($1)==reg_pointer
  2385. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2386. yields {pre_dec_int, regvar($1, reg_pointer)}
  2387. pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
  2388. inreg($1)==reg_pointer
  2389. with any1
  2390. kills allexceptcon, regvar($1, reg_pointer)
  2391. gen move %1, {pre_dec1, regvar($1, reg_pointer)}
  2392. #if WORD_SIZE!=2
  2393. pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-2 && $5==2 &&
  2394. inreg($1)==reg_pointer
  2395. with any2
  2396. kills allexceptcon, regvar($1, reg_pointer)
  2397. gen move %1, {pre_dec2, regvar($1, reg_pointer)}
  2398. #else
  2399. pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-4 && $5==4 &&
  2400. inreg($1)==reg_pointer
  2401. with any4
  2402. kills allexceptcon, regvar($1, reg_pointer)
  2403. gen move %1, {pre_dec4, regvar($1, reg_pointer)}
  2404. #endif
  2405. pat LLP adp SLP sil $1==$3 && $1==$4 && $2==0-WORD_SIZE &&
  2406. inreg($1)==reg_pointer
  2407. with any_int-sconsts
  2408. kills allexceptcon, regvar($1, reg_pointer)
  2409. gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
  2410. pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directadd($3)
  2411. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2412. uses AA_REG = {DLOCAL, $1}
  2413. gen add_l {const4, $3}, {DLOCAL, $1}
  2414. killreg %a
  2415. yields %a
  2416. pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directsub($3)
  2417. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2418. uses AA_REG = {DLOCAL, $1}
  2419. gen sub_l {const4, 0-$3}, {DLOCAL, $1}
  2420. killreg %a
  2421. yields %a
  2422. pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer
  2423. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2424. uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
  2425. gen add_l %b, {DLOCAL, $1}
  2426. killreg %a
  2427. yields %a
  2428. pat LLP dup adp SLP $1==$4 && $2==4 && directadd($3)
  2429. kills all_indir, DLOCAL %bd==$1
  2430. uses AA_REG = {DLOCAL, $1}
  2431. gen add_l {const4, $3}, {DLOCAL, $1}
  2432. killreg %a
  2433. yields %a
  2434. pat LLP dup adp SLP $1==$4 && $2==4 && directsub($3)
  2435. kills all_indir, DLOCAL %bd==$1
  2436. uses AA_REG = {DLOCAL, $1}
  2437. gen sub_l {const4, 0-$3}, {DLOCAL, $1}
  2438. killreg %a
  2439. yields %a
  2440. pat LLP dup adp SLP $1==$4 && $2==4
  2441. kills all_indir, DLOCAL %bd==$1
  2442. uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
  2443. gen add_l %b, {DLOCAL, $1}
  2444. killreg %a
  2445. yields %a
  2446. pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directadd($2)
  2447. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2448. gen add_l {const4, $2}, {DLOCAL, $1}
  2449. pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directsub($2)
  2450. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2451. gen sub_l {const4, 0-$2}, {DLOCAL, $1}
  2452. pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer
  2453. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2454. uses DD_REG4 = {const4, $2}
  2455. gen add_l %a, {DLOCAL, $1}
  2456. pat LLP adp SLP $1==$3 && directadd($2)
  2457. kills all_indir, DLOCAL %bd==$1
  2458. gen add_l {const4, $2}, {DLOCAL, $1}
  2459. pat LLP adp SLP $1==$3 && directsub($2)
  2460. kills all_indir, DLOCAL %bd==$1
  2461. gen sub_l {const4, 0-$2}, {DLOCAL, $1}
  2462. pat LLP adp SLP $1==$3
  2463. kills all_indir, DLOCAL %bd==$1
  2464. uses DD_REG4 = {const4, $2}
  2465. gen add_l %a, {DLOCAL, $1}
  2466. #if WORD_SIZE!=2
  2467. pat lil dup adp sil sti $1==$4 && $2==4 && inreg($1)==reg_pointer && $5<=4
  2468. with conreg
  2469. kills allexceptcon
  2470. uses AA_REG = {indirect4, regvar($1, reg_pointer)}
  2471. gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)}
  2472. killreg %a
  2473. yields %1 %a leaving sti $5
  2474. pat lil dup adp sil $1==$4 && $2==4 && inreg($1)==reg_pointer
  2475. kills allexceptcon
  2476. uses AA_REG = {indirect4, regvar($1, reg_pointer)}
  2477. gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)}
  2478. killreg %a
  2479. yields %a
  2480. pat lil dup adp sil $1==$4 && $2==4
  2481. kills allexceptcon
  2482. uses AA_REG, AA_REG = {LOCAL, $1}
  2483. gen move {indirect4, %b}, %a
  2484. add_l {const, $3}, {indirect4, %b}
  2485. killreg %a
  2486. yields %a
  2487. pat lil adp sil $1==$3 && inreg($1)==reg_pointer
  2488. kills allexceptcon
  2489. gen add_l {const, $2}, {indirect4, regvar($1, reg_pointer)}
  2490. pat lil adp sil $1==$3 && inreg($1)!=reg_any
  2491. kills allexceptcon
  2492. #if TBL68020 /* WORD_SIZE==4 */
  2493. gen add_l {const, $2}, {ILOCAL,$1}
  2494. #else
  2495. uses AA_REG = {LOCAL, $1}
  2496. gen add_l {const, $2}, {indirect4, %a}
  2497. #endif
  2498. #endif /* WORD_SIZE==2 */
  2499. pat LEP dup adp SEP $1==$4 && $2==4
  2500. kills posextern
  2501. uses AA_REG = {absolute4, $1}
  2502. gen add_l {const4, $3}, {absolute4, $1}
  2503. killreg %a
  2504. yields %a
  2505. pat LEP adp SEP $1==$3
  2506. kills posextern
  2507. gen add_l {const4, $2}, {absolute4, $1}
  2508. pat loc and $1==255 && $2==WORD_SIZE
  2509. #if WORD_SIZE==2
  2510. with exact absolute_int yields {absolute1,%1.bd+1}
  2511. with exact offsetted_int yields {offsetted1,%1.reg,%1.bd+1}
  2512. with exact LOCAL yields {offsetted1,lb,%1.bd+1}
  2513. #else
  2514. with exact absolute_int yields {absolute1,%1.bd+3}
  2515. with exact offsetted_int yields {offsetted1,%1.reg,%1.bd+3}
  2516. with exact LOCAL yields {offsetted1,lb,%1.bd+3}
  2517. #endif
  2518. with yields {const, $1} leaving and WORD_SIZE
  2519. /************************************************
  2520. * Group 1: load instructions *
  2521. ************************************************/
  2522. pat loc $1==0 yields {zero_const, $1}
  2523. pat loc small($1) yields {small_const, $1}
  2524. pat loc in_1($1) yields {bconst, $1}
  2525. pat loc yields {const, $1}
  2526. #if WORD_SIZE!=2
  2527. pat ldc leaving loc 18 trp
  2528. #else
  2529. pat ldc highw($1)==0 && loww($1)==0 yields {zero_const4, 0}
  2530. pat ldc highw($1)==0 && small(loww($1)) yields {small_const4, loww($1)}
  2531. pat ldc highw($1)==0 && in_1(loww($1)) yields {bconst4, loww($1)}
  2532. pat ldc yields {const4, $1}
  2533. #endif
  2534. pat LLP inreg($1)==reg_pointer
  2535. kills pre_post %reg==regvar($1, reg_pointer)
  2536. yields {DLOCAL, $1}
  2537. pat lol yields {LOCAL, $1}
  2538. #if WORD_SIZE!=2
  2539. pat ldl leaving lol $1+4 lol $1
  2540. #else
  2541. pat ldl yields {DLOCAL, $1}
  2542. #endif
  2543. pat loe yields {absolute_int, $1}
  2544. /* replace ste loe by dup ste, but not if followed by a test ... */
  2545. proc steloezxx example ste loe zne
  2546. with any_int-sconsts
  2547. kills posextern
  2548. gen move_i %1, {absolute_int, $1}
  2549. bxx* {llabel, $3}
  2550. with exact STACK
  2551. kills posextern
  2552. gen move_i {post_inc_int, sp}, {absolute_int, $1}
  2553. bxx* {llabel, $3}
  2554. pat ste loe zlt $1==$2 call steloezxx("blt")
  2555. pat ste loe zle $1==$2 call steloezxx("ble")
  2556. pat ste loe zeq $1==$2 call steloezxx("beq")
  2557. pat ste loe zne $1==$2 call steloezxx("bne")
  2558. pat ste loe zge $1==$2 call steloezxx("bge")
  2559. pat ste loe zgt $1==$2 call steloezxx("bgt")
  2560. pat ste loe $1==$2 leaving dup WORD_SIZE ste $1
  2561. pat lil inreg($1)==reg_pointer
  2562. kills pre_post %reg==regvar($1, reg_pointer)
  2563. yields {indirect_int, regvar($1, reg_pointer)}
  2564. #if WORD_SIZE==4
  2565. pat lil inreg($1)==reg_any
  2566. uses AA_REG = {DLOCAL, $1}
  2567. yields {indirect_int, %a}
  2568. #endif
  2569. pat lil
  2570. #if TBL68020
  2571. yields {ILOCAL, $1}
  2572. #else
  2573. uses AA_REG = {DLOCAL, $1}
  2574. yields {indirect_int, %a}
  2575. #endif
  2576. /* When using the 'offsetted' intructions regAregXcon cannot be used
  2577. * for the m68k[24]; there is no way of knowing about the size of
  2578. * %1.bd+$1, because expressions are not allowed in stack patterns, and
  2579. * this may lead to outputting too large displacements. With regAcon
  2580. * the chance that this will happen is very slim, because it can
  2581. * have displacements of 16 bits. Besides, leaving out regAcon here
  2582. * would make it very hard to handle this instruction efficiently.
  2583. */
  2584. pat lof
  2585. with A_REG yields {offsetted_int, %1, $1}
  2586. with exact local_addr yields {LOCAL, %1.bd+$1}
  2587. with exact ext_addr yields {absolute_int, %1.bd+$1}
  2588. #ifndef TBL68020
  2589. with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
  2590. #else /* TBL68020 */
  2591. with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
  2592. with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
  2593. #ifdef FANCY_MODES
  2594. with exact offsetted4 yields {OFF_off_int, %1.reg, %1.bd, $1}
  2595. with exact indirect yields {OFF_off_int, %1.reg, 0, $1}
  2596. with exact DLOCAL yields {OFF_off_int, lb, %1.bd, $1}
  2597. with exact off_con yields {OFF_off_int, %1.reg, %1.bd, %1.od+$1}
  2598. with exact index_off4 yields {INDOFF_off_int, %1.reg, %1.xreg, %1.sc, %1.bd, $1}
  2599. with exact indoff_con yields {INDOFF_off_int,
  2600. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
  2601. with exact off_regXcon yields {OFF_indoff_int,
  2602. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
  2603. with exact absolute4 yields {ABS_off_int, %1.bd, $1}
  2604. with exact abs_con yields {ABS_off_int, %1.bd, %1.od+$1}
  2605. with exact abs_regXcon yields {ABS_indoff_int, %1.sc, %1.xreg, %1.bd, %1.od+$1}
  2606. with exact abs_index4 yields {ABSIND_off_int, %1.sc, %1.xreg, %1.bd, $1}
  2607. with exact absind_con yields {ABSIND_off_int, %1.sc, %1.xreg, %1.bd, %1.od+$1}
  2608. with exact ext_regX yields {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
  2609. #endif /* FANCY_MODES */
  2610. #endif /* TBL68020 */
  2611. pat lal yields {local_addr, $1}
  2612. pat lae yields {ext_addr, $1}
  2613. pat lxl $1==0 yields lb
  2614. pat lxl $1==1 yields {DLOCAL, SL}
  2615. pat lxl $1==2
  2616. #if TBL68020 && FANCY_MODES
  2617. yields {OFF_off4, lb, SL, SL}
  2618. #else
  2619. uses AA_REG = {DLOCAL, SL}
  2620. yields {offsetted4, %a, SL}
  2621. #endif
  2622. pat lxl $1==3
  2623. #if TBL68020 && FANCY_MODES
  2624. uses AA_REG = {OFF_off4, lb, SL, SL}
  2625. #else
  2626. uses AA_REG = {DLOCAL, SL}
  2627. gen move_l {offsetted4, %a, SL}, %a
  2628. #endif
  2629. yields {offsetted4, %a, SL}
  2630. pat lxl $1>3
  2631. uses AA_REG = {DLOCAL, SL},
  2632. DD_REG4 = {const, $1-2}
  2633. gen 1:
  2634. move_l {offsetted4, %a, SL} ,%a
  2635. dbf %b, {slabel, 1b}
  2636. yields %a
  2637. pat lxa $1==0 yields {local_addr, SL}
  2638. pat lxa $1==1
  2639. #if TBL68020 && FANCY_MODES
  2640. yields {off_con, lb, SL, SL}
  2641. #else
  2642. uses AA_REG = {DLOCAL, SL}
  2643. yields {regAcon, %a, SL}
  2644. #endif
  2645. pat lxa $1==2
  2646. #if TBL68020 && FANCY_MODES
  2647. uses AA_REG = {OFF_off4, lb, SL, SL}
  2648. #else
  2649. uses AA_REG = {DLOCAL, SL}
  2650. gen move_l {offsetted4, %a, SL}, %a
  2651. #endif
  2652. yields {regAcon, %a, SL}
  2653. pat lxa $1>2
  2654. uses AA_REG = {DLOCAL, SL},
  2655. DD_REG4 = {const, $1-2}
  2656. gen 1:
  2657. move_l {offsetted4, %a, SL} ,%a
  2658. dbf %b, {slabel, 1b}
  2659. yields {regAcon, %a, SL}
  2660. pat loi $1==1
  2661. with A_REG yields {indirect1, %1}
  2662. with exact local_addr yields {offsetted1, lb, %1.bd}
  2663. with exact ext_addr yields {absolute1, %1.bd}
  2664. #ifndef TBL68020
  2665. with regAcon yields {offsetted1, %1.reg, %1.bd}
  2666. with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
  2667. #else /* TBL68020 */
  2668. with exact regAcon yields {offsetted1, %1.reg, %1.bd}
  2669. with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
  2670. #ifdef FANCY_MODES
  2671. with exact indirect4 yields {OFF_off1, %1.reg, 0, 0}
  2672. with exact offsetted4 yields {OFF_off1, %1.reg, %1.bd, 0}
  2673. with exact LOCAL yields {OFF_off1, lb, %1.bd, 0}
  2674. with exact off_con yields {OFF_off1, %1.reg, %1.bd, %1.od}
  2675. with exact index_off4 yields {INDOFF_off1, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
  2676. with exact indoff_con yields {INDOFF_off1,
  2677. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  2678. with exact off_regXcon yields {OFF_indoff1,
  2679. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  2680. with exact absolute4 yields {ABS_off1, %1.bd, 0}
  2681. with exact abs_con yields {ABS_off1, %1.bd, %1.od}
  2682. with exact abs_regXcon yields {ABS_indoff1, %1.sc, %1.xreg, %1.bd, %1.od}
  2683. with exact abs_index4 yields {ABSIND_off1, %1.sc, %1.xreg, %1.bd, 0}
  2684. with exact absind_con yields {ABSIND_off1, %1.sc, %1.xreg, %1.bd, %1.od}
  2685. with exact ext_regX yields {abs_index1, %1.sc, %1.xreg, %1.bd}
  2686. #endif /* FANCY_MODES */
  2687. #endif /* TBL68020 */
  2688. pat loi $1==2
  2689. with A_REG yields {indirect2, %1}
  2690. #if WORD_SIZE!=2
  2691. with exact local_addr yields {offsetted2, lb, %1.bd}
  2692. #else
  2693. with exact local_addr yields {LOCAL, %1.bd}
  2694. #endif
  2695. with exact ext_addr yields {absolute2, %1.bd}
  2696. #ifndef TBL68020
  2697. with regAcon yields {offsetted2, %1.reg, %1.bd}
  2698. with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
  2699. #else /* TBL68020 */
  2700. with exact regAcon yields {offsetted2, %1.reg, %1.bd}
  2701. with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
  2702. #if WORD_SIZE==2
  2703. with exact DLOCAL yields {ILOCAL, %1.bd}
  2704. #endif
  2705. #ifdef FANCY_MODES
  2706. with exact indirect4 yields {OFF_off2, %1.reg, 0, 0}
  2707. with exact offsetted4 yields {OFF_off2, %1.reg, %1.bd, 0}
  2708. with exact LOCAL yields {OFF_off2, lb, %1.bd, 0}
  2709. with exact off_con yields {OFF_off2, %1.reg, %1.bd, %1.od}
  2710. with exact index_off4 yields {INDOFF_off2, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
  2711. with exact indoff_con yields {INDOFF_off2,
  2712. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  2713. with exact off_regXcon yields {OFF_indoff2,
  2714. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  2715. with exact absolute4 yields {ABS_off2, %1.bd, 0}
  2716. with exact abs_con yields {ABS_off2, %1.bd, %1.od}
  2717. with exact abs_regXcon yields {ABS_indoff2, %1.sc, %1.xreg, %1.bd, %1.od}
  2718. with exact abs_index4 yields {ABSIND_off2, %1.sc, %1.xreg, %1.bd, 0}
  2719. with exact absind_con yields {ABSIND_off2, %1.sc, %1.xreg, %1.bd, %1.od}
  2720. with exact ext_regX yields {abs_index2, %1.sc, %1.xreg, %1.bd}
  2721. #endif /* FANCY_MODES */
  2722. #endif /* TBL68020 */
  2723. pat loi $1==4
  2724. with A_REG yields {indirect4, %1}
  2725. with exact local_addr yields {DLOCAL, %1.bd}
  2726. with exact ext_addr yields {absolute4, %1.bd}
  2727. #ifndef TBL68020
  2728. with regAcon yields {offsetted4, %1.reg, %1.bd}
  2729. with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
  2730. #else /* TBL68020 */
  2731. with exact regAcon yields {offsetted4, %1.reg, %1.bd}
  2732. with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
  2733. #if WORD_SIZE==4
  2734. with exact LOCAL yields {ILOCAL, %1.bd}
  2735. #endif
  2736. #ifdef FANCY_MODES
  2737. with exact indirect4 yields {OFF_off4, %1.reg, 0, 0}
  2738. with exact offsetted4 yields {OFF_off4, %1.reg, %1.bd, 0}
  2739. with exact off_con yields {OFF_off4, %1.reg, %1.bd, %1.od}
  2740. with exact index_off4 yields {INDOFF_off4, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
  2741. with exact indoff_con yields {INDOFF_off4,
  2742. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  2743. with exact off_regXcon yields {OFF_indoff4,
  2744. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  2745. with exact absolute4 yields {ABS_off4, %1.bd, 0}
  2746. with exact abs_con yields {ABS_off4, %1.bd, %1.od}
  2747. with exact abs_regXcon yields {ABS_indoff4, %1.sc, %1.xreg, %1.bd, %1.od}
  2748. with exact abs_index4 yields {ABSIND_off4, %1.sc, %1.xreg, %1.bd, 0}
  2749. with exact absind_con yields {ABSIND_off4, %1.sc, %1.xreg, %1.bd, %1.od}
  2750. with exact ext_regX yields {abs_index4, %1.sc, %1.xreg, %1.bd}
  2751. #endif /* FANCY_MODES */
  2752. #endif /* TBL68020 */
  2753. #if WORD_SIZE==2
  2754. pat loi $1==6
  2755. with AA_REG
  2756. yields {offsetted2, %1, 4} {indirect4, %1}
  2757. with exact local_addr
  2758. yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
  2759. with exact ext_addr
  2760. yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
  2761. #endif
  2762. pat loi $1==8
  2763. #if WORD_SIZE!=2
  2764. leaving ldf 0
  2765. #else
  2766. with AA_REG
  2767. yields {offsetted4, %1, 4} {indirect4, %1}
  2768. with exact local_addr
  2769. yields {offsetted4, lb, %1.bd+4} {offsetted4, lb, %1.bd}
  2770. with exact ext_addr
  2771. yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
  2772. #endif
  2773. #if WORD_SIZE==4
  2774. pat loi $1==3*WORD_SIZE
  2775. with AA_REG STACK
  2776. kills ALL
  2777. uses DD_REG4={const,$1}
  2778. gen add_l %a, %1
  2779. move_i {pre_dec_int, %1},{pre_dec_int, sp}
  2780. move_i {pre_dec_int, %1},{pre_dec_int, sp}
  2781. move_i {pre_dec_int, %1},{pre_dec_int, sp}
  2782. pat loi $1==4*WORD_SIZE
  2783. with AA_REG STACK
  2784. kills ALL
  2785. uses DD_REG4={const4,$1}
  2786. gen add_l %a, %1
  2787. move_i {pre_dec_int, %1},{pre_dec_int, sp}
  2788. move_i {pre_dec_int, %1},{pre_dec_int, sp}
  2789. move_i {pre_dec_int, %1},{pre_dec_int, sp}
  2790. move_i {pre_dec_int, %1},{pre_dec_int, sp}
  2791. #endif
  2792. pat loi $1>4*WORD_SIZE && $1/WORD_SIZE <= 65536
  2793. with AA_REG STACK
  2794. kills ALL
  2795. uses DD_REG4 = {const, $1/WORD_SIZE -1}
  2796. gen add_l {const4, $1}, %1
  2797. 1:
  2798. move_i {pre_dec_int, %1}, {pre_dec_int, sp}
  2799. dbf %a, {slabel, 1b}
  2800. pat loi
  2801. with STACK
  2802. kills ALL
  2803. gen move_i {const,$1},{pre_dec_int, sp}
  2804. jsr {absolute4, ".los"}
  2805. pat los $1==WORD_SIZE
  2806. with STACK
  2807. kills ALL
  2808. gen jsr {absolute4, ".los"}
  2809. #if WORD_SIZE==2
  2810. pat los $1==4
  2811. with STACK
  2812. kills ALL
  2813. gen jsr {absolute4, ".los4"}
  2814. #endif
  2815. pat lde
  2816. #if WORD_SIZE==2
  2817. yields {absolute4, $1}
  2818. #else
  2819. yields {absolute4, $1+4}
  2820. {absolute4, $1}
  2821. #endif
  2822. pat ldf
  2823. #if WORD_SIZE==2
  2824. with A_REG yields {offsetted4, %1, $1}
  2825. with exact local_addr yields {DLOCAL, %1.bd+$1}
  2826. with regAcon yields {offsetted4, %1.reg, %1.bd+$1}
  2827. #else
  2828. with A_REG yields {offsetted4, %1, $1+4}
  2829. {offsetted4, %1, $1}
  2830. with exact local_addr yields {LOCAL, %1.bd+$1+4}
  2831. {LOCAL, %1.bd+$1}
  2832. with regAcon yields {offsetted4, %1.reg, %1.bd+$1+4}
  2833. {offsetted4, %1.reg, %1.bd+$1}
  2834. #endif
  2835. pat lpi yields {ext_addr, $1}
  2836. /************************************************
  2837. * Group 2: store instructions *
  2838. ************************************************/
  2839. pat stl inreg($1)==reg_any
  2840. with exact memory1-consts
  2841. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  2842. gen clr_i {LOCAL, $1}
  2843. move_b %1, {dreg1, regvar($1,reg_any)}
  2844. #if WORD_SIZE==2
  2845. with any2
  2846. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  2847. gen move %1, {LOCAL, $1}
  2848. #else
  2849. with exact memory2-consts
  2850. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  2851. gen clr_i {LOCAL, $1}
  2852. move_w %1, {dreg2, regvar($1,reg_any)}
  2853. with store4
  2854. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  2855. gen move %1, {LOCAL, $1}
  2856. #endif
  2857. with exact STACK
  2858. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  2859. gen move_i {post_inc_int, sp}, {LOCAL, $1}
  2860. pat SLP inreg($1)==reg_pointer
  2861. with any4
  2862. #if WORD_SIZE!=2
  2863. -sconsts4
  2864. #endif
  2865. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2866. gen move %1, {areg, regvar($1, reg_pointer)}
  2867. with exact ext_addr
  2868. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2869. gen move_l %1, {areg, regvar($1, reg_pointer)}
  2870. with address-ext_addr
  2871. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2872. gen lea %1, {areg, regvar($1, reg_pointer)}
  2873. with exact STACK
  2874. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  2875. gen move_l {post_inc4, sp}, {areg, regvar($1, reg_pointer)}
  2876. pat stl
  2877. with store_int-sconsts
  2878. kills all_indir, LOCAL %bd==$1
  2879. gen move %1, {LOCAL, $1}
  2880. with exact STACK
  2881. kills all_indir, LOCAL %bd==$1
  2882. gen move_i {post_inc_int,sp}, {LOCAL, $1}
  2883. pat ste
  2884. with store_int-sconsts
  2885. kills posextern
  2886. gen move %1, {absolute_int, $1}
  2887. with exact STACK
  2888. kills posextern
  2889. gen move_i {post_inc_int, sp}, {absolute_int, $1}
  2890. pat sil inreg($1)==reg_pointer
  2891. with store_int-sconsts
  2892. kills allexceptcon
  2893. gen move %1, {indirect_int, regvar($1, reg_pointer)}
  2894. with exact STACK
  2895. kills allexceptcon
  2896. gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
  2897. #if WORD_SIZE==4
  2898. pat sil inreg($1)==reg_any
  2899. with store_int-sconsts
  2900. kills allexceptcon
  2901. uses AA_REG = {DLOCAL, $1}
  2902. gen move %1, {indirect_int, %a}
  2903. with exact STACK
  2904. kills allexceptcon
  2905. uses AA_REG = {DLOCAL, $1}
  2906. gen move_i {post_inc_int, sp}, {indirect_int, %a}
  2907. #endif
  2908. pat sil
  2909. #if TBL68020
  2910. with store_int-sconsts
  2911. kills allexceptcon
  2912. gen move %1, {ILOCAL, $1}
  2913. with exact STACK
  2914. kills allexceptcon
  2915. gen move_i {post_inc_int, sp}, {ILOCAL, $1}
  2916. #else
  2917. with store_int-sconsts
  2918. kills allexceptcon
  2919. uses AA_REG = {DLOCAL, $1}
  2920. gen move %1, {indirect_int, %a}
  2921. with exact STACK
  2922. kills allexceptcon
  2923. uses AA_REG = {DLOCAL, $1}
  2924. gen move_i {post_inc_int, sp}, {indirect_int, %a}
  2925. #endif
  2926. pat stf
  2927. with A_REG store_int-sconsts
  2928. kills allexceptcon
  2929. gen move %2, {offsetted_int, %1, $1}
  2930. with exact any4 STACK
  2931. kills allexceptcon
  2932. uses AA_REG = %1
  2933. gen move_i {post_inc_int, sp}, {offsetted_int, %a, $1}
  2934. with exact STACK
  2935. kills allexceptcon
  2936. uses AA_REG
  2937. gen move_l {post_inc4, sp}, %a
  2938. move_i {post_inc_int, sp}, {offsetted_int, %a, $1}
  2939. with exact local_addr store_int
  2940. kills allexceptcon
  2941. gen move %2, {LOCAL, %1.bd+$1}
  2942. with exact ext_addr store_int
  2943. kills allexceptcon
  2944. gen move %2, {absolute_int, %1.bd+$1}
  2945. #if TBL68000
  2946. #if WORD_SIZE==4
  2947. with regAcon store_int
  2948. kills allexceptcon
  2949. gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
  2950. #endif
  2951. #else /* TBL68020 */
  2952. with exact regAcon store_int
  2953. kills allexceptcon
  2954. gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
  2955. with exact regAregXcon store_int
  2956. kills allexceptcon
  2957. gen move %2, {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
  2958. #ifdef FANCY_MODES
  2959. with exact indirect4 store_int
  2960. kills allexceptcon
  2961. gen move %2, {OFF_off_int, %1.reg, 0, $1}
  2962. with exact offsetted4 store_int
  2963. kills allexceptcon
  2964. gen move %2, {OFF_off_int, %1.reg, %1.bd, $1}
  2965. with exact DLOCAL store_int
  2966. kills allexceptcon
  2967. gen move %2, {OFF_off_int, lb, %1.bd, $1}
  2968. with exact off_con store_int
  2969. kills allexceptcon
  2970. gen move %2, {OFF_off_int, %1.reg, %1.bd, %1.od+$1}
  2971. with exact index_off4 store_int
  2972. kills allexceptcon
  2973. gen move %2, {INDOFF_off_int, %1.reg, %1.xreg, %1.sc, %1.bd, $1}
  2974. with exact indoff_con store_int
  2975. kills allexceptcon
  2976. gen move %2, {INDOFF_off_int, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
  2977. with exact off_regXcon store_int
  2978. kills allexceptcon
  2979. gen move %2, {OFF_indoff_int, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
  2980. with exact absolute4 store_int
  2981. kills allexceptcon
  2982. gen move %2, {ABS_off_int, %1.bd, $1}
  2983. with exact abs_con store_int
  2984. kills allexceptcon
  2985. gen move %2, {ABS_off_int, %1.bd, %1.od+$1}
  2986. with exact abs_regXcon store_int
  2987. kills allexceptcon
  2988. gen move %2, {ABS_indoff_int, %1.sc, %1.xreg, %1.bd, %1.od+$1}
  2989. with exact abs_index4 store_int
  2990. kills allexceptcon
  2991. gen move %2, {ABSIND_off_int, %1.sc, %1.xreg, %1.bd, $1}
  2992. with exact absind_con store_int
  2993. kills allexceptcon
  2994. gen move %2, {ABSIND_off_int, %1.sc, %1.xreg, %1.bd, %1.od+$1}
  2995. with exact ext_regX store_int
  2996. kills allexceptcon
  2997. gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
  2998. #endif /* FANCY_MODES */
  2999. #endif /* TBL68020 */
  3000. pat sti $1==1
  3001. with A_REG any1
  3002. kills allexceptcon
  3003. gen move %2, {indirect1, %1}
  3004. with local_addr any1
  3005. kills allexceptcon
  3006. gen move %2, {offsetted1, lb, %1.bd}
  3007. with exact ext_addr any1
  3008. kills allexceptcon
  3009. gen move %2, {absolute1, %1.bd}
  3010. #ifndef TBL68020
  3011. with regAcon any1
  3012. kills allexceptcon
  3013. gen move %2, {offsetted1, %1.reg, %1.bd}
  3014. with regAregXcon any1
  3015. kills allexceptcon
  3016. gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
  3017. #else /* TBL68020 */
  3018. with exact regAcon any1
  3019. kills allexceptcon
  3020. gen move %2, {offsetted1, %1.reg, %1.bd}
  3021. with exact regAregXcon any1
  3022. kills allexceptcon
  3023. gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
  3024. #ifdef FANCY_MODES
  3025. with exact indirect4 any1
  3026. kills allexceptcon
  3027. gen move %2, {OFF_off1, %1.reg, 0, 0}
  3028. with exact offsetted4 any1
  3029. kills allexceptcon
  3030. gen move %2, {OFF_off1, %1.reg, %1.bd, 0}
  3031. with exact LOCAL any1
  3032. kills allexceptcon
  3033. gen move %2, {OFF_off1, lb, %1.bd, 0}
  3034. with exact off_con any1
  3035. kills allexceptcon
  3036. gen move %2, {OFF_off1, %1.reg, %1.bd, %1.od}
  3037. with exact index_off4 any1
  3038. kills allexceptcon
  3039. gen move %2, {INDOFF_off1, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
  3040. with exact indoff_con any1
  3041. kills allexceptcon
  3042. gen move %2, {INDOFF_off1, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  3043. with exact off_regXcon any1
  3044. kills allexceptcon
  3045. gen move %2, {OFF_indoff1, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  3046. with exact absolute4 any1
  3047. kills allexceptcon
  3048. gen move %2, {ABS_off1, %1.bd, 0}
  3049. with exact abs_con any1
  3050. kills allexceptcon
  3051. gen move %2, {ABS_off1, %1.bd, %1.od}
  3052. with exact abs_regXcon any1
  3053. kills allexceptcon
  3054. gen move %2, {ABS_indoff1, %1.sc, %1.xreg, %1.bd, %1.od}
  3055. with exact abs_index4 any1
  3056. kills allexceptcon
  3057. gen move %2, {ABSIND_off1, %1.sc, %1.xreg, %1.bd, 0}
  3058. with exact absind_con any1
  3059. kills allexceptcon
  3060. gen move %2, {ABSIND_off1, %1.sc, %1.xreg, %1.bd, %1.od}
  3061. with exact ext_regX any1
  3062. kills allexceptcon
  3063. gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
  3064. #endif /* FANCY_MODES */
  3065. #endif /* TBL68020 */
  3066. pat sti $1==2
  3067. with A_REG any2
  3068. kills allexceptcon
  3069. gen move %2, {indirect2, %1}
  3070. with local_addr any2
  3071. kills allexceptcon
  3072. gen move %2, {offsetted2, lb, %1.bd}
  3073. with exact ext_addr any2
  3074. kills allexceptcon
  3075. gen move %2, {absolute2, %1.bd}
  3076. #ifndef TBL68020
  3077. with regAcon any2
  3078. kills allexceptcon
  3079. gen move %2, {offsetted2, %1.reg, %1.bd}
  3080. with regAregXcon any2
  3081. kills allexceptcon
  3082. gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
  3083. #else /* TBL68020 */
  3084. with exact regAcon any2
  3085. kills allexceptcon
  3086. gen move %2, {offsetted2, %1.reg, %1.bd}
  3087. with exact regAregXcon any2
  3088. kills allexceptcon
  3089. gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
  3090. #if WORD_SIZE==2
  3091. with exact DLOCAL any2
  3092. kills allexceptcon
  3093. gen move %2, {ILOCAL, %1.bd}
  3094. #endif
  3095. #ifdef FANCY_MODES
  3096. with exact indirect4 any2
  3097. kills allexceptcon
  3098. gen move %2, {OFF_off2, %1.reg, 0, 0}
  3099. with exact offsetted4 any2
  3100. kills allexceptcon
  3101. gen move %2, {OFF_off2, %1.reg, %1.bd, 0}
  3102. with exact LOCAL any2
  3103. kills allexceptcon
  3104. gen move %2, {OFF_off2, lb, %1.bd, 0}
  3105. with exact off_con any2
  3106. kills allexceptcon
  3107. gen move %2, {OFF_off2, %1.reg, %1.bd, %1.od}
  3108. with exact index_off4 any2
  3109. kills allexceptcon
  3110. gen move %2, {INDOFF_off2, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
  3111. with exact indoff_con any2
  3112. kills allexceptcon
  3113. gen move %2, {INDOFF_off2, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  3114. with exact off_regXcon any2
  3115. kills allexceptcon
  3116. gen move %2, {OFF_indoff2, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  3117. with exact absolute4 any2
  3118. kills allexceptcon
  3119. gen move %2, {ABS_off2, %1.bd, 0}
  3120. with exact abs_con any2
  3121. kills allexceptcon
  3122. gen move %2, {ABS_off2, %1.bd, %1.od}
  3123. with exact abs_regXcon any2
  3124. kills allexceptcon
  3125. gen move %2, {ABS_indoff2, %1.sc, %1.xreg, %1.bd, %1.od}
  3126. with exact abs_index4 any2
  3127. kills allexceptcon
  3128. gen move %2, {ABSIND_off2, %1.sc, %1.xreg, %1.bd, 0}
  3129. with exact absind_con any2
  3130. kills allexceptcon
  3131. gen move %2, {ABSIND_off2, %1.sc, %1.xreg, %1.bd, %1.od}
  3132. with exact ext_regX any2
  3133. kills allexceptcon
  3134. gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
  3135. #endif /* FANCY_MODES */
  3136. #endif /* TBL68020 */
  3137. pat sti $1==4
  3138. with A_REG store4-sconsts4
  3139. kills allexceptcon
  3140. gen move %2, {indirect4, %1}
  3141. with exact any4 STACK
  3142. kills allexceptcon
  3143. uses AA_REG = %1
  3144. gen move_l {post_inc4, sp}, {indirect4, %a}
  3145. with exact STACK
  3146. kills allexceptcon
  3147. uses AA_REG
  3148. gen move_l {post_inc4, sp}, %a
  3149. move_l {post_inc4, sp}, {indirect4, %a}
  3150. with exact local_addr store4
  3151. kills allexceptcon
  3152. gen move %2, {DLOCAL, %1.bd}
  3153. with exact ext_addr store4
  3154. kills allexceptcon
  3155. gen move %2, {absolute4, %1.bd}
  3156. #ifndef TBL68020
  3157. with regAcon store4-sconsts4
  3158. kills allexceptcon
  3159. gen move %2, {offsetted4, %1.reg, %1.bd}
  3160. with regAregXcon store4-sconsts4
  3161. kills allexceptcon
  3162. gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
  3163. #else /* TBL68020 */
  3164. with exact regAcon store4
  3165. kills allexceptcon
  3166. gen move %2, {offsetted4, %1.reg, %1.bd}
  3167. with exact regAregXcon store4
  3168. kills allexceptcon
  3169. gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
  3170. #if WORD_SIZE==4
  3171. with exact LOCAL store4
  3172. kills allexceptcon
  3173. gen move %2, {ILOCAL, %1.bd}
  3174. #endif
  3175. #ifdef FANCY_MODES
  3176. with exact indirect4 store4
  3177. kills allexceptcon
  3178. gen move %2, {OFF_off4, %1.reg, 0, 0}
  3179. with exact offsetted4 store4
  3180. kills allexceptcon
  3181. gen move %2, {OFF_off4, %1.reg, %1.bd, 0}
  3182. with exact off_con store4
  3183. kills allexceptcon
  3184. gen move %2, {OFF_off4, %1.reg, %1.bd, %1.od}
  3185. with exact index_off4 store4
  3186. kills allexceptcon
  3187. gen move %2, {INDOFF_off4, %1.reg, %1.xreg, %1.sc, %1.bd, 0}
  3188. with exact indoff_con store4
  3189. kills allexceptcon
  3190. gen move %2, {INDOFF_off4, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  3191. with exact off_regXcon store4
  3192. kills allexceptcon
  3193. gen move %2, {OFF_indoff4, %1.reg, %1.xreg, %1.sc, %1.bd, %1.od}
  3194. with exact absolute4 store4
  3195. kills allexceptcon
  3196. gen move %2, {ABS_off4, %1.bd, 0}
  3197. with exact abs_con store4
  3198. kills allexceptcon
  3199. gen move %2, {ABS_off4, %1.bd, %1.od}
  3200. with exact abs_regXcon store4
  3201. kills allexceptcon
  3202. gen move %2, {ABS_indoff4, %1.sc, %1.xreg, %1.bd, %1.od}
  3203. with exact abs_index4 store4
  3204. kills allexceptcon
  3205. gen move %2, {ABSIND_off4, %1.sc, %1.xreg, %1.bd, 0}
  3206. with exact absind_con store4
  3207. kills allexceptcon
  3208. gen move %2, {ABSIND_off4, %1.sc, %1.xreg, %1.bd, %1.od}
  3209. with exact ext_regX store4
  3210. kills allexceptcon
  3211. gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
  3212. #endif /* FANCY_MODES */
  3213. #endif /* TBL68020 */
  3214. #if WORD_SIZE==2
  3215. pat sti $1==6
  3216. with A_REG any4 any2
  3217. kills ALL
  3218. gen move %2, {indirect4, %1}
  3219. move %3, {offsetted2, %1, 4}
  3220. with AA_REG any4 any2
  3221. kills ALL
  3222. gen move %2, {post_inc4, %1}
  3223. move %3, {post_inc2, %1}
  3224. with exact A_REG STACK
  3225. kills ALL
  3226. gen move_l {post_inc4, sp}, {indirect4, %1}
  3227. move_w {post_inc2, sp}, {offsetted2, %1, 4}
  3228. with exact AA_REG STACK
  3229. kills ALL
  3230. gen move_l {post_inc4, sp}, {post_inc4, %1}
  3231. move_w {post_inc2, sp}, {post_inc2, %1}
  3232. #endif
  3233. pat sti $1==8
  3234. #if WORD_SIZE!=2
  3235. leaving sdf 0
  3236. #else
  3237. with AA_REG any4-pre_post any4-pre_post
  3238. kills ALL
  3239. gen move_l %2,{indirect4, %1}
  3240. move_l %3,{offsetted4, %1, 4}
  3241. with exact local_addr any4-pre_post any4-pre_post
  3242. kills ALL
  3243. gen move_l %2,{offsetted4, lb, %1.bd}
  3244. move_l %3,{offsetted4, lb, %1.bd+4}
  3245. with exact ext_addr any4-pre_post any4-pre_post
  3246. kills ALL
  3247. gen move_l %2,{absolute4, %1.bd}
  3248. move_l %3,{absolute4, %1.bd+4}
  3249. #endif
  3250. #if WORD_SIZE==4
  3251. pat sti $1==3*WORD_SIZE
  3252. with AA_REG STACK
  3253. kills ALL
  3254. gen move_i {post_inc_int, sp},{post_inc_int,%1}
  3255. move_i {post_inc_int, sp},{post_inc_int,%1}
  3256. move_i {post_inc_int, sp},{post_inc_int,%1}
  3257. pat sti $1==4*WORD_SIZE
  3258. with AA_REG STACK
  3259. kills ALL
  3260. gen move_i {post_inc_int, sp},{post_inc_int,%1}
  3261. move_i {post_inc_int, sp},{post_inc_int,%1}
  3262. move_i {post_inc_int, sp},{post_inc_int,%1}
  3263. move_i {post_inc_int, sp},{post_inc_int,%1}
  3264. #endif
  3265. pat sti $1>4*WORD_SIZE && $1/WORD_SIZE <= 65536
  3266. with AA_REG STACK
  3267. kills ALL
  3268. uses DD_REG4 = {const, $1/WORD_SIZE -1}
  3269. gen 1:
  3270. move_i {post_inc_int, sp}, {post_inc_int, %1}
  3271. dbf %a, {slabel, 1b}
  3272. pat sti
  3273. with STACK
  3274. kills ALL
  3275. gen move_i {const, $1}, {pre_dec_int, sp}
  3276. jsr {absolute4, ".sts"}
  3277. pat sts $1==WORD_SIZE
  3278. with STACK
  3279. kills ALL
  3280. gen jsr {absolute4, ".sts"}
  3281. #if WORD_SIZE==2
  3282. pat sts $1==4
  3283. with STACK
  3284. kills ALL
  3285. gen jsr {absolute4, ".sts4"}
  3286. #endif
  3287. #if WORD_SIZE==2
  3288. pat sdl
  3289. with store4-sconsts4
  3290. kills all_indir, DLOCAL %bd==$1
  3291. gen move %1, {DLOCAL, $1}
  3292. with exact STACK
  3293. kills all_indir, DLOCAL %bd==$1
  3294. gen move_l {post_inc4,sp}, {DLOCAL, $1}
  3295. #else
  3296. pat sdl
  3297. with any4-sconsts any4-sconsts
  3298. kills all_indir, LOCAL %bd==$1
  3299. gen move %1, {LOCAL, $1}
  3300. move %2, {LOCAL, $1+4}
  3301. #if TBL68881
  3302. with exact FD_REG
  3303. kills all_indir, LOCAL %bd==$1
  3304. gen fmove_d %1, {LOCAL, $1}
  3305. #endif
  3306. with exact STACK
  3307. kills all_indir, LOCAL %bd==$1
  3308. gen move_l {post_inc4, sp}, {LOCAL,$1}
  3309. move_l {post_inc4, sp}, {LOCAL,$1+4}
  3310. #endif /* WORD_SIZE==2 */
  3311. pat sde
  3312. #if WORD_SIZE==2
  3313. with any4-sconsts4
  3314. kills posextern
  3315. gen move_l %1, {absolute4, $1}
  3316. with exact STACK
  3317. kills posextern
  3318. gen move_l {post_inc4, sp}, {absolute4, $1}
  3319. #else
  3320. with any4-sconsts any4-sconsts
  3321. kills posextern
  3322. gen move %1, {absolute4, $1}
  3323. move %2, {absolute4, $1+4}
  3324. #if TBL68881
  3325. with exact FD_REG
  3326. kills posextern
  3327. gen fmove_d %1, {absolute4, $1}
  3328. #endif
  3329. with exact STACK
  3330. kills posextern
  3331. gen move_l {post_inc4, sp}, {absolute4,$1}
  3332. move_l {post_inc4, sp}, {absolute4,$1+4}
  3333. #endif
  3334. pat sdf
  3335. #if WORD_SIZE==2
  3336. with A_REG any4-sconsts4
  3337. kills allexceptcon
  3338. gen move_l %2, {offsetted4, %1, $1}
  3339. with exact A_REG STACK
  3340. kills allexceptcon
  3341. gen move_l {post_inc4, sp}, {offsetted4, %1, $1}
  3342. #else
  3343. with A_REG any4-sconsts any4-sconsts
  3344. kills allexceptcon
  3345. gen move %2, {offsetted4, %1, $1}
  3346. move %3, {offsetted4, %1, $1+4}
  3347. with exact local_addr any4 any4
  3348. kills allexceptcon
  3349. gen move %2, {LOCAL, %1.bd+$1}
  3350. move %3, {LOCAL, %1.bd+$1+4}
  3351. with regAcon any4-sconsts any4-sconsts
  3352. kills allexceptcon
  3353. gen move %2, {offsetted4, %1.reg, %1.bd+$1}
  3354. move %3, {offsetted4, %1.reg, %1.bd+$1+4}
  3355. #endif
  3356. /************************************************
  3357. * Group 3: integer arithmetic. *
  3358. ************************************************/
  3359. #if WORD_SIZE==2
  3360. pat adi $1==2
  3361. with any2-bconst DD_REG
  3362. gen add_w %1, %2 yields %2
  3363. with DD_REG any2-DD_REG-bconst
  3364. gen add_w %2, %1 yields %1
  3365. with exact any2 STACK
  3366. uses reusing %1,DD_REG=%1
  3367. gen add_w {post_inc2, sp}, %a
  3368. yields %a
  3369. #endif
  3370. pat adi $1==4
  3371. with any4-bconst4 DD_REG4
  3372. gen add_l %1, %2 yields %2
  3373. with DD_REG4 any4-DD_REG4-bconst4
  3374. gen add_l %2, %1 yields %1
  3375. with exact any4 STACK
  3376. uses reusing %1,DD_REG4=%1
  3377. gen add_l {post_inc4, sp}, %a
  3378. yields %a
  3379. #if WORD_SIZE==2
  3380. pat sbi $1==2
  3381. with any2-bconst DD_REG
  3382. gen sub_w %1, %2 yields %2
  3383. with DD_REG any2-DD_REG-bconst
  3384. gen sub_w %2, %1
  3385. neg_w %1 yields %1
  3386. with exact any2 STACK
  3387. uses reusing %1,DD_REG=%1
  3388. gen sub_w {post_inc2, sp}, %a
  3389. neg_w %a yields %a
  3390. #endif
  3391. pat sbi $1==4
  3392. with any4-bconst4 DD_REG4
  3393. gen sub_l %1, %2 yields %2
  3394. with DD_REG4 any4-DD_REG4-bconst4
  3395. gen sub_l %2, %1
  3396. neg_l %1 yields %1
  3397. with exact any4 STACK
  3398. uses reusing %1,DD_REG4=%1
  3399. gen sub_l {post_inc4, sp}, %a
  3400. neg_l %a yields %a
  3401. with any4-bconst4 AA_REG
  3402. gen sub_l %1, %2 yields %2
  3403. #if WORD_SIZE==2
  3404. pat loc loc cii ldc mli $1==2 && $2==4 && highw($4)==0 && loww($4)>0 && $5==4
  3405. with any2-pre_post
  3406. uses reusing %1, DD_REG4
  3407. gen move %1, %a.1
  3408. muls_w {const, loww($4)}, %a.1
  3409. yields %a
  3410. pat mli $1==2
  3411. with any2-pre_post any2-pre_post
  3412. uses reusing %2,DD_REG = %2
  3413. gen muls_w %1, %a yields %a
  3414. #endif
  3415. pat mli $1==4
  3416. #ifdef TBL68020
  3417. with data4 DD_REG4
  3418. gen muls_l %1, %2 yields %2
  3419. #else /* TBL68020 */
  3420. with STACK
  3421. kills ALL
  3422. gen jsr {absolute4, ".mli"}
  3423. yields dl1
  3424. #endif
  3425. #if WORD_SIZE==2
  3426. pat dvi $1==2
  3427. with data2-sconsts DD_REG
  3428. gen ext_l %2
  3429. divs_w %1, %2
  3430. yields %2
  3431. #endif
  3432. pat dvi $1==4
  3433. #ifdef TBL68020
  3434. with data4-sconsts4 DD_REG4
  3435. gen divs_l %1, %2 yields %2
  3436. #else /* TBL68020 */
  3437. with STACK
  3438. kills ALL
  3439. gen jsr {absolute4, ".dvi"}
  3440. yields dl1
  3441. #endif /* TBL68020 */
  3442. #if WORD_SIZE==2
  3443. pat rmi $1==2
  3444. with data2-sconsts DD_REG
  3445. gen ext_l %2
  3446. divs_w %1, %2
  3447. swap %2
  3448. killreg %2
  3449. yields %2
  3450. #endif
  3451. pat rmi $1==4
  3452. #ifdef TBL68020
  3453. with data4-sconsts4 DD_REG4
  3454. uses DD_REG4
  3455. gen divsl_l %1, {DREG_pair, %a, %2}
  3456. killreg %2
  3457. /* !!!! contents of %2 have changed: make this known to cg */
  3458. yields %a
  3459. #else /* TBL68020 */
  3460. with STACK
  3461. kills ALL
  3462. gen jsr {absolute4, ".dvi"}
  3463. yields dl2
  3464. #endif /* TBL68020 */
  3465. #if WORD_SIZE==2
  3466. pat ngi $1==2
  3467. with DD_REG
  3468. gen neg_w %1 yields %1
  3469. #endif
  3470. pat ngi $1==4
  3471. with DD_REG4
  3472. gen neg_l %1 yields %1
  3473. #if WORD_SIZE==2
  3474. pat sli $1==2
  3475. with shconreg DD_REG
  3476. gen asl_w %1, %2 yields %2
  3477. #endif
  3478. pat sli $1==4
  3479. with shconreg DD_REG4
  3480. gen asl_l %1, %2 yields %2
  3481. #if WORD_SIZE==2
  3482. pat sri $1==2
  3483. with shconreg DD_REG
  3484. gen asr_w %1, %2 yields %2
  3485. #endif
  3486. pat sri $1==4
  3487. with shconreg DD_REG4
  3488. gen asr_l %1, %2 yields %2
  3489. /************************************************
  3490. * Group 4: unsigned arithmetic. *
  3491. ************************************************/
  3492. pat adu leaving adi $1
  3493. pat sbu leaving sbi $1
  3494. #if WORD_SIZE==2
  3495. pat mlu $1==2
  3496. with any2-pre_post any2-pre_post
  3497. uses reusing %2,DD_REG = %2
  3498. gen mulu_w %1, %a yields %a
  3499. #endif
  3500. pat mlu $1==4
  3501. #ifdef TBL68020
  3502. with data4-sconsts4 DD_REG4
  3503. gen mulu_l %1, %2 yields %2
  3504. #else /* TBL68020 */
  3505. with STACK
  3506. kills ALL
  3507. gen jsr {absolute4, ".mlu"}
  3508. yields dl1
  3509. #endif /* TBL68020 */
  3510. #if WORD_SIZE==2
  3511. pat dvu $1==2
  3512. with data2-sconsts data2
  3513. uses DD_REG4 = {zero_const4,0}
  3514. gen move %2,%a.1
  3515. divu_w %1, %a.1 yields %a.1
  3516. #endif
  3517. pat dvu $1==4
  3518. #ifdef TBL68020
  3519. with data4-sconsts4 DD_REG4
  3520. gen divu_l %1, %2 yields %2
  3521. #else /* TBL68020 */
  3522. with STACK
  3523. kills ALL
  3524. gen jsr {absolute4, ".dvu"}
  3525. yields dl1
  3526. #endif /* TBL68020 */
  3527. #if WORD_SIZE==2
  3528. pat rmu $1==2
  3529. with data2-sconsts data2
  3530. uses DD_REG4 = {zero_const4, 0}
  3531. gen move %2,%a.1
  3532. divu_w %1, %a.1
  3533. swap %a.1
  3534. killreg %a
  3535. yields %a.1
  3536. #endif
  3537. pat rmu $1==4
  3538. #ifdef TBL68020
  3539. with data4-sconsts4 DD_REG4
  3540. uses DD_REG4
  3541. gen divul_l %1, {DREG_pair, %a, %2}
  3542. killreg %2
  3543. /* !!!! contents of %2 have changed: make this known to cg */
  3544. yields %a
  3545. #else /* TBL68020 */
  3546. with STACK
  3547. kills ALL
  3548. gen jsr {absolute4, ".dvu"}
  3549. yields dl2
  3550. #endif /* TBL68020 */
  3551. pat slu leaving sli $1
  3552. #if WORD_SIZE==2
  3553. pat sru $1==2
  3554. with shconreg DD_REG
  3555. gen lsr_w %1, %2 yields %2
  3556. #endif
  3557. pat sru $1==4
  3558. with shconreg DD_REG4
  3559. gen lsr_l %1, %2 yields %2
  3560. /************************************************
  3561. * Group 5: floating point arithmetic *
  3562. ************************************************/
  3563. /* Floating point stuff
  3564. * Arithmetic instructions
  3565. */
  3566. #if TBL68881
  3567. pat adf stl $1==4
  3568. with FS_REG STACK
  3569. gen fadd_s {post_inc4,sp},%1 yields %1 leaving stl $2
  3570. pat adf sdl $1==8
  3571. with FD_REG STACK
  3572. gen fadd_d {post_inc4,sp},%1 yields %1 leaving sdl $2
  3573. pat sbf stl $1==4
  3574. with FS_REG FS_REG STACK
  3575. gen fsub %1,%2 yields %2 leaving stl $2
  3576. pat sbf sdl $1==8
  3577. with FD_REG FD_REG STACK
  3578. gen fsub %1,%2 yields %2 leaving sdl $2
  3579. pat mlf stl $1==4
  3580. with FS_REG STACK
  3581. gen fmul_s {post_inc4,sp},%1 yields %1 leaving stl $2
  3582. pat mlf sdl $1==8
  3583. with FD_REG STACK
  3584. gen fmul_d {post_inc4,sp},%1 yields %1 leaving sdl $2
  3585. pat dvf stl $1==4
  3586. with FS_REG FS_REG STACK
  3587. gen fdiv %1,%2 yields %2 leaving stl $2
  3588. pat dvf sdl $1==8
  3589. with FD_REG FD_REG STACK
  3590. gen fdiv %1,%2 yields %2 leaving sdl $2
  3591. pat ngf stl $1==4
  3592. with FS_REG STACK
  3593. gen fneg %1 yields %1 leaving stl $2
  3594. pat ngf sdl $1==8
  3595. with FD_REG STACK
  3596. gen fneg %1 yields %1 leaving sdl $2
  3597. pat adf ste $1==4
  3598. with FS_REG STACK
  3599. gen fadd_s {post_inc4,sp},%1 yields %1 leaving ste $2
  3600. pat adf sde $1==8
  3601. with FD_REG STACK
  3602. gen fadd_d {post_inc4,sp},%1 yields %1 leaving sde $2
  3603. pat sbf ste $1==4
  3604. with FS_REG FS_REG STACK
  3605. gen fsub %1,%2 yields %2 leaving ste $2
  3606. pat sbf sde $1==8
  3607. with FD_REG FD_REG STACK
  3608. gen fsub %1,%2 yields %2 leaving sde $2
  3609. pat mlf ste $1==4
  3610. with FS_REG STACK
  3611. gen fmul_s {post_inc4,sp},%1 yields %1 leaving ste $2
  3612. pat mlf sde $1==8
  3613. with FD_REG STACK
  3614. gen fmul_d {post_inc4,sp},%1 yields %1 leaving sde $2
  3615. pat dvf ste $1==4
  3616. with FS_REG FS_REG STACK
  3617. gen fdiv %1,%2 yields %2 leaving ste $2
  3618. pat dvf sde $1==8
  3619. with FD_REG FD_REG STACK
  3620. gen fdiv %1,%2 yields %2 leaving sde $2
  3621. pat ngf ste $1==4
  3622. with FS_REG STACK
  3623. gen fneg %1 yields %1 leaving ste $2
  3624. pat ngf sde $1==8
  3625. with FD_REG STACK
  3626. gen fneg %1 yields %1 leaving sde $2
  3627. pat adf $1==4
  3628. with FS_REG STACK
  3629. gen fadd_s {indirect4,sp},%1
  3630. fmove_s %1,{indirect4,sp}
  3631. pat adf $1==8
  3632. with FD_REG STACK
  3633. gen fadd_d {indirect4,sp},%1
  3634. fmove_d %1,{indirect4,sp}
  3635. pat sbf $1==4
  3636. with FS_REG FS_REG STACK
  3637. gen fsub %1,%2
  3638. fmove_s %2,{pre_dec4,sp}
  3639. pat sbf $1==8
  3640. with FD_REG FD_REG STACK
  3641. gen fsub %1,%2
  3642. fmove_d %2,{pre_dec4,sp}
  3643. pat mlf $1==4
  3644. with FS_REG STACK
  3645. gen fmul_s {indirect4,sp},%1
  3646. fmove_s %1,{indirect4,sp}
  3647. pat mlf $1==8
  3648. with FD_REG STACK
  3649. gen fmul_d {indirect4,sp},%1
  3650. fmove_d %1,{indirect4,sp}
  3651. pat dvf $1==4
  3652. with FS_REG FS_REG STACK
  3653. gen fdiv %1,%2
  3654. fmove_s %2,{pre_dec4,sp}
  3655. pat dvf $1==8
  3656. with FD_REG FD_REG STACK
  3657. gen fdiv %1,%2
  3658. fmove_d %2,{pre_dec4,sp}
  3659. pat ngf $1==4
  3660. with FS_REG STACK
  3661. gen fneg %1
  3662. fmove_s %1,{pre_dec4,sp}
  3663. pat ngf $1==8
  3664. with FD_REG STACK
  3665. gen fneg %1
  3666. fmove_d %1,{pre_dec4,sp}
  3667. pat fif $1==4
  3668. with FS_REG FS_REG STACK
  3669. gen fmul %1,%2
  3670. fintrz %2,%1
  3671. fsub %1,%2
  3672. fmove_s %2,{pre_dec4,sp}
  3673. fmove_s %1,{pre_dec4,sp}
  3674. pat fif $1==8
  3675. with FD_REG FD_REG STACK
  3676. gen fmul %1,%2
  3677. fintrz %2,%1
  3678. fsub %1,%2
  3679. fmove_d %2,{pre_dec4,sp}
  3680. fmove_d %1,{pre_dec4,sp}
  3681. #else
  3682. pat adf $1==4 leaving cal ".adf4" asp 4
  3683. pat adf $1==8 leaving cal ".adf8" asp 8
  3684. pat sbf $1==4 leaving cal ".sbf4" asp 4
  3685. pat sbf $1==8 leaving cal ".sbf8" asp 8
  3686. pat mlf $1==4 leaving cal ".mlf4" asp 4
  3687. pat mlf $1==8 leaving cal ".mlf8" asp 8
  3688. pat dvf $1==4 leaving cal ".dvf4" asp 4
  3689. pat dvf $1==8 leaving cal ".dvf8" asp 8
  3690. pat ngf $1==4 leaving cal ".ngf4"
  3691. pat ngf $1==8 leaving cal ".ngf8"
  3692. pat fif $1==4 leaving lor 1 cal ".fif4" asp 4
  3693. pat fif $1==8 leaving lor 1 cal ".fif8" asp 4
  3694. #endif
  3695. #if WORD_SIZE==2
  3696. pat fef $1==4 leaving lor 1 adp 0-2 cal ".fef4" asp 2
  3697. pat fef $1==8 leaving lor 1 adp 0-2 cal ".fef8" asp 2
  3698. #else
  3699. pat fef $1==4 leaving lor 1 adp 0-4 cal ".fef4"
  3700. pat fef $1==8 leaving lor 1 adp 0-4 cal ".fef8"
  3701. #endif
  3702. /************************************************
  3703. * Group 6: pointer arithmetic *
  3704. ************************************************/
  3705. pat adp $1==0 /* skip; array instructions might 'leave' this */
  3706. pat adp
  3707. with A_REG yields {t_regAcon, %1, $1}
  3708. with exact local_addr yields {local_addr, %1.bd+$1}
  3709. with exact ext_addr yields {ext_addr, %1.bd+$1}
  3710. with exact regAcon + t_regAcon
  3711. yields {t_regAcon, %1.reg, %1.bd+$1}
  3712. with exact regAregXcon + t_regAregXcon
  3713. yields {t_regAregXcon,%1.reg, %1.xreg, %1.sc, %1.bd+$1}
  3714. #if TBL68020 && FANCY_MODES
  3715. with exact indirect4 yields {off_con, %1.reg, 0, $1}
  3716. with exact LOCAL yields {off_con, lb, %1.bd, $1}
  3717. with exact offsetted4 yields {off_con, %1.reg, %1.bd, $1}
  3718. with exact off_con yields {off_con, %1.reg, %1.bd, %1.od+$1}
  3719. with exact index_off4 yields {indoff_con, %1.reg, %1.xreg, %1.sc, %1.bd, $1}
  3720. with exact indoff_con yields {indoff_con,
  3721. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
  3722. with exact off_regXcon yields {off_regXcon,
  3723. %1.reg, %1.xreg, %1.sc, %1.bd, %1.od+$1}
  3724. with exact absolute4 yields {abs_con, %1.bd, $1}
  3725. with exact abs_con yields {abs_con, %1.bd, %1.od+$1}
  3726. with exact abs_regXcon yields {abs_regXcon, %1.sc, %1.xreg, %1.bd, %1.od+$1}
  3727. with exact abs_index4 yields {absind_con, %1.sc, %1.xreg, %1.bd, $1}
  3728. with exact absind_con yields {absind_con, %1.sc, %1.xreg, %1.bd, %1.od+$1}
  3729. with exact ext_regX yields {ext_regX, %1.sc, %1.xreg, %1.bd+$1}
  3730. #endif
  3731. pat ads cmp $1==4
  3732. with DD_REG4 any4
  3733. gen add_l %2, %1 yields %1 leaving cmu 4
  3734. with any4 DD_REG4
  3735. gen add_l %1, %2 yields %2 leaving cmu 4
  3736. #ifdef TBL68020
  3737. with regX AA_REG
  3738. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3739. yields %2 leaving cmu 4
  3740. #endif
  3741. #if WORD_SIZE!=2
  3742. pat ads bne $1==4
  3743. with DD_REG4 any4
  3744. gen add_l %2, %1 yields %1 leaving bne $2
  3745. with any4 DD_REG4
  3746. gen add_l %1, %2 yields %2 leaving bne $2
  3747. #ifdef TBL68020
  3748. with regX AA_REG
  3749. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3750. yields %2 leaving bne $2
  3751. #endif
  3752. pat ads beq $1==4
  3753. with DD_REG4 any4
  3754. gen add_l %2, %1 yields %1 leaving beq $2
  3755. with any4 DD_REG4
  3756. gen add_l %1, %2 yields %2 leaving beq $2
  3757. #ifdef TBL68020
  3758. with regX AA_REG
  3759. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3760. yields %2 leaving beq $2
  3761. #endif
  3762. pat ads LEP bne $1==4
  3763. with DD_REG4 any4
  3764. gen add_l %2, %1 yields %1 leaving LEP $2 bne $3
  3765. with any4 DD_REG4
  3766. gen add_l %1, %2 yields %2 leaving LEP $2 bne $3
  3767. #ifdef TBL68020
  3768. with regX AA_REG
  3769. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3770. yields %2 leaving loe $2 bne $3
  3771. #endif
  3772. pat ads LEP beq $1==4
  3773. with DD_REG4 any4
  3774. gen add_l %2, %1 yields %1 leaving LEP $2 beq $3
  3775. with any4 DD_REG4
  3776. gen add_l %1, %2 yields %2 leaving LEP $2 beq $3
  3777. #ifdef TBL68020
  3778. with regX AA_REG
  3779. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3780. yields %2 leaving loe $2 beq $3
  3781. #endif
  3782. pat ads LEP cmp $1==4
  3783. with DD_REG4 any4
  3784. gen add_l %2, %1 yields %1 leaving LEP $2 cmu 4
  3785. with any4 DD_REG4
  3786. gen add_l %1, %2 yields %2 leaving LEP $2 cmu 4
  3787. #ifdef TBL68020
  3788. with regX AA_REG
  3789. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3790. yields %2 leaving LEP $2 cmu 4
  3791. #endif
  3792. pat ads lae bne $1==4
  3793. with DD_REG4 any4
  3794. gen add_l %2, %1 yields %1 leaving lae $2 bne $3
  3795. with any4 DD_REG4
  3796. gen add_l %1, %2 yields %2 leaving lae $2 bne $3
  3797. #ifdef TBL68020
  3798. with regX AA_REG
  3799. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3800. yields %2 leaving lae $2 bne $3
  3801. #endif
  3802. pat ads lae beq $1==4
  3803. with DD_REG4 any4
  3804. gen add_l %2, %1 yields %1 leaving lae $2 beq $3
  3805. with any4 DD_REG4
  3806. gen add_l %1, %2 yields %2 leaving lae $2 beq $3
  3807. #ifdef TBL68020
  3808. with regX AA_REG
  3809. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3810. yields %2 leaving lae $2 beq $3
  3811. #endif
  3812. #endif /* WORD_SIZE==2 */
  3813. pat ads lae cmp $1==4
  3814. with DD_REG4 any4
  3815. gen add_l %2, %1 yields %1 leaving lae $2 cmu 4
  3816. with any4 DD_REG4
  3817. gen add_l %1, %2 yields %2 leaving lae $2 cmu 4
  3818. #ifdef TBL68020
  3819. with regX AA_REG
  3820. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3821. yields %2 leaving lae $2 cmu 4
  3822. #endif
  3823. #if WORD_SIZE!=2
  3824. pat ads lal bne $1==4
  3825. with DD_REG4 any4
  3826. gen add_l %2, %1 yields %1 leaving lal $2 bne $3
  3827. with any4 DD_REG4
  3828. gen add_l %1, %2 yields %2 leaving lal $2 bne $3
  3829. #ifdef TBL68020
  3830. with regX AA_REG
  3831. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3832. yields %2 leaving lal $2 bne $3
  3833. #endif
  3834. pat ads lal beq $1==4
  3835. with DD_REG4 any4
  3836. gen add_l %2, %1 yields %1 leaving lal $2 beq $3
  3837. with any4 DD_REG4
  3838. gen add_l %1, %2 yields %2 leaving lal $2 beq $3
  3839. #ifdef TBL68020
  3840. with regX AA_REG
  3841. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3842. yields %2 leaving lal $2 beq $3
  3843. #endif
  3844. pat ads lal cmp $1==4
  3845. with DD_REG4 any4
  3846. gen add_l %2, %1 yields %1 leaving lal $2 cmu 4
  3847. with any4 DD_REG4
  3848. gen add_l %1, %2 yields %2 leaving lal $2 cmu 4
  3849. #ifdef TBL68020
  3850. with regX AA_REG
  3851. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3852. yields %2 leaving lal $2 cmu 4
  3853. #endif
  3854. pat ads LLP bne $1==4
  3855. with DD_REG4 any4
  3856. gen add_l %2, %1 yields %1 leaving LLP $2 bne $3
  3857. with any4 DD_REG4
  3858. gen add_l %1, %2 yields %2 leaving LLP $2 bne $3
  3859. #ifdef TBL68020
  3860. with regX AA_REG
  3861. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3862. yields %2 leaving lol $2 bne $3
  3863. #endif
  3864. pat ads LLP beq $1==4
  3865. with DD_REG4 any4
  3866. gen add_l %2, %1 yields %1 leaving LLP $2 beq $3
  3867. with any4 DD_REG4
  3868. gen add_l %1, %2 yields %2 leaving LLP $2 beq $3
  3869. #ifdef TBL68020
  3870. with regX AA_REG
  3871. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3872. yields %2 leaving lol $2 beq $3
  3873. #endif
  3874. #endif /* WORD_SIZE==2 */
  3875. pat ads LLP cmp $1==4
  3876. with DD_REG4 any4
  3877. gen add_l %2, %1 yields %1 leaving LLP $2 cmu 4
  3878. with any4 DD_REG4
  3879. gen add_l %1, %2 yields %2 leaving LLP $2 cmu 4
  3880. #ifdef TBL68020
  3881. with regX AA_REG
  3882. gen move {regAregXcon, %2, %1.xreg, %1.sc, 0},%2
  3883. yields %2 leaving lol $2 cmu 4
  3884. #endif
  3885. #if WORD_SIZE==2
  3886. pat ads $1==2
  3887. leaving loc 2 loc 4 cii ads 4
  3888. #endif
  3889. pat ads $1==4
  3890. with D_REG4 A_REG yields {regAregXcon, %2, %1, 1, 0}
  3891. with D_REG4 regAcon + t_regAcon
  3892. yields {t_regAregXcon, %2.reg, %1, 1, %2.bd}
  3893. with D_REG4 local_addr yields {t_regAregXcon, lb, %1, 1, %2.bd}
  3894. with any4 AA_REG
  3895. gen add_l %1, %2 yields %2
  3896. #ifdef TBL68020
  3897. with D_REG4 yields {regX, 1, %1}
  3898. leaving ads 4
  3899. with regX A_REG yields {regAregXcon, %2, %1.xreg, %1.sc, 0}
  3900. with exact regX regAcon yields {regAregXcon, %2.reg, %1.xreg, %1.sc, %2.bd}
  3901. with exact regX local_addr
  3902. yields {regAregXcon, lb, %1.xreg, %1.sc, %2.bd}
  3903. #ifdef FANCY_MODES
  3904. with exact regX indirect4
  3905. yields {off_regXcon, %2.reg, %1.xreg,%1.sc,0,0}
  3906. with exact regX offsetted4
  3907. yields {off_regXcon, %2.reg, %1.xreg, %1.sc, %2.bd, 0}
  3908. with exact regX DLOCAL yields {off_regXcon, lb, %1.xreg, %1.sc, %2.bd, 0}
  3909. with exact regX off_con yields {off_regXcon, %2.reg, %1.xreg,%1.sc,%2.bd,%2.od}
  3910. with exact regX ext_addr
  3911. yields {ext_regX, %1.sc, %1.xreg, %2.bd}
  3912. with exact regX absolute4
  3913. yields {abs_regXcon, %1.sc, %1.xreg, %2.bd, 0}
  3914. with exact regX abs_con yields {abs_regXcon, %1.sc, %1.xreg, %2.bd, %2.od}
  3915. with exact indirect4 ext_addr
  3916. yields {off_con, %1.reg, 0, %2.bd}
  3917. with exact offsetted4 ext_addr
  3918. yields {off_con, %1.reg, %1.bd, %2.bd}
  3919. with exact LOCAL ext_addr
  3920. yields {off_con, lb, %1.bd, %2.bd}
  3921. with exact index_off4 ext_addr
  3922. yields {indoff_con, %1.reg, %1.xreg, %1.sc,%1.bd,%2.bd}
  3923. with exact absolute4 ext_addr
  3924. yields {abs_con, %1.bd, %2.bd}
  3925. with exact abs_index4 ext_addr
  3926. yields {absind_con, %1.sc, %1.xreg, %1.bd, %2.bd}
  3927. with exact indirect4 ext_regX
  3928. yields {off_regXcon, %1.reg, %2.xreg, %2.sc, 0, %2.bd}
  3929. with exact offsetted4 ext_regX
  3930. yields {off_regXcon, %1.reg, %2.xreg,%2.sc,%1.bd,%2.bd}
  3931. with exact LOCAL ext_regX
  3932. yields {off_regXcon, lb, %2.xreg, %2.sc, %1.bd, %2.bd}
  3933. with exact absolute4 ext_regX
  3934. yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
  3935. #endif /* FANCY_MODES */
  3936. #endif /* TBL68020 */
  3937. /* I WOULD ALSO LIKE THIS:
  3938. * pat ads
  3939. * with const leaving adp %1.num
  3940. * BUT THAT DOESN'T WORK.
  3941. */
  3942. #if WORD_SIZE==2
  3943. pat sbs $1==2
  3944. leaving sbs 4 loc 4 loc 2 cii
  3945. #endif
  3946. pat sbs $1==4 leaving sbi 4
  3947. /* regX type OK ??? */
  3948. #ifdef TBL68020
  3949. pat loc slu $2==4 leaving loc $1 sli 4
  3950. pat loc sli ads $1==1 && $2==4 && $3==4
  3951. with D_REG4 yields {regX, 2, %1}
  3952. leaving ads 4
  3953. pat loc sli ads $1==2 && $2==4 && $3==4
  3954. with D_REG4 yields {regX, 4, %1}
  3955. leaving ads 4
  3956. pat loc sli ads $1==3 && $2==4 && $3==4
  3957. with D_REG4 yields {regX, 8, %1}
  3958. leaving ads 4
  3959. #else
  3960. pat loc sli $1==1 && $2==WORD_SIZE
  3961. with DD_REG
  3962. gen add_i %1, %1 yields %1
  3963. #if WORD_SIZE==2
  3964. pat loc sli $1==1 && $2==4
  3965. with DD_REG4
  3966. gen add_l %1, %1 yields %1
  3967. #endif
  3968. #endif /* TBL68020 */
  3969. /************************************************
  3970. * Group 7: increment / decrement / zero *
  3971. ************************************************/
  3972. pat inc leaving loc 1 adi WORD_SIZE
  3973. pat inl inreg($1)==reg_any
  3974. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  3975. gen add_i {const, 1}, {LOCAL, $1}
  3976. pat inl
  3977. kills all_indir, LOCAL %bd==$1
  3978. gen add_i {const, 1}, {LOCAL, $1}
  3979. pat lol inl $1==$2
  3980. kills all_indir, LOCAL %bd==$1
  3981. uses DD_REG = {LOCAL, $1}
  3982. gen add_i {const, 1}, {LOCAL, $1}
  3983. killreg %a
  3984. yields %a
  3985. pat ine
  3986. kills posextern
  3987. gen add_i {const, 1}, {absolute_int, $1}
  3988. pat dec leaving loc 1 sbi WORD_SIZE
  3989. pat del inreg($1)==reg_any
  3990. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  3991. gen sub_i {const, 1}, {LOCAL, $1}
  3992. pat del
  3993. kills all_indir, LOCAL %bd==$1
  3994. gen sub_i {const, 1}, {LOCAL, $1}
  3995. pat lol del $1==$2
  3996. kills all_indir, LOCAL %bd==$1
  3997. uses DD_REG = {LOCAL, $1}
  3998. gen sub_i {const, 1}, {LOCAL, $1}
  3999. killreg %a
  4000. yields %a
  4001. pat dee
  4002. kills posextern
  4003. gen sub_i {const, 1}, {absolute_int, $1}
  4004. pat zrl inreg($1)==reg_any
  4005. kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
  4006. gen clr_i {LOCAL, $1}
  4007. pat zrl inreg($1)==reg_pointer
  4008. kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
  4009. gen move {const4,0}, {areg, regvar($1, reg_pointer)}
  4010. pat zrl
  4011. kills all_indir, LOCAL %bd==$1
  4012. gen clr_i {LOCAL, $1}
  4013. pat zrl lol $1==$2 && inreg($1) < 0
  4014. kills all_indir, LOCAL %bd==$1
  4015. gen clr_i {LOCAL, $1} yields {zero_const, 0}
  4016. pat zre
  4017. kills posextern
  4018. gen clr_i {absolute_int, $1}
  4019. pat zre loe $1==$2
  4020. kills posextern
  4021. gen clr_i {absolute_int, $1} yields {zero_const, 0}
  4022. pat zer $1==4 yields {zero_const4, 0}
  4023. #if WORD_SIZE==2
  4024. pat zer $1==6 yields {zero_const, 0} {zero_const, 0} {zero_const, 0}
  4025. #else
  4026. pat zer $1==8 yields {zero_const, 0} {zero_const, 0}
  4027. pat zer $1==12 yields {zero_const, 0} {zero_const, 0} {zero_const, 0}
  4028. #endif
  4029. pat zer $1/WORD_SIZE <= 65536
  4030. with STACK
  4031. uses DD_REG4 = {const, $1/WORD_SIZE -1}
  4032. gen 1:
  4033. clr_i {pre_dec_int, sp}
  4034. dbf %a, {slabel, 1b}
  4035. pat zer
  4036. with STACK
  4037. uses DD_REG4 = {const, $1/WORD_SIZE}
  4038. gen 1:
  4039. clr_i {pre_dec_int, sp}
  4040. sub_l {const4,1}, %a
  4041. bne {slabel, 1b}
  4042. /************************************************
  4043. * Group 8: convert instructions *
  4044. ************************************************/
  4045. pat cii
  4046. with STACK
  4047. kills ALL
  4048. gen jsr {absolute4, ".cii"}
  4049. #if WORD_SIZE==2
  4050. /* No sign-extension, though this is probably not what you may want.
  4051. * This will teach compiler writers not to convert between unsigneds and
  4052. * integers of a different size.
  4053. */
  4054. pat loc loc ciu $1==2 && $2==4
  4055. with zero_const
  4056. yields {zero_const4, 0}
  4057. with any
  4058. uses DD_REG4 = {zero_const4, 0}
  4059. gen move %1,%a.1
  4060. yields %a
  4061. pat loc loc ciu $1==4 && $2==2
  4062. with zero_const4
  4063. yields {zero_const, 0}
  4064. with any4
  4065. uses reusing %1, DD_REG4 = %1
  4066. yields %a.1
  4067. pat loc loc cui $1==2 && $2==4
  4068. with any2
  4069. uses DD_REG4={zero_const4,0}
  4070. gen move %1,%a.1 yields %a
  4071. pat loc loc cui $1==4 && $2==2
  4072. with DD_REG4
  4073. yields %1.1
  4074. pat loc loc cuu $1==2 && $2==4
  4075. with any2
  4076. uses reusing %1,DD_REG4
  4077. gen move %1,%a.1
  4078. and_l {const4,65535}, %a yields %a
  4079. with any2
  4080. uses DD_REG4={zero_const4,0}
  4081. gen move %1,%a.1 yields %a
  4082. pat loc loc cuu $1==4 && $2==2
  4083. with DD_REG4
  4084. yields %1.1
  4085. #endif
  4086. pat cuu
  4087. with STACK
  4088. kills ALL
  4089. gen jsr {absolute4, ".cuu"}
  4090. pat ciu leaving cuu
  4091. pat cui leaving cuu
  4092. #if TBL68881
  4093. pat loc loc cif $1==4 && $2==4
  4094. with data4 STACK
  4095. uses FS_REG
  4096. gen fmove_l %1,%a
  4097. fmove_s %a,{pre_dec4,sp}
  4098. pat loc loc cif $1==4 && $2==8
  4099. with data4 STACK
  4100. uses FD_REG
  4101. gen fmove_l %1,%a
  4102. fmove_d %a,{pre_dec4,sp}
  4103. pat loc loc cuf $1==4 && $2==4
  4104. with D_REG STACK
  4105. uses FS_REG
  4106. gen fmove_l %1,%a
  4107. tst_l %1
  4108. bge {slabel, 1f}
  4109. fsub_l {const,0-2147483648},%a
  4110. fsub_l {const,0-2147483648},%a
  4111. 1:
  4112. fmove_s %a,{pre_dec4,sp}
  4113. pat loc loc cuf $1==4 && $2==8
  4114. with D_REG STACK
  4115. uses FD_REG
  4116. gen fmove_l %1,%a
  4117. tst_l %1
  4118. bge {slabel, 1f}
  4119. fsub_l {const,0-2147483648},%a
  4120. fsub_l {const,0-2147483648},%a
  4121. 1:
  4122. fmove_d %a,{pre_dec4,sp}
  4123. pat loc loc cfi $1==4 && $2==4
  4124. with FS_REG
  4125. uses D_REG
  4126. gen fintrz %1,%1
  4127. fmove_l %1,%a yields %a
  4128. pat loc loc cfi $1==8 && $2==4
  4129. with FD_REG
  4130. uses D_REG
  4131. gen fintrz %1,%1
  4132. fmove_l %1,%a yields %a
  4133. pat loc loc cfu $1==4 && $2==4
  4134. with FS_REG
  4135. uses D_REG
  4136. gen fabs %1
  4137. fintrz %1,%1
  4138. fmove_l %1,%a yields %a
  4139. pat loc loc cfu $1==8 && $2==4
  4140. with FD_REG
  4141. uses D_REG
  4142. gen fabs %1
  4143. fintrz %1,%1
  4144. fmove_l %1,%a yields %a
  4145. pat loc loc cff $1==4 && $2==8
  4146. with FS_REG STACK
  4147. gen fmove_d %1,{pre_dec4,sp}
  4148. pat loc loc cff $1==8 && $2==4
  4149. with FD_REG STACK
  4150. gen fmove_s %1,{pre_dec4,sp}
  4151. #else
  4152. /*
  4153. * Floating point stuff
  4154. * Conversion
  4155. */
  4156. #if WORD_SIZE==2
  4157. /* The patterns need some room on the stack first */
  4158. pat loc loc cif $1==2 && $2==4 leaving loc $1 cal ".cif4"
  4159. pat loc loc cif $1==2 && $2==8
  4160. with any2
  4161. kills ALL
  4162. gen clr_l {pre_dec4, sp}
  4163. move_w %1,{pre_dec2, sp} leaving loc $1 cal ".cif8"
  4164. pat loc loc cif $1==4 && $2==4 leaving loc $1 cal ".cif4" asp 2
  4165. pat loc loc cif $1==4 && $2==8
  4166. with any4
  4167. kills ALL
  4168. gen clr_w {pre_dec2, sp}
  4169. move_l %1,{pre_dec4, sp} leaving loc $1 cal ".cif8"
  4170. pat loc loc cuf $1==2 && $2==4 leaving loc $1 cal ".cuf4"
  4171. pat loc loc cuf $1==2 && $2==8
  4172. with any2
  4173. kills ALL
  4174. gen clr_l {pre_dec4, sp}
  4175. move_w %1,{pre_dec2, sp} leaving loc $1 cal ".cuf8"
  4176. pat loc loc cuf $1==4 && $2==4 leaving loc $1 cal ".cuf4" asp 2
  4177. pat loc loc cuf $1==4 && $2==8
  4178. with any4
  4179. kills ALL
  4180. gen clr_w {pre_dec2, sp}
  4181. move_l %1,{pre_dec4, sp} leaving loc $1 cal ".cuf8"
  4182. pat loc loc cfi $1==4 && ($2==2 || $2==4)
  4183. leaving loc $1 loc $2 cal ".cfi" asp 8-$2
  4184. pat loc loc cfi $1==8 && ($2==2 || $2==4)
  4185. leaving loc $1 loc $2 cal ".cfi" asp 12-$2
  4186. pat loc loc cfu $1==4 && ($2==2 || $2==4)
  4187. leaving loc $1 loc $2 cal ".cfu" asp 8-$2
  4188. pat loc loc cfu $1==8 && ($2==2 || $2==4)
  4189. leaving loc $1 loc $2 cal ".cfu" asp 12-$2
  4190. #else
  4191. pat loc loc cif $1==4 && $2==4 leaving loc 4 cal ".cif4" asp 4
  4192. pat loc loc cif $1==4 && $2==8 leaving loc 4 cal ".cif8"
  4193. pat loc loc cuf $1==4 && $2==4 leaving loc 4 cal ".cuf4" asp 4
  4194. pat loc loc cuf $1==4 && $2==8 leaving loc 4 cal ".cuf8"
  4195. pat loc loc cfi leaving loc $1 loc $2 cal ".cfi" asp $1+4
  4196. pat loc loc cfu leaving loc $1 loc $2 cal ".cfu" asp $1+4
  4197. #endif
  4198. pat loc loc cff $1==8 && $2==4 leaving cal ".cff4" asp 4
  4199. pat loc loc cff $1==4 && $2==8
  4200. leaving zer 4 exg 4 cal ".cff8"
  4201. #endif /* TBL68881 */
  4202. /************************************************
  4203. * Group 9: logical instructions *
  4204. ************************************************/
  4205. #if WORD_SIZE==2
  4206. proc log2w
  4207. with datalt4+consts4-sconsts4 DD_REG4
  4208. gen xxx* %1, %2 yields %2
  4209. with DD_REG4 datalt4+consts4-sconsts4
  4210. gen xxx* %2, %1 yields %1
  4211. with exact any4 STACK
  4212. uses reusing %1,DD_REG4=%1
  4213. gen xxx* {post_inc4, sp}, %a yields %a
  4214. #endif
  4215. proc logw
  4216. with datalt_int+consts-sconsts DD_REG
  4217. gen xxx* %1, %2 yields %2
  4218. with DD_REG datalt_int+consts-sconsts
  4219. gen xxx* %2, %1 yields %1
  4220. with exact any_int STACK
  4221. uses reusing %1,DD_REG=%1
  4222. gen xxx* {post_inc_int, sp}, %a yields %a
  4223. proc logdef example and
  4224. with STACK
  4225. uses DD_REG4 = {const, $1/WORD_SIZE -1},
  4226. AA_REG,
  4227. DD_REG
  4228. gen
  4229. lea {regAcon, sp, $1}, %b
  4230. 1:
  4231. move_i {post_inc_int, sp}, %c
  4232. xxx* %c, {post_inc_int, %b}
  4233. dbf %a, {slabel, 1b}
  4234. #if WORD_SIZE==4
  4235. proc logndef
  4236. with DD_REG4 STACK
  4237. uses AA_REG,
  4238. DD_REG
  4239. gen
  4240. lea {regAregXcon, sp, %1, 1, 0},%a
  4241. asr_l {small_const, 2}, %1
  4242. 1:
  4243. move_i {post_inc_int, sp}, %b
  4244. xxx* %b, {post_inc_int, %a}
  4245. sub_l {const4,1}, %1
  4246. bne {slabel, 1b}
  4247. #else
  4248. proc logndef
  4249. with any_int STACK
  4250. uses AA_REG,
  4251. DD_REG,
  4252. DD_REG4={const,0}
  4253. gen
  4254. move %1, %c.1
  4255. lea {regAregXcon, sp, %c, 1, 0},%a
  4256. asr_l {small_const, 1}, %c
  4257. sub_l {const4,1}, %c
  4258. 1:
  4259. move_i {post_inc_int, sp}, %b
  4260. xxx* %b, {post_inc_int, %a}
  4261. dbf %c, {slabel, 1b}
  4262. #endif
  4263. proc logbdef example and
  4264. with STACK
  4265. uses AA_REG,
  4266. DD_REG,
  4267. DD_REG4
  4268. gen
  4269. move_l {const4,$1/WORD_SIZE}, %c
  4270. lea {regAregXcon, sp, %c, 1, 0},%a
  4271. 1:
  4272. move_i {post_inc_int, sp}, %b
  4273. xxx* %b, {post_inc_int, %a}
  4274. sub_l {const4,1}, %c
  4275. bne {slabel, 1b}
  4276. pat and $1==WORD_SIZE call logw(AND_I)
  4277. #if WORD_SIZE==2
  4278. pat and $1==2*WORD_SIZE call log2w("and.l")
  4279. #endif
  4280. pat and $1>4 && $1/WORD_SIZE<=65536 call logdef(AND_I)
  4281. pat and defined($1) call logbdef(AND_I)
  4282. pat and !defined($1) call logndef(AND_I)
  4283. pat ior $1==WORD_SIZE call logw(OR_I)
  4284. #if WORD_SIZE==2
  4285. pat ior $1==2*WORD_SIZE call log2w("or.l")
  4286. #endif
  4287. pat ior $1>2 && $1/WORD_SIZE<=65536 call logdef(OR_I)
  4288. pat ior defined($1) call logbdef(OR_I)
  4289. pat ior !defined($1) call logndef(OR_I)
  4290. #if WORD_SIZE==2
  4291. pat xor $1==2
  4292. with DD_REG conreg2-bconst
  4293. gen eor_w %2, %1 yields %1
  4294. #endif
  4295. pat xor $1==4
  4296. with DD_REG4 conreg4-bconst4
  4297. gen eor_l %2, %1 yields %1
  4298. pat xor $1>4 && $1/WORD_SIZE<=65536 call logdef(EOR_I)
  4299. pat xor defined($1) call logbdef(EOR_I)
  4300. pat xor !defined($1) call logndef(EOR_I)
  4301. #if WORD_SIZE==2
  4302. pat com $1==2
  4303. with DD_REG
  4304. gen not_w %1 yields %1
  4305. #endif
  4306. pat com $1==4
  4307. with DD_REG4
  4308. gen not_l %1 yields %1
  4309. pat com $1==8
  4310. with DD_REG4 DD_REG4
  4311. gen not_l %1
  4312. not_l %2 yields %2 %1
  4313. pat com $1>8 && $1/WORD_SIZE<=65536
  4314. with STACK
  4315. uses AA_REG,
  4316. DD_REG4 = {const, $1/WORD_SIZE -1}
  4317. gen move_l sp, %a
  4318. 1:
  4319. not_i {post_inc_int, %a}
  4320. dbf %b, {slabel, 1b}
  4321. pat com defined($1)
  4322. with STACK
  4323. uses AA_REG,
  4324. DD_REG4 = {const, $1/WORD_SIZE}
  4325. gen move_l sp, %a
  4326. 1:
  4327. not_i {post_inc_int, %a}
  4328. sub_l {const4, 1}, %b
  4329. bne {slabel, 1b}
  4330. #if WORD_SIZE==4
  4331. pat com !defined($1)
  4332. with DD_REG STACK
  4333. uses AA_REG
  4334. gen move_l sp, %a
  4335. asr_l {small_const, 2}, %1
  4336. 1:
  4337. not_i {post_inc_int, %a}
  4338. sub_l {const4, 1}, %1
  4339. bne {slabel, 1b}
  4340. #else
  4341. pat com !defined($1)
  4342. with any_int STACK
  4343. uses AA_REG,
  4344. DD_REG4={const,0}
  4345. gen move %1, %b.1
  4346. move_l sp, %a
  4347. asr_l {small_const, 1}, %b
  4348. sub_l {const4, 1}, %b
  4349. 1:
  4350. not_i {post_inc_int, %a}
  4351. dbf %b, {slabel, 1b}
  4352. #endif
  4353. #if WORD_SIZE==2
  4354. pat rol $1==2
  4355. with shconreg DD_REG
  4356. gen rol_w %1, %2 yields %2
  4357. #endif
  4358. pat rol $1==4
  4359. with shconreg DD_REG4
  4360. gen rol_l %1, %2 yields %2
  4361. #if WORD_SIZE==2
  4362. pat ror $1==2
  4363. with shconreg DD_REG
  4364. gen ror_w %1, %2 yields %2
  4365. #endif
  4366. pat ror $1==4
  4367. with shconreg DD_REG4
  4368. gen ror_l %1, %2 yields %2
  4369. /************************************************
  4370. * Group 10: sets *
  4371. ************************************************/
  4372. #if WORD_SIZE==2
  4373. pat inn $1==4
  4374. with conreg2 DD_REG4
  4375. gen btst %1, %2.1
  4376. sne {dreg1, %2.1}
  4377. and_l {const4, 1}, %2
  4378. yields %2.1
  4379. #endif
  4380. pat inn $1==WORD_SIZE
  4381. with conreg2 DD_REG
  4382. gen btst %1, %2
  4383. sne {dreg1, %2}
  4384. and_i {const, 1}, %2
  4385. yields %2
  4386. /* The interface for the .inn differ for m68k2 and m68k4. */
  4387. /* ??? Work out a cleaner interface, that is similar for all tables */
  4388. #if WORD_SIZE==2
  4389. pat inn defined($1)
  4390. with STACK
  4391. kills ALL
  4392. gen move {const, $1}, d0
  4393. jsr {absolute4, ".inn"}
  4394. killreg d0
  4395. yields d0
  4396. pat inn !defined($1)
  4397. with any_int STACK
  4398. kills ALL
  4399. gen move %1, d0
  4400. jsr {absolute4, ".inn"}
  4401. killreg d0
  4402. yields d0
  4403. #else
  4404. pat inn defined($1)
  4405. with any_int STACK
  4406. kills ALL
  4407. gen move %1, d0
  4408. move {const, $1}, d1
  4409. jsr {absolute4, ".inn"}
  4410. killreg d0
  4411. yields d0
  4412. pat inn !defined($1)
  4413. with any_int any_int STACK
  4414. kills ALL
  4415. gen move %2, d0
  4416. move %1, d1
  4417. jsr {absolute4, ".inn"}
  4418. killreg d0
  4419. yields d0
  4420. #endif /* WORD_SIZE==2 */
  4421. pat loc inn $2==WORD_SIZE && small($1)
  4422. with DD_REG
  4423. gen asr_i {small_const, $1}, %1
  4424. and_i {const, 1}, %1
  4425. yields %1
  4426. #if WORD_SIZE==2
  4427. pat set $1==2
  4428. with conreg2
  4429. uses DD_REG = {zero_const, 0}
  4430. gen bset %1, %a yields %a
  4431. #else
  4432. pat set $1==4
  4433. with conreg2
  4434. uses DD_REG4 = {zero_const4, 0}
  4435. gen bset %1, %a yields %a
  4436. #endif
  4437. #if WORD_SIZE==2
  4438. pat set $1>2
  4439. with STACK
  4440. kills ALL
  4441. gen move {const, $1}, d0
  4442. jsr {absolute4, ".set"}
  4443. pat set !defined($1)
  4444. with any_int STACK
  4445. kills ALL
  4446. gen move %1, d0
  4447. jsr {absolute4, ".set"}
  4448. #else
  4449. pat set $1>4
  4450. with any_int STACK
  4451. kills ALL
  4452. gen move %1, d0
  4453. move {const, $1}, d1
  4454. jsr {absolute4, ".set"}
  4455. pat set !defined($1)
  4456. with any_int any_int STACK
  4457. kills ALL
  4458. gen move %2, d0
  4459. move %1, d1
  4460. jsr {absolute4, ".set"}
  4461. #endif /* WORD_SIZE==2 */
  4462. /************************************************
  4463. * Group 11: arrays *
  4464. ************************************************/
  4465. /* ??? interface */
  4466. #if WORD_SIZE==2
  4467. pat lar defined($1) && $1 == WORD_SIZE
  4468. with STACK
  4469. kills ALL
  4470. gen jsr {absolute4, ".lar"}
  4471. pat sar defined($1) && $1 == WORD_SIZE
  4472. with STACK
  4473. kills ALL
  4474. gen jsr {absolute4, ".sar"}
  4475. pat aar defined($1) && $1 == WORD_SIZE
  4476. with STACK
  4477. kills ALL
  4478. gen jsr {absolute4, ".aar"}
  4479. #else
  4480. pat lar defined($1)
  4481. with STACK
  4482. kills ALL
  4483. gen move {const, $1}, d0
  4484. jsr {absolute4, ".lar"}
  4485. pat lar !defined($1)
  4486. with any_int STACK
  4487. kills ALL
  4488. gen move %1, d0
  4489. jsr {absolute4, ".lar"}
  4490. pat sar defined($1)
  4491. with STACK
  4492. kills ALL
  4493. gen move {const, $1}, d0
  4494. jsr {absolute4, ".sar"}
  4495. pat sar !defined($1)
  4496. with any_int STACK
  4497. kills ALL
  4498. gen move %1, d0
  4499. jsr {absolute4, ".sar"}
  4500. pat aar defined($1)
  4501. with STACK
  4502. kills ALL
  4503. gen move {const, $1}, d0
  4504. jsr {absolute4, ".aar"}
  4505. yields a0
  4506. pat aar !defined($1)
  4507. with any_int STACK
  4508. kills ALL
  4509. gen move %1, d0
  4510. jsr {absolute4, ".aar"}
  4511. yields a0
  4512. #if ARR_OPT
  4513. pat lae lar $2==4 && nicesize(rom($1,3))
  4514. leaving lae $1 aar 4 loi rom($1, 3)
  4515. pat lae sar $2==4 && nicesize(rom($1,3))
  4516. leaving lae $1 aar 4 sti rom($1, 3)
  4517. pat lae aar $2==4 && rom($1,3)==1
  4518. leaving ads 4 adp 0-rom($1,1)
  4519. #ifdef TBL68020
  4520. pat lae aar $2==4 && nicesize(rom($1,3))
  4521. with D_REG yields {regX, rom($1,3), %1}
  4522. leaving ads 4 adp rom($1,3)*(0-rom($1,1))
  4523. #else /* TBL68020 */
  4524. pat lae aar $2==4 && rom($1,3)==2
  4525. with DD_REG
  4526. gen asl_l {small_const, 1}, %1
  4527. yields %1
  4528. leaving ads 4 adp (0 - rom($1,1))<<1
  4529. pat lae aar $2==4 && rom($1,3)==4
  4530. with DD_REG
  4531. gen asl_l {small_const, 2}, %1
  4532. yields %1
  4533. leaving ads 4 adp (0 - rom($1,1))<<2
  4534. pat lae aar $2==4 && rom($1,3)==8
  4535. with DD_REG
  4536. gen asl_l {small_const, 3}, %1
  4537. yields %1
  4538. leaving ads 4 adp (0 - rom($1,1))<<3
  4539. #endif /* TBL68020 */
  4540. #endif /* ARR_OPT */
  4541. #endif /* WORD_SIZE!=2 */
  4542. /* I WOULD ALSO LIKE THESE:
  4543. * pat lae aar $2==4 && defined(rom($1,3))
  4544. * with const leaving adp rom($1,3)*(%1.num-rom($1,1))
  4545. * pat lae lar $2==4 && defined(rom($1,3))
  4546. * with const leaving adp rom($1,3)*(%1.num-rom($1,1))
  4547. * loi rom($1,3)
  4548. * pat lae sar $2==4 && defined(rom($1,3))
  4549. * with const leaving adp rom($1,3)*(%1.num-rom($1,1))
  4550. * sti rom($1,3)
  4551. * BUT THEY DON'T WORK.
  4552. */
  4553. /************************************************
  4554. * Group 12: compare instructions *
  4555. ************************************************/
  4556. #if WORD_SIZE==2
  4557. pat cmi defined($1) && $1==2
  4558. with any2 DD_REG
  4559. uses DD_REG = {zero_const, 0}
  4560. gen cmp_w %1,%2
  4561. beq {slabel,2f}
  4562. bgt {slabel,1f}
  4563. add_w {small_const, 1},%a
  4564. bra {slabel,2f}
  4565. 1:
  4566. sub_w {small_const, 1},%a
  4567. 2:
  4568. yields %a
  4569. pat cmi defined($1) && $1==4
  4570. with STACK
  4571. gen jsr {absolute4, ".cmi"} yields d1
  4572. #else
  4573. /* pat cmi $1==4 leaving sbi 4
  4574. WRONG !!
  4575. */
  4576. pat cmi defined($1)
  4577. with STACK
  4578. kills ALL
  4579. gen move {const, $1}, d0
  4580. jsr {absolute4, ".cmi"}
  4581. yields d0
  4582. pat cmi !defined($1)
  4583. with any_int STACK
  4584. kills ALL
  4585. gen move %1, d0
  4586. jsr {absolute4, ".cmi"}
  4587. yields d0
  4588. #endif
  4589. /* pat cmu $1==4 leaving sbi 4
  4590. WRONG !!
  4591. */
  4592. #if WORD_SIZE==2
  4593. pat cmu defined($1)
  4594. with STACK
  4595. gen move {const, $1},d0
  4596. jsr {absolute4, ".cmu"}
  4597. pat cmu !defined($1)
  4598. with any STACK
  4599. gen move %1,d0
  4600. jsr {absolute4, ".cmu"}
  4601. #else
  4602. pat cmu defined($1)
  4603. with STACK
  4604. kills ALL
  4605. gen move {const, $1}, d0
  4606. jsr {absolute4, ".cmu"}
  4607. yields d0
  4608. pat cmu !defined($1)
  4609. with any_int STACK
  4610. kills ALL
  4611. gen move %1, d0
  4612. jsr {absolute4, ".cmu"}
  4613. yields d0
  4614. #endif /* WORD_SIZE==2 */
  4615. #if WORD_SIZE==2
  4616. pat cms $1==2 leaving cmi 2
  4617. pat cms $1==4 leaving cmi 4
  4618. #else
  4619. pat cms $1==4 leaving cmi 4
  4620. #endif
  4621. pat cms defined($1)
  4622. with STACK
  4623. kills ALL
  4624. gen move {const, $1}, d0
  4625. jsr {absolute4, ".cms"}
  4626. yields d0
  4627. pat cms !defined($1)
  4628. with any_int STACK
  4629. kills ALL
  4630. gen move %1, d0
  4631. jsr {absolute4, ".cms"}
  4632. yields d0
  4633. pat cmp leaving cmu 4
  4634. #ifndef XXXXX
  4635. proc txx
  4636. with test_set_int
  4637. uses reusing %1,DD_REG
  4638. gen test %1
  4639. bxx[1] {slabel,1f}
  4640. clr_i %a
  4641. bra {slabel,2f}
  4642. 1:
  4643. move_i {small_const,1},%a
  4644. 2:
  4645. yields %a
  4646. #if WORD_SIZE==2
  4647. with test_set1
  4648. #else
  4649. with test_set1 + test_set2
  4650. #endif
  4651. uses reusing %1,DD_REG
  4652. gen test %1
  4653. bxx[2] {slabel,1f}
  4654. clr_i %a
  4655. bra {slabel,2f}
  4656. 1:
  4657. move_i {small_const,1},%a
  4658. 2:
  4659. yields %a
  4660. /* for some branches, we need to get rid of the overflow bit first.
  4661. The easiest way to do this is to just test ....
  4662. */
  4663. proc txx_ouch
  4664. with test_set_int
  4665. uses reusing %1,DD_REG
  4666. gen killcc.
  4667. test %1
  4668. bxx[1] {slabel,1f}
  4669. clr_i %a
  4670. bra {slabel,2f}
  4671. 1:
  4672. move_i {small_const,1},%a
  4673. 2:
  4674. yields %a
  4675. #if WORD_SIZE==2
  4676. with test_set1
  4677. #else
  4678. with test_set1 + test_set2
  4679. #endif
  4680. uses reusing %1,DD_REG
  4681. gen test %1
  4682. bxx[2] {slabel,1f}
  4683. clr_i %a
  4684. bra {slabel,2f}
  4685. 1:
  4686. move_i {small_const,1},%a
  4687. 2:
  4688. yields %a
  4689. pat tlt call txx("bmi", "bcs")
  4690. pat tle call txx_ouch("ble", "bls")
  4691. pat teq call txx("beq", "beq")
  4692. pat tne call txx("bne", "bne")
  4693. pat tge call txx("bpl", "bcc")
  4694. pat tgt call txx_ouch("bgt", "bhi")
  4695. #else
  4696. proc txx
  4697. with test_set_int
  4698. uses reusing %1,DD_REG
  4699. gen test %1
  4700. sxx[1] %a
  4701. neg_b %a
  4702. yields {extend1, %a}
  4703. #if WORD_SIZE==2
  4704. with test_set1
  4705. #else
  4706. with test_set1 + test_set2
  4707. #endif
  4708. uses reusing %1,DD_REG
  4709. gen test %1
  4710. sxx[2] %a
  4711. neg_b %a
  4712. yields {extend1, %a}
  4713. pat tlt call txx("smi", "scs")
  4714. pat tle call txx("sle", "sls")
  4715. pat teq call txx("seq", "seq")
  4716. pat tne call txx("sne", "sne")
  4717. pat tge call txx("spl", "scc")
  4718. pat tgt call txx("sgt", "shi")
  4719. #endif
  4720. /*
  4721. * Floating point
  4722. * Comparision
  4723. */
  4724. #if TBL68881
  4725. pat cmf $1==4
  4726. with FS_REG FS_REG
  4727. uses D_REG={const,0}
  4728. gen fcmp %1,%2
  4729. fbeq {slabel,2f}
  4730. fblt {slabel,1f}
  4731. add_l {const,1},%a
  4732. bra {slabel,2f}
  4733. 1:
  4734. sub_l {const,1},%a
  4735. 2: yields %a
  4736. pat cmf $1==8
  4737. with FD_REG FD_REG
  4738. uses D_REG={const,0}
  4739. gen fcmp %1,%2
  4740. fbeq {slabel,2f}
  4741. fblt {slabel,1f}
  4742. add_l {const,1},%a
  4743. bra {slabel,2f}
  4744. 1:
  4745. sub_l {const,1},%a
  4746. 2: yields %a
  4747. #else
  4748. pat cmf $1==4 leaving cal ".cmf4" asp 8 lfr WORD_SIZE
  4749. pat cmf $1==8 leaving cal ".cmf8" asp 16 lfr WORD_SIZE
  4750. #endif
  4751. /*
  4752. * Floating Point
  4753. * Zero Constants
  4754. */
  4755. pat zrf leaving zer $1
  4756. /************************************************
  4757. * Group 13: branch instructions *
  4758. ************************************************/
  4759. #if WORD_SIZE==2
  4760. pat lab topeltsize($1)==4 && !fallthrough($1)
  4761. kills ALL
  4762. gen labeldef $1 yields dl0
  4763. pat lab topeltsize($1)==4 && fallthrough($1)
  4764. with any4 STACK
  4765. kills ALL
  4766. gen move %1, dl0
  4767. killreg dl0
  4768. labeldef $1 yields dl0
  4769. #endif
  4770. pat lab topeltsize($1)==WORD_SIZE && !fallthrough($1)
  4771. kills ALL
  4772. gen labeldef $1 yields d0
  4773. pat lab topeltsize($1)==WORD_SIZE && fallthrough($1)
  4774. with any_int STACK
  4775. kills ALL
  4776. gen move %1,d0
  4777. killreg d0
  4778. labeldef $1 yields d0
  4779. pat lab
  4780. with STACK
  4781. kills ALL
  4782. gen labeldef $1
  4783. #if WORD_SIZE==2
  4784. pat bra topeltsize($1)==4
  4785. with any4 STACK
  4786. gen move %1,dl0
  4787. bra {llabel, $1}
  4788. #endif
  4789. pat bra topeltsize($1)==WORD_SIZE
  4790. with any_int STACK
  4791. gen move %1,d0
  4792. bra {llabel, $1}
  4793. pat bra
  4794. with STACK
  4795. gen bra {llabel, $1}
  4796. proc brxx example beq
  4797. with exact extend1 extend1
  4798. kills ALL
  4799. gen cmp_b %1,%2
  4800. bxx[1] {llabel, $1}
  4801. #if WORD_SIZE!=2
  4802. with exact extend2 extend2
  4803. kills ALL
  4804. gen cmp_w %1,%2
  4805. bxx[1] {llabel, $1}
  4806. #endif
  4807. with exact sconsts any_int
  4808. kills ALL
  4809. uses DD_REG=%1
  4810. gen cmp_i %2, %a
  4811. bxx[2] {llabel, $1}
  4812. with exact any_int sconsts
  4813. kills ALL
  4814. uses DD_REG=%2
  4815. gen cmp_i %1, %a
  4816. bxx[1] {llabel, $1}
  4817. with any_int-sconsts genreg STACK
  4818. gen cmp_i %1, %2
  4819. bxx[1] {llabel, $1}
  4820. with genreg any_int-sconsts STACK
  4821. gen cmp_i %2, %1
  4822. bxx[2] {llabel, $1}
  4823. with exact immediate_int-sconsts imm_cmp_int
  4824. kills ALL
  4825. gen cmp_i %1, %2
  4826. bxx[1] {llabel, $1}
  4827. with exact imm_cmp_int immediate_int-sconsts
  4828. kills ALL
  4829. gen cmp_i %2, %1
  4830. bxx[2] {llabel, $1}
  4831. with exact immediate_int-sconsts STACK
  4832. gen cmp_i %1, {post_inc_int, sp}
  4833. bxx[1] {llabel, $1}
  4834. with exact any_int STACK
  4835. uses reusing %1,DD_REG=%1
  4836. gen cmp_i {post_inc_int, sp}, %a
  4837. bxx[2] {llabel, $1}
  4838. with exact STACK
  4839. uses DD_REG
  4840. gen move_i {post_inc_int, sp},%a
  4841. cmp_i {post_inc_int, sp},%a
  4842. bxx[2] {llabel, $1}
  4843. #if WORD_SIZE==4
  4844. with exact post_inc4 post_inc4
  4845. gen cmp_l %1,%2
  4846. bxx[1] {llabel, $1}
  4847. #endif
  4848. with exact post_inc2 post_inc2
  4849. gen cmp_w %1,%2
  4850. bxx[1] {llabel, $1}
  4851. with exact post_inc1 post_inc1
  4852. gen cmp_b %1,%2
  4853. bxx[1] {llabel, $1}
  4854. pat blt call brxx("blt","bgt")
  4855. pat ble call brxx("ble","bge")
  4856. pat beq call brxx("beq","beq")
  4857. pat bne call brxx("bne","bne")
  4858. pat bge call brxx("bge","ble")
  4859. pat bgt call brxx("bgt","blt")
  4860. proc zxx example zeq
  4861. with test_set_int STACK
  4862. gen test %1
  4863. bxx[1] {llabel, $1}
  4864. #if WORD_SIZE==2
  4865. with test_set1 STACK
  4866. #else
  4867. with test_set1 + test_set2 STACK
  4868. #endif
  4869. gen test %1
  4870. bxx[2] {llabel, $1}
  4871. with exact STACK
  4872. gen tst_i {post_inc_int, sp}
  4873. bxx[1] {llabel, $1}
  4874. /* for some branches, we need to get rid of the overflow bit first.
  4875. The easiest way to do this is to just test ....
  4876. */
  4877. proc zxx_ouch example zeq
  4878. with test_set_int STACK
  4879. gen killcc.
  4880. test %1
  4881. bxx[1] {llabel, $1}
  4882. #if WORD_SIZE==2
  4883. with test_set1 STACK
  4884. #else
  4885. with test_set1 + test_set2 STACK
  4886. #endif
  4887. gen test %1
  4888. bxx[2] {llabel, $1}
  4889. with exact STACK
  4890. gen tst_i {post_inc_int, sp}
  4891. bxx[1] {llabel, $1}
  4892. pat zlt call zxx("bmi", "bcs")
  4893. pat zle call zxx_ouch("ble", "bls")
  4894. pat zeq call zxx("beq", "beq")
  4895. pat zne call zxx("bne", "bne")
  4896. pat zge call zxx("bpl", "bcc")
  4897. pat zgt call zxx_ouch("bgt", "bhi")
  4898. /************************************************
  4899. * Group 14: procedure calls instructions *
  4900. ************************************************/
  4901. pat cai
  4902. with exact ext_addr
  4903. kills ALL
  4904. gen jsr {absolute4, %1.bd}
  4905. with A_REG STACK
  4906. kills ALL
  4907. gen jsr {indirect4, %1}
  4908. with STACK
  4909. kills ALL
  4910. uses AA_REG = {post_inc4, sp}
  4911. gen jsr {indirect4, %a}
  4912. with address STACK
  4913. kills ALL
  4914. gen jsr %1
  4915. pat cal
  4916. with STACK
  4917. kills ALL
  4918. gen jsr {absolute4, $1}
  4919. #if WORD_SIZE==2
  4920. pat lfr $1==2 yields d0
  4921. pat lfr $1==4 yields dl0
  4922. pat lfr $1==8 yields dl1 dl0
  4923. #else
  4924. pat lfr $1==4 yields d0
  4925. pat lfr $1==8 yields d1 d0
  4926. #endif
  4927. pat ret $1==0
  4928. gen return
  4929. pat asp ret $2==0
  4930. gen return
  4931. #if WORD_SIZE==2
  4932. pat ret $1==2
  4933. with any2
  4934. gen move %1, d0
  4935. return
  4936. with exact STACK
  4937. gen move_w {post_inc2, sp}, d0
  4938. return
  4939. #endif
  4940. pat ret $1==4
  4941. with any4
  4942. gen move %1, dl0
  4943. return
  4944. with exact STACK
  4945. gen move_l {post_inc4, sp}, dl0
  4946. return
  4947. pat ret $1==8
  4948. with any4 any4
  4949. gen move %1, dl0
  4950. move %2, dl1
  4951. return
  4952. with exact any4 STACK
  4953. gen move %1, dl0
  4954. move_l {post_inc4, sp}, dl1
  4955. return
  4956. with exact STACK
  4957. gen move_l {post_inc4, sp}, dl0
  4958. move_l {post_inc4, sp}, dl1
  4959. return
  4960. /************************************************
  4961. * Group 15: miscellaneous instructions *
  4962. ************************************************/
  4963. #if WORD_SIZE==2
  4964. pat asp $1==2
  4965. with any2-pre_post
  4966. with STACK
  4967. gen add_l {const4, $1}, sp
  4968. #endif
  4969. pat asp $1==4
  4970. #if WORD_SIZE==2
  4971. with any-pre_post any-pre_post
  4972. #endif
  4973. with any4-pre_post
  4974. with STACK
  4975. gen add_l {const4, $1}, sp
  4976. #if WORD_SIZE==2
  4977. pat asp $1==6
  4978. with any4-pre_post any-pre_post
  4979. with any-pre_post any4-pre_post
  4980. with any-pre_post any-pre_post any-pre_post
  4981. with STACK
  4982. gen add_l {const4, $1}, sp
  4983. #endif
  4984. pat asp $1==8
  4985. with any4-pre_post any4-pre_post
  4986. with STACK
  4987. gen add_l {const4, $1}, sp
  4988. pat asp
  4989. with STACK
  4990. gen lea {regAcon, sp, $1}, sp
  4991. /* ??? DD_REG$ ??? */
  4992. #if WORD_SIZE==2
  4993. pat ass $1==2
  4994. with any2 STACK
  4995. uses reusing %1,DD_REG4
  4996. gen move %1,%a.1
  4997. ext_l %a.1
  4998. add_l %a, sp
  4999. #endif
  5000. pat ass $1==4
  5001. with any4 STACK
  5002. gen add_l %1, sp
  5003. #if WORD_SIZE==2
  5004. pat blm $1==2
  5005. with A_REG A_REG
  5006. kills allexceptcon
  5007. gen move_w {indirect2, %2}, {indirect2, %1}
  5008. #endif
  5009. pat blm $1==4
  5010. with A_REG A_REG
  5011. kills allexceptcon
  5012. gen move_l {indirect4, %2}, {indirect4, %1}
  5013. #if WORD_SIZE==2
  5014. pat blm $1==6
  5015. with A_REG A_REG
  5016. kills allexceptcon
  5017. gen move_l {indirect4, %2}, {indirect4, %1}
  5018. move_w {offsetted2, %2, 4}, {offsetted2, %1, 4}
  5019. #endif
  5020. pat blm $1==8
  5021. with A_REG A_REG
  5022. kills allexceptcon
  5023. gen move_l {indirect4, %2}, {indirect4, %1}
  5024. move_l {offsetted4, %2, 4}, {offsetted4, %1, 4}
  5025. pat blm $1>2*WORD_SIZE && $1/WORD_SIZE <= 65536
  5026. with AA_REG AA_REG
  5027. kills ALL
  5028. uses DD_REG4={const, $1/WORD_SIZE -1}
  5029. gen 1:
  5030. move_i {post_inc_int, %2}, {post_inc_int, %1}
  5031. dbf %a, {slabel, 1b}
  5032. pat blm
  5033. with AA_REG AA_REG
  5034. kills ALL
  5035. uses DD_REG4={const,$1/WORD_SIZE}
  5036. gen 1:
  5037. move_i {post_inc_int, %2}, {post_inc_int, %1}
  5038. sub_l {const4, 1}, %a
  5039. bne {slabel, 1b}
  5040. #if WORD_SIZE==2
  5041. pat bls $1==2
  5042. with DD_REG AA_REG AA_REG
  5043. kills ALL
  5044. gen asr_w {small_const, 1}, %1
  5045. beq {slabel, 2f}
  5046. 1:
  5047. move_w {post_inc2, %3}, {post_inc2, %2}
  5048. sub_w {const, 1}, %1
  5049. bne {slabel, 1b}
  5050. 2:
  5051. #endif
  5052. pat bls $1==4
  5053. with DD_REG4 AA_REG AA_REG
  5054. kills ALL
  5055. gen
  5056. #if WORD_SIZE==2
  5057. asr_l {small_const, 1}, %1
  5058. #else
  5059. asr_l {small_const, 2}, %1
  5060. #endif
  5061. beq {slabel, 2f}
  5062. 1:
  5063. move_i {post_inc_int, %3}, {post_inc_int, %2}
  5064. sub_l {const4, 1}, %1
  5065. bne {slabel, 1b}
  5066. 2:
  5067. #if WORD_SIZE==2
  5068. pat csa $1==2
  5069. #if TBL68020
  5070. with any4 D_REG+LOCAL+const+ILOCAL+absolute2 STACK
  5071. #else
  5072. with any4 D_REG+LOCAL+const+absolute2 STACK
  5073. #endif
  5074. gen move %1,a0
  5075. move %2,d0
  5076. jmp {absolute4, ".csa2"}
  5077. #endif
  5078. pat csa $1==4
  5079. #if TBL68020 && WORD_SIZE==4
  5080. with any4 D_REG4+DLOCAL+const4+ILOCAL+absolute4 STACK
  5081. #else
  5082. with any4 D_REG4+DLOCAL+const4+absolute4 STACK
  5083. #endif
  5084. gen move %1,a0
  5085. move %2,dl0
  5086. jmp {absolute4, ".csa4"}
  5087. #if WORD_SIZE==2
  5088. pat csb $1==2
  5089. #if TBL68020
  5090. with any4 D_REG+LOCAL+const+ILOCAL+absolute2 STACK
  5091. #else
  5092. with any4 D_REG+LOCAL+const+absolute2 STACK
  5093. #endif
  5094. gen move %1,a0
  5095. move %2,d0
  5096. jmp {absolute4, ".csb2"}
  5097. #endif
  5098. pat csb $1==4
  5099. #if TBL68020 && WORD_SIZE==4
  5100. with any4 D_REG4+DLOCAL+const4+ILOCAL+absolute4 STACK
  5101. #else
  5102. with any4 D_REG4+DLOCAL+const4+absolute4 STACK
  5103. #endif
  5104. gen move %1,a0
  5105. move %2,dl0
  5106. jmp {absolute4, ".csb4"}
  5107. pat dch leaving loi 4
  5108. #if WORD_SIZE==2
  5109. pat dup $1==2
  5110. with dups2 yields %1 %1
  5111. #endif
  5112. pat dup $1==4
  5113. #if WORD_SIZE==2
  5114. with dups2 dups2 yields %2 %1 %2 %1
  5115. #endif
  5116. with dups4 yields %1 %1
  5117. pat dup $1==8
  5118. with dups4 dups4 yields %2 %1 %2 %1
  5119. pat dup $1>2*WORD_SIZE && $1/WORD_SIZE<=65536
  5120. with STACK
  5121. uses DD_REG4 = {const, $1/WORD_SIZE -1}
  5122. gen 1:
  5123. move_i {offsetted_int, sp, $1 -WORD_SIZE}, {pre_dec_int, sp}
  5124. dbf %a, {slabel, 1b}
  5125. pat dup
  5126. with STACK
  5127. uses DD_REG4 = {const, $1/WORD_SIZE}
  5128. gen 1:
  5129. move_i {offsetted_int, sp, $1 -WORD_SIZE}, {pre_dec_int, sp}
  5130. sub_l {const4, 1}, %a
  5131. bne {slabel, 1b}
  5132. #if WORD_SIZE==2
  5133. pat dus $1==2
  5134. with any2 STACK
  5135. uses DD_REG4 = {zero_const4, 0}, AA_REG
  5136. gen
  5137. move_w %1, %a.1
  5138. lea {regAregXcon, sp, %a, 1, 0}, %b
  5139. asr_l {small_const, 1}, %a
  5140. beq {slabel, 2f}
  5141. 1:
  5142. move_w {pre_dec2, %b}, {pre_dec2, sp}
  5143. sub_l {const4, 1}, %a
  5144. bne {slabel, 1b}
  5145. 2:
  5146. #endif
  5147. pat dus $1==4
  5148. with DD_REG4 STACK
  5149. uses AA_REG
  5150. gen
  5151. lea {regAregXcon, sp, %1, 1, 0}, %a
  5152. #if WORD_SIZE==2
  5153. asr_l {small_const, 1}, %1
  5154. #else
  5155. asr_l {small_const, 2}, %1
  5156. #endif
  5157. beq {slabel, 2f}
  5158. 1:
  5159. move_i {pre_dec_int, %a}, {pre_dec_int, sp}
  5160. sub_l {const4, 1}, %1
  5161. bne {slabel, 1b}
  5162. 2:
  5163. #if WORD_SIZE==2
  5164. pat exg $1==2
  5165. with any2 any2 yields %1 %2
  5166. #endif
  5167. pat exg $1==4
  5168. with any4 any4 yields %1 %2
  5169. pat exg defined($1)
  5170. with STACK
  5171. kills ALL
  5172. gen move {const, $1}, d0
  5173. jsr {absolute4, ".exg"}
  5174. pat exg !defined($1)
  5175. with any_int STACK
  5176. kills ALL
  5177. gen move %1, d0
  5178. jsr {absolute4, ".exg"}
  5179. pat fil
  5180. gen move_l {ext_addr, $1}, {absolute4, ".filn"}
  5181. pat gto
  5182. with STACK
  5183. uses AA_REG = {ext_addr, $1}
  5184. gen move_l {offsetted4, %a, 8}, lb
  5185. move_l {offsetted4, %a, 4}, sp
  5186. #if TBL68020 && FANCY_MODES
  5187. jmp {OFF_off4, %a, 0, 0}
  5188. #else
  5189. move_l {indirect4, %a}, %a
  5190. jmp {indirect4, %a}
  5191. #endif
  5192. pat lim yields {absolute_int, ".trpim"}
  5193. pat lin
  5194. kills posextern
  5195. gen move_i {const, $1}, {absolute_int, ".lino"}
  5196. pat lni
  5197. kills posextern
  5198. gen add_i {const, 1}, {absolute_int, ".lino"}
  5199. pat lor $1==0 yields lb
  5200. pat lor $1==1
  5201. with STACK
  5202. uses AA_REG = sp yields %a
  5203. pat lor $1==2 yields {absolute4, ".reghp"}
  5204. pat lpb leaving adp 8
  5205. pat mon
  5206. with STACK
  5207. kills ALL
  5208. gen jsr {absolute4, ".mon"}
  5209. pat nop
  5210. with STACK
  5211. kills ALL
  5212. #ifdef DEBUG
  5213. gen jsr {absolute4, ".nop"}
  5214. #endif
  5215. #if WORD_SIZE==2
  5216. pat rck $1==2
  5217. #ifdef TBL68020
  5218. with ext_addr D_REG
  5219. gen cmp2_w {absolute2, %1.bd}, %2
  5220. bcc {slabel, 1f}
  5221. move_w {small_const, 1}, {pre_dec2, sp} /* push constant 1 == ERANGE */
  5222. jsr {absolute4, ".trp"}
  5223. 1: yields %2
  5224. with address-ext_addr D_REG
  5225. gen cmp2_w %1, %2
  5226. bcc {slabel, 1f}
  5227. move_w {small_const, 1}, {pre_dec2, sp} /* push constant 1 == ERANGE */
  5228. jsr {absolute4, ".trp"}
  5229. 1: yields %2
  5230. with A_REG D_REG
  5231. gen cmp2_w {indirect2, %1}, %2
  5232. bcc {slabel, 1f}
  5233. move_w {small_const, 1}, {pre_dec2, sp} /* push constant 1 == ERANGE */
  5234. jsr {absolute4, ".trp"}
  5235. 1: yields %2
  5236. #else
  5237. with STACK
  5238. kills ALL
  5239. gen jsr {absolute4, ".rck"}
  5240. #endif
  5241. #endif /* WORD_SIZE==2 */
  5242. #if WORD_SIZE==4 || TBL68020
  5243. pat rck $1==4
  5244. #ifdef TBL68020
  5245. with ext_addr D_REG4
  5246. gen cmp2_l {absolute4, %1.bd}, %2
  5247. bcc {slabel, 1f}
  5248. pea {absolute4, 1} /* push constant 1 == ERANGE */
  5249. jsr {absolute4, ".trp"}
  5250. 1: yields %2
  5251. with address-ext_addr D_REG4
  5252. gen cmp2_l %1, %2
  5253. bcc {slabel, 1f}
  5254. pea {absolute4, 1} /* push constant 1 == ERANGE */
  5255. jsr {absolute4, ".trp"}
  5256. 1: yields %2
  5257. with A_REG D_REG4
  5258. gen cmp2_l {indirect4, %1}, %2
  5259. bcc {slabel, 1f}
  5260. pea {absolute4, 1} /* push constant 1 == ERANGE */
  5261. jsr {absolute4, ".trp"}
  5262. 1: yields %2
  5263. #else /* TBL68020 */
  5264. with STACK
  5265. kills ALL
  5266. gen jsr {absolute4, ".rck"}
  5267. #endif /* TBL68020 */
  5268. #endif /* WORD_SIZE==4 || TBL68020 */
  5269. pat rtt leaving ret 0
  5270. pat sig
  5271. with any4
  5272. kills posextern
  5273. uses AA_REG
  5274. gen move_l {absolute4, ".trppc"}, %a
  5275. move_l %1, {absolute4, ".trppc"}
  5276. yields %a
  5277. pat sim
  5278. with any_int
  5279. kills posextern
  5280. gen move_i %1, {absolute_int, ".trpim"}
  5281. pat str $1==0
  5282. with any4 STACK
  5283. kills ALL
  5284. gen move_l %1, lb
  5285. pat str $1==1
  5286. with any4 STACK
  5287. gen move_l %1, sp
  5288. pat str $1==2
  5289. with STACK
  5290. kills ALL
  5291. gen jsr {absolute4, ".strhp"}
  5292. pat trp
  5293. with STACK
  5294. kills ALL
  5295. gen jsr {absolute4, ".trp"}
  5296. /************************************************
  5297. * more rules for long EM-patterns *
  5298. ************************************************/
  5299. pat loe ine $1==$2
  5300. kills posextern
  5301. uses DD_REG = {absolute_int, $1}
  5302. gen add_i {const,1}, {absolute_int, $1}
  5303. killreg %a
  5304. yields %a
  5305. pat loe dee $1==$2
  5306. kills posextern
  5307. uses DD_REG = {absolute_int, $1}
  5308. gen sub_i {const,1}, {absolute_int, $1}
  5309. killreg %a
  5310. yields %a
  5311. proc llol1shstl example lol loc sli stl /* only left */
  5312. kills all_indir, DLOCAL %bd==$1
  5313. gen shw* {offsetted2, lb, $1+2}
  5314. roxl {offsetted2, lb, $1}
  5315. proc lloe1shste example loe loc sli ste /* only left */
  5316. kills posextern
  5317. gen shw* {absolute2, $1+2}
  5318. roxl {absolute2, $1}
  5319. proc llil1shsil example lil loc sli sil /* only left */
  5320. kills allexceptcon
  5321. #if TBL68020 && FANCY_MODES
  5322. gen shw* {OFF_off2, lb, $1, 2}
  5323. roxl {OFF_off2, lb, $1, 0}
  5324. #else
  5325. uses AA_REG = {DLOCAL, $1}
  5326. gen shw* {offsetted2, %a, 2}
  5327. roxl {indirect2, %a}
  5328. #endif
  5329. proc rlol1shstl example lol loc sri stl /* only right */
  5330. kills all_indir, DLOCAL %bd==$1
  5331. gen shw* {offsetted2, lb, $1}
  5332. roxr {offsetted2, lb, $1+2}
  5333. proc rloe1shste example loe loc sri ste /* only right */
  5334. kills posextern
  5335. gen shw* {absolute2, $1}
  5336. roxr {absolute2, $1+2}
  5337. proc rlil1shsil example lil loc sri sil /* only right */
  5338. kills allexceptcon
  5339. #if TBL68020 && FANCY_MODES
  5340. gen shw* {OFF_off2, lb, $1, 0}
  5341. roxr {OFF_off2, lb, $1, 2}
  5342. #else
  5343. uses AA_REG = {DLOCAL, $1}
  5344. gen shw* {indirect2, %a}
  5345. roxr {offsetted2, %a, 2}
  5346. #endif
  5347. pat lol loc sli stl $1==$4 && $2==1 && $3==4 call llol1shstl("asl #1,")
  5348. pat loe loc sli ste $1==$4 && $2==1 && $3==4 call lloe1shste("asl #1,")
  5349. pat lil loc sli sil $1==$4 && $2==1 && $3==4 call llil1shsil("asl #1,")
  5350. pat lol loc sri stl $1==$4 && $2==1 && $3==4 call rlol1shstl("asr #1,")
  5351. pat loe loc sri ste $1==$4 && $2==1 && $3==4 call rloe1shste("asr #1,")
  5352. pat lil loc sri sil $1==$4 && $2==1 && $3==4 call rlil1shsil("asr #1,")
  5353. pat lol loc slu stl $1==$4 && $2==1 && $3==4 call llol1shstl("asl #1,")
  5354. pat loe loc slu ste $1==$4 && $2==1 && $3==4 call lloe1shste("asl #1,")
  5355. pat lil loc slu sil $1==$4 && $2==1 && $3==4 call llil1shsil("asl #1,")
  5356. pat lol loc sru stl $1==$4 && $2==1 && $3==4 call rlol1shstl("lsr #1,")
  5357. pat loe loc sru ste $1==$4 && $2==1 && $3==4 call rloe1shste("lsr #1,")
  5358. pat lil loc sru sil $1==$4 && $2==1 && $3==4 call rlil1shsil("lsr #1,")
  5359. proc txxand
  5360. with test_set_int DD_REG
  5361. gen test %1
  5362. bxx[1] {slabel, 1f}
  5363. bclr {const,0}, %2
  5364. 1: yields %2
  5365. #if WORD_SIZE==2
  5366. with test_set1 DD_REG
  5367. #else
  5368. with test_set1 + test_set2 DD_REG
  5369. #endif
  5370. gen test %1
  5371. bxx[2] {slabel, 1f}
  5372. bclr {const,0}, %2
  5373. 1: yields %2
  5374. proc txxior
  5375. with test_set_int DD_REG
  5376. gen test %1
  5377. bxx[1] {slabel, 1f}
  5378. bset {zero_const, 0}, %2
  5379. 1: yields %2
  5380. #if WORD_SIZE==2
  5381. with test_set1 DD_REG
  5382. #else
  5383. with test_set1 + test_set2 DD_REG
  5384. #endif
  5385. gen test %1
  5386. bxx[2] {slabel, 1f}
  5387. bset {zero_const, 0}, %2
  5388. 1: yields %2
  5389. proc txxand_ouch
  5390. with test_set_int DD_REG
  5391. gen killcc.
  5392. test %1
  5393. bxx[1] {slabel, 1f}
  5394. bclr {const,0}, %2
  5395. 1: yields %2
  5396. #if WORD_SIZE==2
  5397. with test_set1 DD_REG
  5398. #else
  5399. with test_set1 + test_set2 DD_REG
  5400. #endif
  5401. gen test %1
  5402. bxx[2] {slabel, 1f}
  5403. bclr {const,0}, %2
  5404. 1: yields %2
  5405. proc txxior_ouch
  5406. with test_set_int DD_REG
  5407. gen killcc.
  5408. test %1
  5409. bxx[1] {slabel, 1f}
  5410. bset {zero_const, 0}, %2
  5411. 1: yields %2
  5412. #if WORD_SIZE==2
  5413. with test_set1 DD_REG
  5414. #else
  5415. with test_set1 + test_set2 DD_REG
  5416. #endif
  5417. gen test %1
  5418. bxx[2] {slabel, 1f}
  5419. bset {zero_const, 0}, %2
  5420. 1: yields %2
  5421. pat tlt and $2==WORD_SIZE call txxand("bmi", "bcs")
  5422. pat tle and $2==WORD_SIZE call txxand_ouch("ble", "bls")
  5423. pat teq and $2==WORD_SIZE call txxand("beq", "beq")
  5424. pat tne and $2==WORD_SIZE call txxand("bne", "bne")
  5425. pat tge and $2==WORD_SIZE call txxand("bpl", "bcc")
  5426. pat tgt and $2==WORD_SIZE call txxand_ouch("bgt", "bhi")
  5427. pat tlt ior $2==WORD_SIZE call txxior("bpl", "bcc")
  5428. pat tle ior $2==WORD_SIZE call txxior_ouch("bgt", "bhi")
  5429. pat teq ior $2==WORD_SIZE call txxior("bne", "bne")
  5430. pat tne ior $2==WORD_SIZE call txxior("beq", "beq")
  5431. pat tge ior $2==WORD_SIZE call txxior("bmi", "bcs")
  5432. pat tgt ior $2==WORD_SIZE call txxior_ouch("ble", "bls")
  5433. proc cmxtxxand
  5434. with exact extend1 extend1 DD_REG
  5435. gen cmp_b %2, %1
  5436. bxx[2] {llabel,1f}
  5437. bclr {const,0}, %3
  5438. 1: yields %3
  5439. with exact extend2 extend2 DD_REG
  5440. gen cmp_w %2, %1
  5441. bxx[2] {llabel,1f}
  5442. bclr {const,0}, %3
  5443. 1: yields %3
  5444. with exact sconsts any_int DD_REG
  5445. uses DD_REG=%1
  5446. gen cmp_i %2, %a
  5447. bxx[2] {slabel, 1f}
  5448. bclr {const,0}, %3
  5449. 1: yields %3
  5450. with exact any_int sconsts DD_REG
  5451. uses DD_REG=%2
  5452. gen cmp_i %1, %a
  5453. bxx[1] {slabel, 1f}
  5454. bclr {const,0}, %3
  5455. 1: yields %3
  5456. with any_int-sconsts genreg DD_REG
  5457. gen cmp_i %1, %2
  5458. bxx[1] {slabel, 1f}
  5459. bclr {const,0}, %3
  5460. 1: yields %3
  5461. with genreg any_int-sconsts DD_REG
  5462. gen cmp_i %2, %1
  5463. bxx[2] {slabel, 1f}
  5464. bclr {const,0}, %3
  5465. 1: yields %3
  5466. with exact immediate_int-sconsts imm_cmp_int DD_REG
  5467. gen cmp_i %1, %2
  5468. bxx[1] {slabel, 1f}
  5469. bclr {const,0}, %3
  5470. 1: yields %3
  5471. with exact imm_cmp_int immediate_int-sconsts DD_REG
  5472. gen cmp_i %2, %1
  5473. bxx[2] {slabel, 1f}
  5474. bclr {const,0}, %3
  5475. 1: yields %3
  5476. proc cmxtxxior
  5477. with exact extend1 extend1 DD_REG
  5478. gen cmp_b %2, %1
  5479. bxx[2] {llabel,1f}
  5480. bset {zero_const, 0}, %3
  5481. 1: yields %3
  5482. with exact extend2 extend2 DD_REG
  5483. gen cmp_w %2, %1
  5484. bxx[2] {llabel,1f}
  5485. bset {zero_const, 0}, %3
  5486. 1: yields %3
  5487. with exact sconsts any_int DD_REG
  5488. uses DD_REG=%1
  5489. gen cmp_i %2, %a
  5490. bxx[2] {slabel, 1f}
  5491. bset {zero_const, 0}, %3
  5492. 1: yields %3
  5493. with exact any_int sconsts DD_REG
  5494. uses DD_REG=%2
  5495. gen cmp_i %1, %a
  5496. bxx[1] {slabel, 1f}
  5497. bset {zero_const, 0}, %3
  5498. 1: yields %3
  5499. with any_int-sconsts genreg DD_REG
  5500. gen cmp_i %1, %2
  5501. bxx[1] {slabel, 1f}
  5502. bset {zero_const, 0}, %3
  5503. 1: yields %3
  5504. with genreg any_int-sconsts DD_REG
  5505. gen cmp_i %2, %1
  5506. bxx[2] {slabel, 1f}
  5507. bset {zero_const, 0}, %3
  5508. 1: yields %3
  5509. with exact immediate_int-sconsts imm_cmp_int DD_REG
  5510. gen cmp_i %1, %2
  5511. bxx[1] {slabel, 1f}
  5512. bset {zero_const, 0}, %3
  5513. 1: yields %3
  5514. with exact imm_cmp_int immediate_int-sconsts DD_REG
  5515. gen cmp_i %2, %1
  5516. bxx[2] {slabel, 1f}
  5517. bset {zero_const, 0}, %3
  5518. 1: yields %3
  5519. proc cmxtxx
  5520. with exact sconsts any_int
  5521. uses DD_REG=%1
  5522. gen cmp_i %2, %a
  5523. sxx[2] %a
  5524. neg_b %a
  5525. yields {extend1, %a}
  5526. with exact any_int sconsts
  5527. uses DD_REG=%2
  5528. gen cmp_i %1, %a
  5529. sxx[1] %a
  5530. neg_b %a
  5531. yields {extend1, %a}
  5532. with any_int-sconsts genreg
  5533. uses reusing %1,reusing %2,DD_REG
  5534. gen cmp_i %1, %2
  5535. sxx[1] %a
  5536. neg_b %a
  5537. yields {extend1, %a}
  5538. with genreg any_int-sconsts
  5539. uses reusing %1,reusing %2,DD_REG
  5540. gen cmp_i %2, %1
  5541. sxx[2] %a
  5542. neg_b %a
  5543. yields {extend1, %a}
  5544. with exact extend1 extend1
  5545. uses reusing %1,reusing %2,DD_REG
  5546. gen cmp_b %2, %1
  5547. sxx[2] %a
  5548. neg_b %a
  5549. yields {extend1, %a}
  5550. with exact extend2 extend2
  5551. uses reusing %1,reusing %2,DD_REG
  5552. gen cmp_w %2, %1
  5553. sxx[2] %a
  5554. neg_b %a
  5555. yields {extend1, %a}
  5556. with exact immediate_int-sconsts imm_cmp_int
  5557. uses reusing %2,DD_REG
  5558. gen cmp_i %1, %2
  5559. sxx[1] %a
  5560. neg_b %a
  5561. yields {extend1, %a}
  5562. with exact imm_cmp_int immediate_int-sconsts
  5563. uses reusing %1,DD_REG
  5564. gen cmp_i %2, %1
  5565. sxx[2] %a
  5566. neg_b %a
  5567. yields {extend1, %a}
  5568. with exact immediate_int-sconsts STACK
  5569. uses DD_REG
  5570. gen cmp_i %1, {post_inc_int, sp}
  5571. sxx[1] %a
  5572. neg_b %a
  5573. yields {extend1, %a}
  5574. with exact any_int STACK
  5575. uses reusing %1,DD_REG=%1
  5576. gen cmp_i {post_inc_int, sp}, %a
  5577. sxx[2] %a
  5578. neg_b %a
  5579. yields {extend1, %a}
  5580. with exact STACK
  5581. uses DD_REG
  5582. gen move_i {post_inc_int, sp},%a
  5583. cmp_i {post_inc_int, sp},%a
  5584. sxx[2] %a
  5585. neg_b %a
  5586. yields {extend1, %a}
  5587. pat cmi tlt and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("blt","bgt")
  5588. pat cmi tle and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("ble","bge")
  5589. pat cmi teq and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("beq","beq")
  5590. pat cmi tne and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bne","bne")
  5591. pat cmi tge and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bge","ble")
  5592. pat cmi tgt and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bgt","blt")
  5593. pat cmu tlt and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bcs","bhi")
  5594. pat cmu tle and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bls","bcc")
  5595. pat cmu teq and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("beq","beq")
  5596. pat cmu tne and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bne","bne")
  5597. pat cmu tge and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bcc","bls")
  5598. pat cmu tgt and $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxand("bhi","bcs")
  5599. pat cmi tlt ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bge","ble")
  5600. pat cmi tle ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bgt","blt")
  5601. pat cmi teq ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bne","bne")
  5602. pat cmi tne ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("beq","beq")
  5603. pat cmi tge ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("blt","bgt")
  5604. pat cmi tgt ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("ble","bge")
  5605. pat cmu tlt ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bcc","bls")
  5606. pat cmu tle ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bhi","bcs")
  5607. pat cmu teq ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bne","bne")
  5608. pat cmu tne ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("beq","beq")
  5609. pat cmu tge ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bcs","bhi")
  5610. pat cmu tgt ior $1==WORD_SIZE && $3==WORD_SIZE call cmxtxxior("bls","bcc")
  5611. pat cmi tlt $1==WORD_SIZE call cmxtxx("slt","sgt")
  5612. pat cmi tle $1==WORD_SIZE call cmxtxx("sle","sge")
  5613. pat cmi teq $1==WORD_SIZE call cmxtxx("seq","seq")
  5614. pat cmi tne $1==WORD_SIZE call cmxtxx("sne","sne")
  5615. pat cmi tge $1==WORD_SIZE call cmxtxx("sge","sle")
  5616. pat cmi tgt $1==WORD_SIZE call cmxtxx("sgt","slt")
  5617. pat cmu tlt $1==WORD_SIZE call cmxtxx("scs","shi")
  5618. pat cmu tle $1==WORD_SIZE call cmxtxx("sls","scc")
  5619. pat cmu teq $1==WORD_SIZE call cmxtxx("seq","seq")
  5620. pat cmu tne $1==WORD_SIZE call cmxtxx("sne","sne")
  5621. pat cmu tge $1==WORD_SIZE call cmxtxx("scc","sls")
  5622. pat cmu tgt $1==WORD_SIZE call cmxtxx("shi","scs")
  5623. proc cmuzxx example cmu zlt
  5624. with exact sconsts any_int
  5625. kills ALL
  5626. uses DD_REG=%1
  5627. gen cmp_i %2, %a
  5628. bxx[2] {llabel, $2}
  5629. with exact any_int sconsts
  5630. kills ALL
  5631. uses DD_REG=%2
  5632. gen cmp_i %1, %a
  5633. bxx[1] {llabel, $2}
  5634. with any_int-sconsts genreg STACK
  5635. gen cmp_i %1, %2
  5636. bxx[1] {llabel, $2}
  5637. with genreg any_int-sconsts STACK
  5638. gen cmp_i %2, %1
  5639. bxx[2] {llabel, $2}
  5640. with exact immediate_int-sconsts imm_cmp_int
  5641. kills ALL
  5642. gen cmp_i %1, %2
  5643. bxx[1] {llabel, $2}
  5644. with exact imm_cmp_int immediate_int-sconsts
  5645. kills ALL
  5646. gen cmp_i %2, %1
  5647. bxx[2] {llabel, $2}
  5648. with exact immediate_int-sconsts STACK
  5649. gen cmp_i %1, {post_inc_int, sp}
  5650. bxx[1] {llabel, $2}
  5651. with exact any_int STACK
  5652. uses reusing %1, DD_REG=%1
  5653. gen cmp_i {post_inc_int, sp}, %a
  5654. bxx[2] {llabel, $2}
  5655. with exact STACK
  5656. uses DD_REG
  5657. gen move_i {post_inc_int, sp},%a
  5658. cmp_i {post_inc_int, sp},%a
  5659. bxx[2] {llabel, $2}
  5660. with data2-sconsts dreg2 STACK
  5661. gen cmp_w %1, %2
  5662. bxx[1] {llabel, $2}
  5663. with dreg2 data2-conreg2-sconsts STACK
  5664. gen cmp_w %2, %1
  5665. bxx[2] {llabel, $2}
  5666. with data1 dreg1 STACK
  5667. gen cmp_b %1, %2
  5668. bxx[1] {llabel, $2}
  5669. with dreg1 data1-conreg1 STACK
  5670. gen cmp_b %2, %1
  5671. bxx[2] {llabel, $2}
  5672. pat cmu zlt $1==WORD_SIZE call cmuzxx("bcs","bhi")
  5673. pat cmu zle $1==WORD_SIZE call cmuzxx("bls","bcc")
  5674. pat cmu zeq $1==WORD_SIZE call cmuzxx("beq","beq")
  5675. pat cmu zne $1==WORD_SIZE call cmuzxx("bne","bne")
  5676. pat cmu zge $1==WORD_SIZE call cmuzxx("bcc","bls")
  5677. pat cmu zgt $1==WORD_SIZE call cmuzxx("bhi","bcs")
  5678. #if TBL68881
  5679. proc cmf4zxx example cmf zlt
  5680. with FS_REG FS_REG
  5681. gen fcmp %1,%2
  5682. bxx* {llabel, $2}
  5683. pat cmf zlt $1==4 call cmf4zxx("fblt")
  5684. pat cmf zle $1==4 call cmf4zxx("fble")
  5685. pat cmf zne $1==4 call cmf4zxx("fbne")
  5686. pat cmf zeq $1==4 call cmf4zxx("fbeq")
  5687. pat cmf zge $1==4 call cmf4zxx("fbge")
  5688. pat cmf zgt $1==4 call cmf4zxx("fbgt")
  5689. proc cmf8zxx example cmf zlt
  5690. with FD_REG FD_REG
  5691. gen fcmp %1,%2
  5692. bxx* {llabel, $2}
  5693. pat cmf zlt $1==8 call cmf8zxx("fblt")
  5694. pat cmf zle $1==8 call cmf8zxx("fble")
  5695. pat cmf zne $1==8 call cmf8zxx("fbne")
  5696. pat cmf zeq $1==8 call cmf8zxx("fbeq")
  5697. pat cmf zge $1==8 call cmf8zxx("fbge")
  5698. pat cmf zgt $1==8 call cmf8zxx("fbgt")
  5699. #endif
  5700. proc loc1locciibxx example loc loc cii bne
  5701. with any1 extend1 STACK
  5702. gen cmp_b %1,%2
  5703. bxx[1] {llabel, $4}
  5704. with any1 any_int STACK
  5705. uses reusing %1, DD_REG = %1
  5706. #if TBL68020 && WORD_SIZE==4
  5707. gen extb_l %a
  5708. #else
  5709. gen ext_w %a
  5710. #if WORD_SIZE==4
  5711. ext_l %a
  5712. #endif
  5713. #endif
  5714. cmp_i %2,%a
  5715. bxx[2] {llabel, $4}
  5716. pat loc loc cii blt $1==1 && $2==EM_WSIZE call loc1locciibxx("blt","bgt")
  5717. pat loc loc cii ble $1==1 && $2==EM_WSIZE call loc1locciibxx("ble","bge")
  5718. pat loc loc cii bne $1==1 && $2==EM_WSIZE call loc1locciibxx("bne","bne")
  5719. pat loc loc cii beq $1==1 && $2==EM_WSIZE call loc1locciibxx("beq","beq")
  5720. pat loc loc cii bge $1==1 && $2==EM_WSIZE call loc1locciibxx("bge","ble")
  5721. pat loc loc cii bgt $1==1 && $2==EM_WSIZE call loc1locciibxx("bgt","blt")
  5722. #if WORD_SIZE==4
  5723. proc loc2locciibxx example loc loc cii bne
  5724. with any2 extend2 STACK
  5725. gen cmp_w %1,%2
  5726. bxx[1] {llabel, $4}
  5727. with any2 any4 STACK
  5728. uses reusing %1, DD_REG = %1
  5729. gen ext_l %a
  5730. cmp_l %2,%a
  5731. bxx[2] {llabel, $4}
  5732. pat loc loc cii blt $1==2 && $2==EM_WSIZE call loc2locciibxx("blt","bgt")
  5733. pat loc loc cii blt $1==2 && $2==EM_WSIZE call loc2locciibxx("blt","bgt")
  5734. pat loc loc cii ble $1==2 && $2==EM_WSIZE call loc2locciibxx("ble","bge")
  5735. pat loc loc cii bne $1==2 && $2==EM_WSIZE call loc2locciibxx("bne","bne")
  5736. pat loc loc cii beq $1==2 && $2==EM_WSIZE call loc2locciibxx("beq","beq")
  5737. pat loc loc cii bge $1==2 && $2==EM_WSIZE call loc2locciibxx("bge","ble")
  5738. pat loc loc cii bgt $1==2 && $2==EM_WSIZE call loc2locciibxx("bgt","blt")
  5739. #endif
  5740. proc bxx1_in example loc loc cii loc bne
  5741. with imm_cmp1 STACK
  5742. gen cmp_b {const, low8($4)}, %1
  5743. bxx* {llabel, $5}
  5744. #if WORD_SIZE!=2
  5745. proc bxx2_in example loc loc cii loc bne
  5746. with imm_cmp2 STACK
  5747. gen cmp_w {const, loww($4)}, %1
  5748. bxx* {llabel, $5}
  5749. #endif
  5750. proc bxx1_small example loc bne
  5751. with imm_cmp1-D_REG STACK
  5752. gen cmp_b {const, $1}, %1
  5753. bxx[1] {llabel, $2}
  5754. with imm_cmp2-D_REG STACK
  5755. gen cmp_w {const, $1}, %1
  5756. bxx[1] {llabel, $2}
  5757. with data_int STACK
  5758. uses DD_REG = {small_const, $1} /* uses moveq */
  5759. gen cmp_i %1,%a
  5760. bxx[2] {llabel, $2}
  5761. #if WORD_SIZE!=2
  5762. proc bxx2_small example loc bne
  5763. with imm_cmp2-D_REG STACK
  5764. gen cmp_w {const, $1}, %1
  5765. bxx[1] {llabel, $2}
  5766. with imm_cmp4 STACK
  5767. gen cmp_l {const, $1}, %1
  5768. bxx[2] {llabel, $2}
  5769. #endif
  5770. proc zxx1_in example loc loc cii zne
  5771. with test_set1 STACK
  5772. gen test %1
  5773. bxx* {llabel, $4}
  5774. with D_REG STACK
  5775. gen test {dreg1, %1}
  5776. bxx* {llabel, $4}
  5777. #if WORD_SIZE!=2
  5778. proc zxx2_in example loc loc cii zne
  5779. with test_set2 STACK
  5780. gen test %1
  5781. bxx* {llabel, $4}
  5782. with D_REG STACK
  5783. gen test {dreg2, %1}
  5784. bxx* {llabel, $4}
  5785. #endif
  5786. pat loc loc cii zlt $1==1 && $2==WORD_SIZE call zxx1_in("blt")
  5787. pat loc loc cii zle $1==1 && $2==WORD_SIZE call zxx1_in("ble")
  5788. pat loc loc cii zne $1==1 && $2==WORD_SIZE call zxx1_in("bne")
  5789. pat loc loc cii zeq $1==1 && $2==WORD_SIZE call zxx1_in("beq")
  5790. pat loc loc cii zge $1==1 && $2==WORD_SIZE call zxx1_in("bge")
  5791. pat loc loc cii zgt $1==1 && $2==WORD_SIZE call zxx1_in("bgt")
  5792. #if WORD_SIZE!=2
  5793. pat loc loc cii zlt $1==2 && $2==4 call zxx2_in("blt")
  5794. pat loc loc cii zle $1==2 && $2==4 call zxx2_in("ble")
  5795. pat loc loc cii zne $1==2 && $2==4 call zxx2_in("bne")
  5796. pat loc loc cii zeq $1==2 && $2==4 call zxx2_in("beq")
  5797. pat loc loc cii zge $1==2 && $2==4 call zxx2_in("bge")
  5798. pat loc loc cii zgt $1==2 && $2==4 call zxx2_in("bgt")
  5799. #endif
  5800. pat loc loc cii loc blt $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("blt")
  5801. pat loc loc cii loc ble $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("ble")
  5802. pat loc loc cii loc beq $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("beq")
  5803. pat loc loc cii loc bne $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("bne")
  5804. pat loc loc cii loc bge $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("bge")
  5805. pat loc loc cii loc bgt $1==1 && $2==WORD_SIZE && in_1($4) call bxx1_in("bgt")
  5806. #if WORD_SIZE!=2
  5807. pat loc loc cii loc blt $1==2 && $2==4 && in_2($4) call bxx2_in("blt")
  5808. pat loc loc cii loc ble $1==2 && $2==4 && in_2($4) call bxx2_in("ble")
  5809. pat loc loc cii loc beq $1==2 && $2==4 && in_2($4) call bxx2_in("beq")
  5810. pat loc loc cii loc bne $1==2 && $2==4 && in_2($4) call bxx2_in("bne")
  5811. pat loc loc cii loc bge $1==2 && $2==4 && in_2($4) call bxx2_in("bge")
  5812. pat loc loc cii loc bgt $1==2 && $2==4 && in_2($4) call bxx2_in("bgt")
  5813. #endif
  5814. /* the second instruction for bxx1_small is the other way around! */
  5815. pat loc blt $1>=0 && $1<128 call bxx1_small("bcs", "bgt")
  5816. pat loc ble $1>=0 && $1<128 call bxx1_small("bls", "bge")
  5817. pat loc beq $1>=0 && $1<128 call bxx1_small("beq", "beq")
  5818. pat loc bne $1>=0 && $1<128 call bxx1_small("bne", "bne")
  5819. pat loc bge $1>=0 && $1<128 call bxx1_small("bcc", "ble")
  5820. pat loc bgt $1>=0 && $1<128 call bxx1_small("bhi", "blt")
  5821. #if WORD_SIZE!=2
  5822. pat loc blt $1>=128 && $1<32768 call bxx2_small("bcs", "blt")
  5823. pat loc ble $1>=128 && $1<32768 call bxx2_small("bls", "ble")
  5824. pat loc beq $1>=128 && $1<32768 call bxx2_small("beq", "beq")
  5825. pat loc bne $1>=128 && $1<32768 call bxx2_small("bne", "bne")
  5826. pat loc bge $1>=128 && $1<32768 call bxx2_small("bcc", "bge")
  5827. pat loc bgt $1>=128 && $1<32768 call bxx2_small("bhi", "bgt")
  5828. #endif
  5829. pat loc loc cii lal sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
  5830. leaving lal $4 sti $5
  5831. pat loc loc cii lol sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
  5832. leaving lol $4 sti $5
  5833. pat loc loc cii lil sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
  5834. leaving lil $4 sti $5
  5835. pat loc loc cii LLP lof sti $1 <= WORD_SIZE && $1>=$6 && $2==WORD_SIZE
  5836. leaving LLP $4 lof $5 sti $6
  5837. pat loc loc cii lae sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
  5838. leaving lae $4 sti $5
  5839. pat loc loc cii loe sti $1 <= WORD_SIZE && $1>=$5 && $2==WORD_SIZE
  5840. leaving loe $4 sti $5
  5841. pat loc loc cii stl $1==1 && $2==WORD_SIZE && inreg($4)==reg_any
  5842. with memory1+DD_REG
  5843. kills regvar($4, reg_any), use_index %xreg==regvar($4, reg_any)
  5844. gen move_b %1, {dreg1, regvar($4,reg_any)}
  5845. #if WORD_SIZE==2
  5846. ext_w {LOCAL,$4}
  5847. #else
  5848. #ifdef TBL68020
  5849. extb_l {LOCAL,$4}
  5850. #else /* TBL68020 */
  5851. ext_w {LOCAL,$4}
  5852. ext_l {LOCAL,$4}
  5853. #endif /* TBL68020 */
  5854. #endif
  5855. pat loc loc cii $1==2 && $2==4
  5856. #if WORD_SIZE==2
  5857. with D_REG
  5858. uses reusing %1, DD_REG4
  5859. gen move %1,%a.1 yields {extend2, %a}
  5860. with exact extend1
  5861. uses reusing %1,DD_REG4
  5862. gen move %1.reg,%a.1 yields {extend1_4, %a}
  5863. with exact memory2
  5864. uses reusing %1,DD_REG4
  5865. gen move %1, %a.1 yields {extend2, %a}
  5866. #else
  5867. with DD_REG yields {extend2, %1}
  5868. with exact memory2
  5869. uses reusing %1,DD_REG=%1
  5870. yields {extend2, %a}
  5871. #endif
  5872. pat loc loc cii $1==1 && $2==WORD_SIZE
  5873. with DD_REG yields {extend1, %1}
  5874. with exact memory1
  5875. uses reusing %1,DD_REG = %1
  5876. yields {extend1, %a}
  5877. #if WORD_SIZE==2
  5878. pat loc loc cii $1==1 && $2==4
  5879. with DD_REG
  5880. uses reusing %1, DD_REG4
  5881. gen move %1, %a.1
  5882. yields {extend1_4, %a}
  5883. with exact memory1
  5884. uses reusing %1,DD_REG4
  5885. gen move %1,%a.1 yields {extend1_4, %a}
  5886. #endif
  5887. pat loc loc ciu $1==$2 /* skip this */
  5888. pat loc loc cui $1==$2 /* skip this */
  5889. /* The following rules should be handled by the peephole optimizer, I think */
  5890. #if WORD_SIZE==2
  5891. pat ldc dvu highw($1)==0 && loww($1)==2 && $2==4 leaving loc 1 sru 4
  5892. pat ldc dvu highw($1)==0 && loww($1)==4 && $2==4 leaving loc 2 sru 4
  5893. pat ldc dvu highw($1)==0 && loww($1)==8 && $2==4 leaving loc 3 sru 4
  5894. pat ldc dvu highw($1)==0 && loww($1)==16 && $2==4 leaving loc 4 sru 4
  5895. pat ldc dvu highw($1)==0 && loww($1)==32 && $2==4 leaving loc 5 sru 4
  5896. pat ldc dvu highw($1)==0 && loww($1)==64 && $2==4 leaving loc 6 sru 4
  5897. pat ldc dvu highw($1)==0 && loww($1)==128 && $2==4 leaving loc 7 sru 4
  5898. pat ldc dvu highw($1)==0 && loww($1)==256 && $2==4 leaving loc 8 sru 4
  5899. #endif
  5900. pat loc dvu $1==2 && $2==WORD_SIZE leaving loc 1 sru WORD_SIZE
  5901. pat loc dvu $1==4 && $2==WORD_SIZE leaving loc 2 sru WORD_SIZE
  5902. pat loc dvu $1==8 && $2==WORD_SIZE leaving loc 3 sru WORD_SIZE
  5903. pat loc dvu $1==16 && $2==WORD_SIZE leaving loc 4 sru WORD_SIZE
  5904. pat loc dvu $1==32 && $2==WORD_SIZE leaving loc 5 sru WORD_SIZE
  5905. pat loc dvu $1==64 && $2==WORD_SIZE leaving loc 6 sru WORD_SIZE
  5906. pat loc dvu $1==128 && $2==WORD_SIZE leaving loc 7 sru WORD_SIZE
  5907. pat loc dvu $1==256 && $2==WORD_SIZE leaving loc 8 sru WORD_SIZE
  5908. #if WORD_SIZE==2
  5909. pat ldc dvi highw($1)==0 && loww($1)==2 && $2==4
  5910. with DD_REG4
  5911. gen test %1
  5912. bpl {slabel,1f}
  5913. add_l {const4,loww($1)-1},%1
  5914. 1: yields %1 leaving loc 1 sri 4
  5915. pat ldc dvi highw($1)==0 && loww($1)==4 && $2==4
  5916. with DD_REG4
  5917. gen test %1
  5918. bpl {slabel,1f}
  5919. add_l {const4,loww($1)-1},%1
  5920. 1: yields %1 leaving loc 2 sri 4
  5921. pat ldc dvi highw($1)==0 && loww($1)==8 && $2==4
  5922. with DD_REG4
  5923. gen test %1
  5924. bpl {slabel,1f}
  5925. add_l {const4,loww($1)-1},%1
  5926. 1: yields %1 leaving loc 3 sri 4
  5927. pat ldc dvi highw($1)==0 && loww($1)==16 && $2==4
  5928. with DD_REG4
  5929. gen test %1
  5930. bpl {slabel,1f}
  5931. add_l {const4,loww($1)-1},%1
  5932. 1: yields %1 leaving loc 4 sri 4
  5933. pat ldc dvi highw($1)==0 && loww($1)==32 && $2==4
  5934. with DD_REG4
  5935. gen test %1
  5936. bpl {slabel,1f}
  5937. add_l {const4,loww($1)-1},%1
  5938. 1: yields %1 leaving loc 5 sri 4
  5939. pat ldc dvi highw($1)==0 && loww($1)==64 && $2==4
  5940. with DD_REG4
  5941. gen test %1
  5942. bpl {slabel,1f}
  5943. add_l {const4,loww($1)-1},%1
  5944. 1: yields %1 leaving loc 6 sri 4
  5945. pat ldc dvi highw($1)==0 && loww($1)==128 && $2==4
  5946. with DD_REG4
  5947. gen test %1
  5948. bpl {slabel,1f}
  5949. add_l {const4,loww($1)-1},%1
  5950. 1: yields %1 leaving loc 7 sri 4
  5951. pat ldc dvi highw($1)==0 && loww($1)==256 && $2==4
  5952. with DD_REG4
  5953. gen test %1
  5954. bpl {slabel,1f}
  5955. add_l {const4,loww($1)-1},%1
  5956. 1: yields %1 leaving loc 8 sri 4
  5957. #endif /* WORD_SIZE==2 */
  5958. pat loc dvi $1==2 && $2==WORD_SIZE
  5959. with DD_REG
  5960. gen test %1
  5961. bpl {slabel,1f}
  5962. add_i {const,$1-1},%1
  5963. 1: yields %1 leaving loc 1 sri WORD_SIZE
  5964. pat loc dvi $1==4 && $2==WORD_SIZE
  5965. with DD_REG
  5966. gen test %1
  5967. bpl {slabel,1f}
  5968. add_i {const,$1-1},%1
  5969. 1: yields %1 leaving loc 2 sri WORD_SIZE
  5970. pat loc dvi $1==8 && $2==WORD_SIZE
  5971. with DD_REG
  5972. gen test %1
  5973. bpl {slabel,1f}
  5974. add_i {const,$1-1},%1
  5975. 1: yields %1 leaving loc 3 sri WORD_SIZE
  5976. pat loc dvi $1==16 && $2==WORD_SIZE
  5977. with DD_REG
  5978. gen test %1
  5979. bpl {slabel,1f}
  5980. add_i {const,$1-1},%1
  5981. 1: yields %1 leaving loc 4 sri WORD_SIZE
  5982. pat loc dvi $1==32 && $2==WORD_SIZE
  5983. with DD_REG
  5984. gen test %1
  5985. bpl {slabel,1f}
  5986. add_i {const,$1-1},%1
  5987. 1: yields %1 leaving loc 5 sri WORD_SIZE
  5988. pat loc dvi $1==64 && $2==WORD_SIZE
  5989. with DD_REG
  5990. gen test %1
  5991. bpl {slabel,1f}
  5992. add_i {const,$1-1},%1
  5993. 1: yields %1 leaving loc 6 sri WORD_SIZE
  5994. pat loc dvi $1==128 && $2==WORD_SIZE
  5995. with DD_REG
  5996. gen test %1
  5997. bpl {slabel,1f}
  5998. add_i {const,$1-1},%1
  5999. 1: yields %1 leaving loc 7 sri WORD_SIZE
  6000. pat loc dvi $1==256 && $2==WORD_SIZE
  6001. with DD_REG
  6002. gen test %1
  6003. bpl {slabel,1f}
  6004. add_i {const,$1-1},%1
  6005. 1: yields %1 leaving loc 8 sri WORD_SIZE
  6006. /* The rest is all 2-bytes stuff */
  6007. #if WORD_SIZE==2
  6008. pat loc loc cii $1==4 && $2==2
  6009. with D_REG4
  6010. yields %1.1
  6011. with any2-pre_post any2-pre_post
  6012. yields %2
  6013. proc cmqtxx
  6014. with exact sconsts4 any4
  6015. uses DD_REG4=%1
  6016. gen cmp_l %2, %a
  6017. s4xx[2] %a
  6018. neg_b %a.1
  6019. yields {extend1, %a.1}
  6020. with exact any4 sconsts4
  6021. uses DD_REG4=%2
  6022. gen cmp_l %1, %a
  6023. s4xx[1] %a
  6024. neg_b %a.1
  6025. yields {extend1, %a.1}
  6026. with any4-sconsts4 genreg4
  6027. uses reusing %1,reusing %2,DD_REG4
  6028. gen cmp_l %1, %2
  6029. s4xx[1] %a
  6030. neg_b %a.1
  6031. yields {extend1, %a.1}
  6032. with genreg4 any4-sconsts4
  6033. uses reusing %1,reusing %2,DD_REG4
  6034. gen cmp_l %2, %1
  6035. s4xx[2] %a
  6036. neg_b %a.1
  6037. yields {extend1, %a.1}
  6038. with exact extend1_4 extend1_4
  6039. uses reusing %1,reusing %2,DD_REG4
  6040. gen cmp_b %2, %1
  6041. s4xx[2] %a
  6042. neg_b %a.1
  6043. yields {extend1, %a.1}
  6044. with exact extend2 extend2
  6045. uses reusing %1,reusing %2,DD_REG4
  6046. gen cmp_w %2, %1
  6047. s4xx[2] %a
  6048. neg_b %a.1
  6049. yields {extend1, %a.1}
  6050. with exact immediate4-sconsts4 imm_cmp4
  6051. uses reusing %2,DD_REG4
  6052. gen cmp_l %1, %2
  6053. s4xx[1] %a
  6054. neg_b %a.1
  6055. yields {extend1, %a.1}
  6056. with exact imm_cmp4 immediate4-sconsts4
  6057. uses reusing %1,DD_REG4
  6058. gen cmp_l %2, %1
  6059. s4xx[2] %a
  6060. neg_b %a.1
  6061. yields {extend1, %a.1}
  6062. with exact immediate4-sconsts4 STACK
  6063. uses DD_REG4
  6064. gen cmp_l %1, {post_inc4, sp}
  6065. s4xx[1] %a
  6066. neg_b %a.1
  6067. yields {extend1, %a.1}
  6068. with exact any4 STACK
  6069. uses reusing %1,DD_REG4=%1
  6070. gen cmp_l {post_inc4, sp}, %a
  6071. s4xx[2] %a
  6072. neg_b %a.1
  6073. yields {extend1, %a.1}
  6074. with exact STACK
  6075. uses DD_REG4
  6076. gen move_l {post_inc4, sp},%a
  6077. cmp_l {post_inc4, sp},%a
  6078. s4xx[2] %a
  6079. neg_b %a.1
  6080. yields {extend1, %a.1}
  6081. pat cmi tlt $1==4 call cmqtxx("slt","sgt")
  6082. pat cmi tle $1==4 call cmqtxx("sle","sge")
  6083. pat cmi teq $1==4 call cmqtxx("seq","seq")
  6084. pat cmi tne $1==4 call cmqtxx("sne","sne")
  6085. pat cmi tge $1==4 call cmqtxx("sge","sle")
  6086. pat cmi tgt $1==4 call cmqtxx("sgt","slt")
  6087. pat cmu tlt $1==4 call cmqtxx("scs","shi")
  6088. pat cmu tle $1==4 call cmqtxx("sls","scc")
  6089. pat cmu teq $1==4 call cmqtxx("seq","seq")
  6090. pat cmu tne $1==4 call cmqtxx("sne","sne")
  6091. pat cmu tge $1==4 call cmqtxx("scc","sls")
  6092. pat cmu tgt $1==4 call cmqtxx("shi","scs")
  6093. proc cmqzxx example cmu zlt
  6094. with zero_const4 test_set4 STACK
  6095. /* kills ALL */
  6096. gen test %2
  6097. bxx[1] {llabel, $2}
  6098. with exact sconsts4-zero_const4 any4
  6099. kills ALL
  6100. uses DD_REG4=%1
  6101. gen cmp_l %2, %a
  6102. bxx[2] {llabel, $2}
  6103. with exact any4 sconsts4
  6104. kills ALL
  6105. uses DD_REG4=%2
  6106. gen cmp_l %1, %a
  6107. bxx[1] {llabel, $2}
  6108. with any4-sconsts4-zero_const4 genreg4 STACK
  6109. gen cmp_l %1, %2
  6110. bxx[1] {llabel, $2}
  6111. with genreg4 any4-sconsts4-zero_const4 STACK
  6112. gen cmp_l %2, %1
  6113. bxx[2] {llabel, $2}
  6114. with exact immediate4-sconsts4-zero_const4 imm_cmp4
  6115. kills ALL
  6116. gen cmp_l %1, %2
  6117. bxx[1] {llabel, $2}
  6118. with exact imm_cmp4 immediate4-sconsts4-zero_const4
  6119. kills ALL
  6120. gen cmp_l %2, %1
  6121. bxx[2] {llabel, $2}
  6122. with exact immediate4-sconsts4-zero_const4 STACK
  6123. gen cmp_l %1, {post_inc4, sp}
  6124. bxx[1] {llabel, $2}
  6125. with exact any4 STACK
  6126. uses reusing %1, DD_REG4=%1
  6127. gen cmp_l {post_inc4, sp}, %a
  6128. bxx[2] {llabel, $2}
  6129. with exact STACK
  6130. uses DD_REG4
  6131. gen move_l {post_inc4, sp},%a
  6132. cmp_l {post_inc4, sp},%a
  6133. bxx[2] {llabel, $2}
  6134. with data2-sconsts dreg2 STACK
  6135. gen cmp_w %1, %2
  6136. bxx[1] {llabel, $2}
  6137. with dreg2 data2-conreg2-sconsts STACK
  6138. gen cmp_w %2, %1
  6139. bxx[2] {llabel, $2}
  6140. with data1 dreg1 STACK
  6141. gen cmp_b %1, %2
  6142. bxx[1] {llabel, $2}
  6143. with dreg1 data1-conreg1 STACK
  6144. gen cmp_b %2, %1
  6145. bxx[2] {llabel, $2}
  6146. pat cmi zlt $1==4 call cmqzxx("blt","bgt")
  6147. pat cmi zle $1==4 call cmqzxx("ble","bge")
  6148. pat cmi zeq $1==4 call cmqzxx("beq","beq")
  6149. pat cmi zne $1==4 call cmqzxx("bne","bne")
  6150. pat cmi zge $1==4 call cmqzxx("bge","ble")
  6151. pat cmi zgt $1==4 call cmqzxx("bgt","blt")
  6152. pat cms zeq $1==4 call cmqzxx("beq","beq")
  6153. pat cms zne $1==4 call cmqzxx("bne","bne")
  6154. pat cmu zlt $1==4 call cmqzxx("bcs","bhi")
  6155. pat cmu zle $1==4 call cmqzxx("bls","bcc")
  6156. pat cmu zeq $1==4 call cmqzxx("beq","beq")
  6157. pat cmu zne $1==4 call cmqzxx("bne","bne")
  6158. pat cmu zge $1==4 call cmqzxx("bcc","bls")
  6159. pat cmu zgt $1==4 call cmqzxx("bhi","bcs")
  6160. pat ldc cms zeq loww($1)==0 && highw($1)==0 && $2==4
  6161. with test_set4 STACK
  6162. gen test %1
  6163. beq {llabel, $3}
  6164. pat ldc cms zne loww($1)==0 && highw($1)==0 && $2==4
  6165. with test_set4 STACK
  6166. gen test %1
  6167. bne {llabel, $3}
  6168. #endif