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@@ -0,0 +1,458 @@
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+.sect .text
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+.define _main
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+.define _main2
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+.define _xxx
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+! integer arithmetic and logical instructions
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+
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+_main:
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+.data2 0x0
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+adawi r0, r1
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+addb2 r0,r1
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+addb3 r0,r2,r4
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+addw2 r0,r1
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+addw3 r0,r2,r4
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+addl2 r0,r1
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+addl3 r0,r2,r4
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+adwc r0, r1
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+ashl r0, r1, r2
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+ashq r0, r1, r2
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+bicb2 r0,r1
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+bicb3 r0,r2,r4
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+bicw2 r0,r1
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+bicw3 r0,r2,r4
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+bicl2 r0,r1
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+bicl3 r0,r2,r4
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+bisb2 r0,r1
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+bisb3 r0,r2,r4
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+bisw2 r0,r1
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+bisw3 r0,r2,r4
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+bisl2 r0,r1
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+bisl3 r0,r2,r4
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+bitb r0, r1
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+bitw r0, r1
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+bitl r0, r1
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+clrb r0
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+clrw r0
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+clrl r0
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+clrq r0
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+clro r0
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+cmpb r0, r1
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+cmpw r0, r1
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+cmpl r0, r1
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+cvtbw r0, r1
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+cvtbl r0, r1
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+cvtwb r0, r1
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+cvtwl r0, r1
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+cvtlb r0, r1
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+cvtlw r0, r1
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+decb r0
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+decw r0
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+decl r0
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+divb2 r0,r1
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+divb3 r0,r2,r4
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+divw2 r0,r1
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+divw3 r0,r2,r4
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+divl2 r0,r1
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+divl3 r0,r2,r4
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+ediv r0,r1,r2,r3
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+emul r0,r1,r2,r3
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+incb r0
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+incw r0
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+incl r0
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+mcomb r0, r1
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+mcomw r0, r1
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+mcoml r0, r1
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+mnegb r0, r1
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+mnegw r0, r1
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+mnegl r0, r1
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+movb r0, r1
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+movw r0, r1
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+movl r0, r1
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+movq r0, r1
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+movo r0, r1
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+movzbw r0, r1
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+movzbl r0, r1
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+movzwl r0, r1
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+mulb2 r0,r1
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+mulb3 r0,r2,r4
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+mulw2 r0,r1
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+mulw3 r0,r2,r4
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+mull2 r0,r1
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+mull3 r0,r2,r4
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+pushl r0
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+pushl $1
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+rotl r0, r1, r2
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+sbwc r0, r1
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+subb2 r0,r1
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+subb3 r0,r2,r4
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+subw2 r0,r1
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+subw3 r0,r2,r4
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+subl2 r0,r1
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+subl3 r0,r2,r4
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+tstb r0
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+tstw r0
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+tstl r0
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+xorb2 r0,r1
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+xorb3 r0,r2,r4
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+xorw2 r0,r1
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+xorw3 r0,r2,r4
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+xorl2 r0,r1
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+xorl3 r0,r2,r4
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+
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+!* Address instructions */
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+
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+movab (sp),r0
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+movaw (sp),r0
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+moval (sp),r0
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+movaf (sp),r0
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+movaq (sp),r0
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+movad (sp),r0
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+movag (sp),r0
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+movah (sp),r0
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+movao (sp),r0
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+pushab (sp)
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+pushaw (sp)
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+pushal (sp)
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+pushaf (sp)
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+pushaq (sp)
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+pushad (sp)
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+pushag (sp)
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+pushah (sp)
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+pushao (sp)
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+
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+!* Variable length bit-field instructions */
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+
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+cmpv r0,r1,r2,r3
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+cmpzv r0,r1,r2,r3
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+extv r0,r1,r2,r3
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+extzv r0,r1,r2,r3
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+ffc r0,r1,r2,r3
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+ffs r0,r1,r2,r3
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+insv r0,r1,r2,r3
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+
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+!* Control instructions */
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+
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+acbb r0,r1,r2,_main
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+acbw r0,r1,r2,_main
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+acbl r0,r1,r2,_main
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+acbf r0,r1,r2,_main
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+acbd r0,r1,r2,_main
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+acbg r0,r1,r2,_main
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+acbh r0,r1,r2,_main
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+aobleq r0, r1, 1f
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+1:
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+aoblss r0, r1, 1f
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+1:
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+bgtr 1f
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+1:
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+bleq 1f
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+1:
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+bneq 1f
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+1:
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+bnequ 1f
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+1:
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+beql 1f
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+1:
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+beqlu 1f
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+1:
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+bgeq 1f
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+1:
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+blss 1f
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+1:
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+bgtru 1f
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+1:
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+blequ 1f
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+1:
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+bvc 1f
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+1:
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+bvs 1f
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+1:
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+bgequ 1f
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+1:
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+bcc 1f
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+1:
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+blssu 1f
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+1:
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+bcs 1f
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+1:
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+bbs r0, r1, 1f
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+1:
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+bbc r0, r1, 1f
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+1:
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+bbss r0, r1, 1f
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+1:
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+bbcs r0, r1, 1f
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+1:
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+bbsc r0, r1, 1f
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+1:
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+bbcc r0, r1, 1f
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+1:
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+bbssi r0, r1, 1f
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+1:
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+bbcci r0, r1, 1f
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+1:
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+blbs r0,1f
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+blbc r0,1f
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+1:
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+jgtr _main
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+jleq _main
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+jneq _main
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+jnequ _main
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+jeql _main
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+jeqlu _main
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+jgeq _main
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+jlss _main
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+jgtru _main
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+jlequ _main
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+jvc _main
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+jvs _main
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+jgequ _main
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+jcc _main
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+jlssu _main
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+jcs _main
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+jlbs r0, _main
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+jlbc r0, _main
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+jbs r0, r1, _main
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+jbc r0, r1, _main
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+jbss r0, r1, _main
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+jbcs r0, r1, _main
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+jbsc r0, r1, _main
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+jbcc r0, r1, _main
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+jbssi r0, r1, _main
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+jbcci r0, r1, _main
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+br _main
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+br _main2
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+brb 1f
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+1:
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+brw 1f
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+1:
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+jbr _main
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+jbr _main2
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+bsb 1f
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+1:
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+caseb r0, r1, r2
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+casew r0, r1, r2
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+casel r0, r1, r2
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+jmp _main
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+jsb _main
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+rsb
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+sobgeq r0, 1f
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+sobgtr r0, 1f
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+1:
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+
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+!* Procedure call instructions */
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+
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+callg (sp),_main
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+calls $2, _main
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+ret
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+
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+!* Miscellaneous instructions */
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+
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+bicpsw r0
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+bispsw r0
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+bpt
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+halt
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+index r0,r1,r2,r3,r4,r5
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+movpsl r0
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+nop
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+popr r0
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+pushr r0
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+xfc
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+
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+!* Queue instructions */
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+
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+insqhi (sp), _main
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+insqti (sp), _main
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+insque (sp), _main
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+remqhi (sp), _main
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+remqti (sp), _main
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+remque (sp), _main
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+
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+!* Floating point instructions */
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+
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+addf2 r0,r1
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+addf3 r0,r2,r4
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+addd2 r0,r1
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+addd3 r0,r2,r4
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+addg2 r0,r1
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+addg3 r0,r2,r4
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+addh2 r0,r1
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+addh3 r0,r2,r4
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+clrf r0
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+clrd r0
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+clrg r0
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+clrh r0
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+cmpf r0,r2
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+cmpd r0,r2
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+cmpg r0,r2
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+cmph r0,r2
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+cvtbf r0,r2
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+cvtbd r0,r2
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+cvtbg r0,r2
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+cvtbh r0,r2
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+cvtwf r0,r2
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+cvtwd r0,r2
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+cvtwg r0,r2
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+cvtwh r0,r2
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+cvtlf r0,r2
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+cvtld r0,r2
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+cvtlg r0,r2
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+cvtlh r0,r2
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+cvtfb r0,r2
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+cvtdb r0,r2
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+cvtgb r0,r2
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+cvthb r0,r2
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+cvtfw r0,r2
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+cvtdw r0,r2
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+cvtgw r0,r2
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+cvthw r0,r2
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+cvtfl r0,r2
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+cvtdl r0,r2
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+cvtgl r0,r2
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+cvthl r0,r2
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+cvtrfl r0,r2
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+cvtrdl r0,r2
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+cvtrgl r0,r2
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+cvtrhl r0,r2
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+cvtfd r0,r2
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+cvtfg r0,r2
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+cvtfh r0,r2
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+cvtdf r0,r2
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+cvtdh r0,r2
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+cvtgf r0,r2
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+cvtgh r0,r2
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+cvthf r0,r2
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+cvthd r0,r2
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+cvthg r0,r2
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+divf2 r0,r1
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+divf3 r0,r2,r4
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+divd2 r0,r1
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+divd3 r0,r2,r4
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+divg2 r0,r1
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+divg3 r0,r2,r4
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+divh2 r0,r1
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+divh3 r0,r2,r4
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+emodf (r0),(r1),(r2),(r3),(r4)
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+emodd (r0),(r1),(r2),(r3),(r4)
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+emodg (r0),(r1),(r2),(r3),(r4)
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+emodh (r0),(r1),(r2),(r3),(r4)
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+mnegf r0,r2
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+mnegd r0,r2
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+mnegg r0,r2
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+mnegh r0,r2
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+movf r0,r2
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+movd r0,r2
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+movg r0,r2
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+movh r0,r2
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+mulf2 r0,r1
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+mulf3 r0,r2,r4
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+muld2 r0,r1
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+muld3 r0,r2,r4
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+mulg2 r0,r1
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+mulg3 r0,r2,r4
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+mulh2 r0,r1
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+mulh3 r0,r2,r4
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+polyf r0,r2,(sp)
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+polyd r0,r2,(sp)
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+polyg r0,r2,(sp)
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+polyh r0,r2,(sp)
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+subf2 r0,r1
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+subf3 r0,r2,r4
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+subd2 r0,r1
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+subd3 r0,r2,r4
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+subg2 r0,r1
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+subg3 r0,r2,r4
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+subh2 r0,r1
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+subh3 r0,r2,r4
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+tstf r0
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+tstd r0
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+tstg r0
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+tsth r0
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+
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+!* Character string instructions */
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+
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+cmpc3 r0,(sp),(r1)
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+cmpc5 (r0),(r1),(r2),(r3),(r4)
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+locc (r0),(r1),(r2)
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+matchc (r0),(r1),(r2),(r3)
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+movc3 r0,(sp),(r1)
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+movc5 (r0),(r1),(r2),(r3),(r4)
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+movtc (r0),(r1),(r2),(r3),(r4),(r4)
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+movtuc (r0),(r1),(r2),(r3),(r4),(r4)
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+scanc (r0),(r1),(r2),(r3)
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+skpc r0,(sp),(r1)
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+spanc (r0),(r1),(r2),(r3)
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+
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+!* Cyclic redundancy check instructions */
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+
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+crc (r0),(r1),(r2),(r3)
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+
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+!* Decimal string instructions */
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+
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+addp4 (r0),(r1),(r2),(r3)
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+addp6 (r0),(r1),(r2),(r3),(r4),(r4)
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+ashp (r0),(r1),(r2),(r3),(r4),(r4)
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+cmpp3 r0,(sp),(r1)
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+cmpp4 (r0),(r1),(r2),(r3)
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+cvtlp (r0),(r1),(r2)
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+cvtpl (r0),(r1),(r2)
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+cvtps (r0),(r1),(r2),(r3)
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+cvtpt (r0),(r1),(r2),(r3),(r4)
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+cvtsp (r0),(r1),(r2),(r3)
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+cvttp (r0),(r1),(r2),(r3),(r4)
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+divp (r0),(r1),(r2),(r3),(r4),(r4)
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+movp (r0),(r1),(r2)
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+mulp (r0),(r1),(r2),(r3),(r4),(r4)
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+subp4 (r0),(r1),(r2),(r3)
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+subp6 (r0),(r1),(r2),(r3),(r4),(r4)
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+
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+!* Edit instruction */
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+
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+editpc (r0),(r1),(r2),(r3)
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+
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+!* Other VAX-11 instructions */
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+
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+bugw _main
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+bugl _main
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+
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+prober (r0),(r1),(r2)
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+probew (r0),(r1),(r2)
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+
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+rei
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+chmk r0
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+chme r0
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|
|
+chms r0
|
|
|
+chmu r0
|
|
|
+
|
|
|
+ldpctx
|
|
|
+svpctx
|
|
|
+mtpr r0,r1
|
|
|
+mfpr r0,r1
|
|
|
+
|
|
|
+! test some addressing modes
|
|
|
+_main2:
|
|
|
+.data2 0x0
|
|
|
+pushal _xxx
|
|
|
+pushal _main
|
|
|
+pushal _main2
|
|
|
+pushal *_xxx
|
|
|
+pushal *_main
|
|
|
+pushal *_main2
|
|
|
+movl $_xxx,-(sp)
|
|
|
+movl $_main2,-(sp)
|
|
|
+movl *$_main2,-(sp)
|
|
|
+movl (sp)+,r9
|
|
|
+movl *(sp)+,r9
|
|
|
+movl (r0),r9
|
|
|
+movl 12(r0),r9
|
|
|
+movl *12(r0),r9
|
|
|
+movl _xxx(r0),r9
|
|
|
+movl *_xxx(r0),r9
|
|
|
+movl *_xxx(r0)[r1],r9
|
|
|
+movb *_xxx(r0)[r1],r9
|
|
|
+movw *_xxx(r0)[r1],r9
|
|
|
+
|
|
|
+
|
|
|
+.sect .rom
|
|
|
+_xxx:
|
|
|
+ .data2 0
|