/* ARM DESCRIPTOR TABLE FOR ACK TARGET OPTIMISER */

MAXOP           5;
MAXLINELEN      50;
 
%%;
 
ZERO			{strcmp(VAL,"#0") ==0};
CONST,C1,C2,C3,C4 	{VAL[0] == '#'};
REG,REG1,REG2		{is_register(VAL)};
LAB			{VAL[0] == 'I'};
LL,X,Y,Z,W,LOG1,LOG2	{TRUE};
XX			{no_side_effects(VAL)};
YY,ZZ,VV,WW		{TRUE};
RL11			{is_reglist_11(VAL)};
RL1,RL2,RL3,RL4		{is_reglist1(VAL)};
RL13			{is_local(VAL)};
X1,X2,Y1,Y2,Z1,Z2,V1,V2 {TRUE};

%%;
 
/* save space */
ADD REG,REG,ZERO			   -> ;
MOV REG, REG				   -> ;
STMFD R12<,X:LDMFD R12<,X		   -> ;
CMP REG,REG:BNE X1			   -> ;
MOV REG,ZERO : ADD REG,REG,CONST	   -> MOV REG,CONST;
STR REG,XX,Y : LDR REG,XX,Y		   -> STR REG,XX,Y;
LDR REG,XX,Y: STMFD R12<,Z:LDR REG,XX,Y	   -> LDR REG,XX,Y : STMFD R12<,Z;
LDR REG,XX,Y: STMFD R12<,Z,W:LDR REG,XX,Y  -> LDR REG,XX,Y : STMFD R12<,Z,W;
STR REG,XX : LDR REG,XX			   -> STR REG,XX;
LDR REG,XX : STMFD R12<,Z:LDR REG,XX	   -> LDR REG,XX : STMFD R12<,Z;
LDR REG,XX : STMFD R12<,Z,W:LDR REG,XX     -> LDR REG,XX : STMFD R12<,Z,W;
MOV REG, #-2147483648:RSB REG,REG,ZERO	   -> MOV REG,#-2147483648;
ADD R12,X,Y : MOV R12,R13		   -> MOV R12,R13;
MOV R11,REG:STMFD R12<,R11		   -> STMFD R12<,REG;
MOV REG,ZERO:MOV REG1,REG,LSR#8:
SUB REG,REG,REG1,LSL#8			   -> MOV REG,ZERO;

/* conditionals */
SUB.S REG,X,Y : CMP REG,ZERO               -> SUB.S REG,X,Y;
ADD.S REG,X,Y : CMP REG,ZERO               -> ADD.S REG,X,Y;
ORR.S REG,X,Y : CMP REG,ZERO               -> ORR.S REG,X,Y;
AND.S REG,X,Y : CMP REG,ZERO               -> AND.S REG,X,Y;
EOR.S REG,X,Y : CMP REG,ZERO               -> EOR.S REG,X,Y;
 
SUB REG,X,Y : CMP REG,ZERO                 -> SUB.S REG,X,Y;
ADD REG,X,Y : CMP REG,ZERO                 -> ADD.S REG,X,Y;
ORR REG,X,Y : CMP REG,ZERO                 -> ORR.S REG,X,Y;
AND REG,X,Y : CMP REG,ZERO                 -> AND.S REG,X,Y;
EOR REG,X,Y : CMP REG,ZERO                 -> EOR.S REG,X,Y;
 
/* speed increase */
STR REG,XX,Y : LDR REG1,XX,Y
	{is_unequal(REG,REG1)}		   -> STR REG,XX,Y : MOV REG1,REG;
LDR REG,XX,Y : LDR REG1,XX,Y
	{is_unequal(REG,REG1)}		   -> LDR REG,XX,Y : MOV REG1,REG;
STR REG,X    : LDR REG1,X
	{is_unequal(REG,REG1)}		   -> STR REG,X    : MOV REG1,REG;
LDR REG,X    : LDR REG1,X
	{is_unequal(REG,REG1)}		   -> LDR REG,X    : MOV REG1,REG;

LDR REG,XX,Y : STR REG,Z,W : LDR REG,XX,Y  -> LDR REG,XX,Y : STR REG,Z,W;
LDR REG,X    : STR REG,Z,W : LDR REG,X	   -> LDR REG,X    : STR REG,Z,W;

MOV REG,C1   :STMFD R12<,X,Y : MOV REG,C1  -> MOV REG,C1   : STMFD R12<,X,Y;
MOV REG,C1   :STR REG,X,Y    : MOV REG,C1  -> MOV REG,C1   : STR REG,X,Y;
MOV REG,C1   :STR REG,X      : MOV REG,C1  -> MOV REG,C1   : STR REG,X;

MOV REG, ZERO: ADD REG1,REG1,REG	   -> MOV REG,ZERO;
MOV REG, ZERO: ADD REG,REG,CONST	   -> MOV REG,CONST;

/* for loops */
LDR REG,XX,Y:CMP REG,Z:
BEQ LAB:LDR REG,XX,Y			   -> LDR REG,XX,Y:CMP REG,Z:BEQ LAB;
 
/* illegal constant optimisation */
MOV REG,CONST: RSB REG1,REG,#0 
	{is_byte(CONST,LOG1)}		   -> MVN REG1,#LOG1;

MOV REG,CONST:ADD REG,REG,#65280:
ADD REG,REG,#16711680:
ADD REG,REG,#-16777216
	{is_byte2(CONST,LOG1,LOG2)}	   -> MOV REG,#LOG1:
					      MOV REG,REG,ASR#LOG2;

MOV REG,CONST:ADD REG,REG,#65280:
ADD REG,REG,#16711680:
ADD REG,REG,#-16777216:
ADD REG1,REG1,REG
	{is_byte2(CONST,LOG1,LOG2) && is_unequal(REG1,REG)}
					   -> MOV REG,#LOG1:
					      ADD REG1,REG1,REG,ASR#LOG2;

/* combine ldm's and stm's */
STMFD R12<, RL1: STMFD R12<, RL2
	{is_greater(RL1,RL2,W)}		   -> STMFD R12<,W;
LDMFD R12<, RL1: LDMFD R12<, RL2
	{is_greater(RL2,RL1,W)}		   -> LDMFD R12<,W;

/* unsigned comparisons */
/*MOV.HI REG, #-1:MOV.LS REG, #1:
MOV.EQ REG, #0:CMP REG, #0:BGT LAB	   -> BLS LAB;
*/
MOV.HI REG, #-1:MOV.LS REG, #1:
MOV.EQ REG, #0:CMP REG, #0:BGE LAB	   -> BLS LAB /*: BEQ LAB */ ;
MOV.HI REG, #-1:MOV.LS REG, #1:
MOV.EQ REG, #0:CMP REG, #0:BLE LAB	   -> BHI LAB: BEQ LAB;
MOV.HI REG, #-1:MOV.LS REG, #1:
MOV.EQ REG, #0:CMP REG, #0:BLT LAB	   -> BHI LAB;

MOV.HI REG, #1:MOV.LS REG, #-1:
MOV.EQ REG, #0:CMP REG, #0:BGT LAB	   -> BHI LAB;
MOV.HI REG, #1:MOV.LS REG, #-1:
MOV.EQ REG, #0:CMP REG, #0:BGE LAB	   -> BHI LAB: BEQ LAB;
MOV.HI REG, #1:MOV.LS REG, #-1:
MOV.EQ REG, #0:CMP REG, #0:BLE LAB	   -> BLS LAB /*: BEQ LAB */ ;
/*
MOV.HI REG, #1:MOV.LS REG, #-1:
MOV.EQ REG, #0:CMP REG, #0:BLT LAB	   -> BLS LAB;
*/

MOV REG,REG1:RSB REG,REG,ZERO
	{is_unequal(REG,REG1)}		   -> RSB REG,REG1,ZERO;

MOV REG,REG1:AND REG,REG,REG2
	{is_unequal3(REG,REG1,REG2)}	   -> AND REG,REG1,REG2;
MOV REG,REG1:ORR REG,REG,REG2
	{is_unequal3(REG,REG1,REG2)}	   -> ORR REG,REG1,REG2;
MOV REG,REG1:EOR REG,REG,REG2
	{is_unequal3(REG,REG1,REG2)}	   -> EOR REG,REG1,REG2;

/* combine successive pushes into one single multiple push */

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
ADD R11,Y1,Y2 : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1,X2 : ADD R10,Y1,Y2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
ADD R11,Y1,Y2 : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1    : ADD R10,Y1,Y2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1    : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1    : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1    : LDR R10,Y1 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 : BAL.L LL
	{is_lams(ANY) && list_f_10(WW)}  ->
ANY R11,X1    : MOV R10,Y1 : STMFD R12<,WW : BAL.L LL  ;

/* three push sequences */

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : SUB R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : LDR R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck1(10,Z1) && list_f_9(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : MOV R9,Z1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : SUB R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : LDR R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck1(10,Z1) && list_f_9(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : MOV R9,Z1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : SUB R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : LDR R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck1(10,Z1) && list_f_9(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : MOV R9,Z1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : SUB R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : LDR R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck1(10,Z1) && list_f_9(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : MOV R9,Z1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : SUB R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : LDR R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck1(10,Z1) && list_f_9(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : MOV R9,Z1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : SUB R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck2(10,Z1,Z2) && list_f_9(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : LDR R9,Z1,Z2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 : BAL.L LL
{ ok_regcheck1(10,Z1) && list_f_9(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : MOV R9,Z1    : STMFD R12<,WW : BAL.L LL  ;

/* four push sequences */

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : SUB R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : SUB R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : SUB R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : LDR R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : LDR R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : LDR R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : MOV R9,Z1    : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : MOV R9,Z1    : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck2(10,Z1,V1) && list_f_8(WW)}  ->
ANY R11,X1    : SUB R10,Y1,Y2 : MOV R9,Z1    : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : SUB R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : SUB R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : SUB R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : LDR R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : LDR R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : LDR R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : MOV R9,Z1    : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : MOV R9,Z1    : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck2(10,Z1,V1) && list_f_8(WW)}  ->
ANY R11,X1    : LDR R10,Y1,Y2 : MOV R9,Z1    : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : SUB R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : SUB R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : SUB R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : LDR R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : LDR R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : LDR R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : MOV R9,Z1    : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : MOV R9,Z1    : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1    : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck2(10,Z1,V1) && list_f_8(WW)}  ->
ANY R11,X1    : MOV R10,Y1    : MOV R9,Z1    : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : SUB R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : SUB R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : SUB R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : LDR R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : LDR R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : LDR R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : MOV R9,Z1    : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : MOV R9,Z1    : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
SUB R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck2(10,Z1,V1) && list_f_8(WW)}  ->
ANY R11,X1,X2 : SUB R10,Y1,Y2 : MOV R9,Z1    : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : SUB R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : SUB R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : SUB R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : LDR R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : LDR R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : LDR R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : MOV R9,Z1    : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : MOV R9,Z1    : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
LDR R11,Y1,Y2 : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck2(10,Z1,V1) && list_f_8(WW)}  ->
ANY R11,X1,X2 : LDR R10,Y1,Y2 : MOV R9,Z1    : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : SUB R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : SUB R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
SUB R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : SUB R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : LDR R9,Z1,Z2 : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck4(10,Z1,Z2,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : LDR R9,Z1,Z2 : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
LDR R11,Z1,Z2 : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck3(10,Z1,Z2,V1) && list_f_8(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : LDR R9,Z1,Z2 : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
SUB R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : MOV R9,Z1    : SUB R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
LDR R11,V1,V2 : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck2(9,V1,V2) && ok_regcheck3(10,Z1,V1,V2) && list_f_8(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : MOV R9,Z1    : LDR R8,V1,V2 : STMFD R12<,WW : BAL.L LL  ;

ANY R11,X1,X2 : STMFD R12<,RL11 :
MOV R11,Y1    : STMFD R12<,RL11 :
MOV R11,Z1    : STMFD R12<,RL11 :
MOV R11,V1    : STMFD R12<,RL11 : BAL.L LL
{ok_regcheck1(9,V1) && ok_regcheck2(10,Z1,V1) && list_f_8(WW)}  ->
ANY R11,X1,X2 : MOV R10,Y1    : MOV R9,Z1    : MOV R8,V1    : STMFD R12<,WW : BAL.L LL  ;



%%;
 
int is_register(s)
register char *s;
{ if (*s++ == 'R' && *s >= '0' && *s <= '9') {
      if (*s++ == '1' && (*s >= '0' && *s <= '5')) s++;
      return *s == '\0';
      }
      return FALSE;
}
 
int is_byte(s,t)
char *s, *t;
{
	long arg;

	s++;   /* skip # */
	arg = atol(s);
	if (arg<1 || arg>256) return(FALSE);
	sprintf(t,"%d",arg-1);
	return(TRUE);
}

int is_byte2(s,t1,t2)
char *s,*t1,*t2;
{
	long arg, shift;

	s++;
	arg = atol(s);
	if (arg<1 || arg>255) return(FALSE);
	if (arg & 0x80) {
		shift = arg << 24;
		sprintf(t1,"%ld",shift);
		sprintf(t2,"%d", 24);
		return(TRUE);
	}
	return(FALSE);
}
  
int no_side_effects(s)
register char *s;
{
	for (;;) {
		switch(*s++) {
		  case '\0': return(TRUE);
		  case ']' : return(FALSE);
		  case '<' : return(FALSE);
		}
	}
}

int is_greater(s1, s2, rl)
register char *s1, *s2, *rl;
{
	long a1, a2;

	s1++; s1++;   /* skip '{R' */
	s2++; s2++;
	a1 = atol(s1);
	a2 = atol(s2);
	if (a1 > a2) {
		sprintf(rl, "{R%d,R%d}", a2, a1);
		return(TRUE);
	}
	return(FALSE);
}

int is_local(s)
register char *s;
{
	if (strcmp(s, "[R13") == 0) return(TRUE);
	return(FALSE);
}

int is_reglist_11(s)
register char *s;
{
	if (strcmp(s, "{R11}") == 0){
		return(TRUE);
	}
	return(FALSE);
}

int is_reglist(s)
register char *s;
{
	if (*s == '{') return(TRUE);
	return(FALSE);
}

int is_reglist1(s)
register char *s;
{
	if (*s != '{') return(FALSE);
	for (;;) {
		switch(*s++) {
			case '\0': return(TRUE);
			case ',' : return(FALSE);
		}
	}
}

int is_lams(s)
register char *s;
{
/*	if (strcmp(s,"LDR") == 0) return(TRUE);
	if (strcmp(s,"ADD") == 0) return(TRUE);
	if (strcmp(s,"ADR") == 0) return(TRUE);
	if (strcmp(s,"MOV") == 0) return(TRUE);
	if (strcmp(s,"SUB") == 0) return(TRUE);
	return(FALSE);
*/
return(TRUE);
}

int is_unequal(s1, s2)
register char *s1, *s2;
{
	long a1, a2;

	s1++; s2++;
	a1 = atol(s1);
	a2 = atol(s2);
	if (a1 == a2) return(FALSE);
	return(TRUE);
}

int is_unequal3(s1, s2, s3)
register char *s1, *s2, *s3;
{
	long a1, a2, a3;

	s1++; s2++; s3++;
	a1 = atol(s1);
	a2 = atol(s2);
	a3 = atol(s3);
	if (a1 == a2) return(FALSE);
	if (a3 == a2) return(FALSE);
	if (a1 == a3) return(FALSE);
	return(TRUE);
}

int list_f_10(s)
register char *s;
{
	sprintf(s,"{R10,R11}");
	return(TRUE);
}

int list_f_9(s)
register char *s;
{
	sprintf(s,"{R9,R10,R11}");
	return(TRUE);
}

int list_f_8(s)
register char *s;
{
	sprintf(s,"{R8,R9,R10,R11}");
	return(TRUE);
}

int ok_regcheck1(r, s1)
register char *s1;
int r;
{
	int a1;

	if (*s1 == '[') s1++;
	if (*s1 != 'R') return(TRUE);
	s1++;  /* skip R */
	a1 = atoi(s1);
	if (a1 >= r && a1 <= 11) return(FALSE);
	return(TRUE);
}

int ok_regcheck2(r, s1, s2)
register char *s1, *s2;
int r;
{
	if (ok_regcheck1(r,s1))
		if (ok_regcheck1(r,s2))
			return(TRUE);
	return(FALSE);
}

int ok_regcheck3(r, s1, s2, s3)
register char *s1, *s2, *s3;
int r;
{
	if (ok_regcheck1(r,s1))
		if (ok_regcheck2(r,s2,s3))
			return(TRUE);
	return(FALSE);
}

int ok_regcheck4(r, s1, s2, s3, s4)
register char *s1, *s2, *s3, *s4;
int r;
{
	if (ok_regcheck2(r,s1,s2))
		if (ok_regcheck2(r,s3,s4))
			return(TRUE);
	return(FALSE);
}

int ok_regcheck5(r, s1, s2, s3, s4, s5)
register char *s1, *s2, *s3, *s4, *s5;
int r;
{
	if (ok_regcheck2(r,s1,s2))
		if (ok_regcheck3(r,s3,s4,s5))
			return(TRUE);
	return(FALSE);
}

int ok_regcheck6(r, s1, s2, s3, s4, s5, s6)
register char *s1, *s2, *s3, *s4, *s5, *s6;
int r;
{
	if (ok_regcheck2(r,s1,s2))
		if (ok_regcheck4(r,s3,s4,s5,s6))
			return(TRUE);
	return(FALSE);
}

int ok_regcheck7(r, s1, s2, s3, s4, s5, s6, s7)
register char *s1, *s2, *s3, *s4, *s5, *s6, *s7;
int r;
{
	if (ok_regcheck4(r,s1,s2,s3,s4))
		if (ok_regcheck3(r,s5,s6,s7))
			return(TRUE);
	return(FALSE);
}

int ok_regcheck8(r, s1, s2, s3, s4, s5, s6, s7, s8)
register char *s1, *s2, *s3, *s4, *s5, *s6, *s7, *s8;
int r;
{
	if (ok_regcheck4(r,s1,s2,s3,s4))
		if (ok_regcheck4(r,s5,s6,s7,s8))
			return(TRUE);
	return(FALSE);
}


