uart.vhd 8.4 KB

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  1. --+-----------------------------------+-------------------------------------+--
  2. --| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
  3. --| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
  4. --| / __|/ _ \ / __|_ / _ \| | | | | |--
  5. --| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
  6. --| |___/\___/ \___/___\___/ \___/ | |--
  7. --| | http://sowerbutts.com/ |--
  8. --+-----------------------------------+-------------------------------------+--
  9. --| UART implementation |--
  10. --+-------------------------------------------------------------------------+--
  11. library IEEE;
  12. use IEEE.STD_LOGIC_1164.ALL;
  13. use IEEE.NUMERIC_STD.ALL;
  14. entity uart is
  15. generic (
  16. clk_frequency : natural := (128 * 1000000)
  17. );
  18. port ( clk : in std_logic;
  19. serial_out : out std_logic;
  20. serial_in : in std_logic;
  21. data_in : in std_logic_vector(7 downto 0);
  22. data_in_load : in std_logic;
  23. data_out : out std_logic_vector(7 downto 0);
  24. data_out_ready : out std_logic;
  25. bad_bit : out std_logic;
  26. transmitter_busy : out std_logic;
  27. can_transmit : in std_logic
  28. );
  29. end uart;
  30. architecture Behavioral of uart is
  31. -- tested at 1,000,000bps with 48MHz clock. Works (apparently).
  32. constant rx_sample_interval : unsigned(13 downto 0) := to_unsigned(clk_frequency / (115200 * 16) - 1, 14); -- clock speed / (baud x 16) - 1 ; eg 32MHz / (9600 * 16) - 1 = 207
  33. constant bit_duration : unsigned(13 downto 0) := to_unsigned(clk_frequency / (115200 * 1) - 1, 14); -- clock speed / baud - 1 ; eg 32MHz / 9600 - 1 = 3332
  34. signal tx_counter : unsigned(13 downto 0) := to_unsigned(0, 14);
  35. signal tx_shift_reg : std_logic_vector(8 downto 0) := "111111111";
  36. signal tx_bits_left : unsigned(3 downto 0) := to_unsigned(0, 4);
  37. signal tx_busy : std_logic;
  38. signal rx_counter : unsigned(13 downto 0) := to_unsigned(0, 14);
  39. signal rx_shift_reg : std_logic_vector(8 downto 0) := "000000000";
  40. signal rx_bits_got : unsigned(3 downto 0) := to_unsigned(0, 4);
  41. signal rx_state : unsigned(7 downto 0) := (others => '0'); -- 10 bits x 16 samples each = at least 160 states.
  42. signal rx_out_ready : std_logic := '0';
  43. signal data_out_buf : std_logic_vector(7 downto 0) := "00000000";
  44. signal rx_clkin1 : std_logic := '0';
  45. signal rx_clkin2 : std_logic := '0';
  46. signal rx_sample1 : std_logic := '0';
  47. signal rx_sample2 : std_logic := '0';
  48. signal rx_sample3 : std_logic := '0';
  49. signal rx_sample_majority : std_logic;
  50. signal rx_badbit : std_logic := '0';
  51. begin
  52. -- -- receiver -- --
  53. --
  54. -- Incoming data is oversampled 16 times. We check three samples in the
  55. -- middle of each bit and take a simple majority. There is provision for
  56. -- rejecting noise where a start bit should have been. We compensate for
  57. -- small amounts of clock drift by potentially cutting a stop bit short.
  58. --
  59. -- This is not dissimilar to how the AVR USART receiver works.
  60. --
  61. data_out_ready <= rx_out_ready;
  62. bad_bit <= rx_badbit;
  63. data_out <= data_out_buf;
  64. rx_sample_majority <= (rx_sample1 and rx_sample2) or (rx_sample1 and rx_sample3) or (rx_sample2 and rx_sample3); -- simple majority wins
  65. receiver: process(clk)
  66. begin
  67. if rising_edge(clk) then
  68. -- Bring serial_in into our clock domain
  69. rx_clkin1 <= serial_in;
  70. rx_clkin2 <= rx_clkin1; -- rx_clkin2 should now be safe to use.
  71. -- We latch the incoming serial data at full clock speed (NOT divided down)
  72. rx_sample1 <= rx_clkin2;
  73. rx_out_ready <= '0';
  74. -- bad bit
  75. rx_badbit <= rx_badbit;
  76. -- clock divider
  77. rx_counter <= rx_counter + 1;
  78. if rx_counter = rx_sample_interval then
  79. rx_counter <= (others => '0');
  80. if rx_state = "00000000" then
  81. -- line is in the idle state, we're waiting for a start bit!
  82. -- the anticipation is killing me.
  83. if rx_sample1 = '0' then
  84. rx_state <= "00000001"; -- and we're off!
  85. rx_counter <= (others => '0');
  86. end if;
  87. elsif rx_state = "10011010" then
  88. -- wait for the line to be idle. we don't leave this state until the serial line
  89. -- goes high (it should be already, because we should be in mid stop bit).
  90. if rx_sample1 = '1' then
  91. rx_state <= "00000000";
  92. end if;
  93. else
  94. -- we're in the normal bit reception pattern
  95. rx_state <= rx_state + 1;
  96. -- rx_sample1 contains the incoming serial data, latched
  97. rx_sample3 <= rx_sample2;
  98. rx_sample2 <= rx_sample1;
  99. -- when we have the three middle samples, update the shift register
  100. if rx_state(3 downto 0) = "1001" then
  101. rx_shift_reg <= rx_sample_majority & rx_shift_reg(rx_shift_reg'length-1 downto 1);
  102. -- false start bit noise rejection: if we read the start bit as a logical 1, start over again.
  103. if (rx_state(7 downto 4) = "0000") and (rx_sample_majority = '1') then
  104. rx_badbit <= '1';
  105. rx_state <= "00000000";
  106. end if;
  107. -- check stop bit framing and alert CPU if valid byte received
  108. if (rx_state(7 downto 4) = "1001") then
  109. if (rx_sample_majority = '1') then
  110. data_out_buf <= rx_shift_reg(8 downto 1);
  111. rx_out_ready <= '1';
  112. rx_badbit <= '0';
  113. else
  114. rx_badbit <= '1';
  115. end if;
  116. -- if line is high we can skip waiting for the line to go idle which buys us a little more tolerance for clock drift.
  117. if rx_sample1 = '1' then
  118. rx_state <= "00000000";
  119. end if;
  120. end if;
  121. end if;
  122. end if;
  123. end if;
  124. end if;
  125. end process;
  126. -- -- transmitter -- --
  127. --
  128. -- just clock out the bits, damn it.
  129. --
  130. serial_out <= tx_shift_reg(0); -- we always output the bottom bit of the shift register.
  131. transmitter_busy <= tx_busy; -- or data_in_load;
  132. transmitter: process(clk)
  133. begin
  134. if rising_edge(clk) then
  135. tx_busy <= '1';
  136. if tx_bits_left = 0 then
  137. -- idle
  138. if data_in_load = '1' then
  139. tx_shift_reg <= data_in & '0'; -- data bits, start bit
  140. tx_bits_left <= to_unsigned(10, 4); -- total ten bits to transmit including stop bit
  141. tx_counter <= (others => '0'); -- reset counter
  142. else
  143. if can_transmit = '0' then
  144. tx_busy <= '1';
  145. else
  146. tx_busy <= '0';
  147. end if;
  148. end if;
  149. else
  150. -- busy
  151. if (tx_counter = 0) and (tx_bits_left = 10) and (can_transmit = '0') then
  152. -- do nothing, we're waiting for our peer to indicate that we can transmit
  153. tx_counter <= (others => '0');
  154. else
  155. tx_counter <= tx_counter + 1;
  156. if tx_counter = bit_duration then
  157. -- shift out the next bit
  158. tx_shift_reg <= '1' & tx_shift_reg(8 downto 1); -- stop bit and line idle state are both 1 so shift that in the top
  159. tx_counter <= (others => '0'); -- reset counter
  160. tx_bits_left <= tx_bits_left - 1;
  161. end if;
  162. end if;
  163. end if;
  164. end if;
  165. end process;
  166. end Behavioral;