Z80cpu.vhd 3.3 KB

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  1. --+-----------------------------------+-------------------------------------+--
  2. --| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
  3. --| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
  4. --| / __|/ _ \ / __|_ / _ \| | | | | |--
  5. --| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
  6. --| |___/\___/ \___/___\___/ \___/ | |--
  7. --| | http://sowerbutts.com/ |--
  8. --+-----------------------------------+-------------------------------------+--
  9. --| Wrap the T80 CPU core and produce more easily comprehended signals |--
  10. --+-------------------------------------------------------------------------+--
  11. library IEEE;
  12. use IEEE.std_logic_1164.all;
  13. use IEEE.numeric_std.all;
  14. use work.T80_Pack.all;
  15. entity Z80cpu is
  16. port (
  17. -- reset
  18. reset : in std_logic;
  19. -- clocking
  20. clk : in std_logic;
  21. clk_enable : in std_logic;
  22. -- indicates when we're in the M1 cycle (start of an instruction)
  23. m1_cycle : out std_logic;
  24. -- memory and I/O interface
  25. req_mem : out std_logic; -- memory request?
  26. req_io : out std_logic; -- i/o request?
  27. req_read : out std_logic; -- read?
  28. req_write : out std_logic; -- write?
  29. mem_wait : in std_logic; -- memory or i/o can force the CPU to wait
  30. address : out std_logic_vector(15 downto 0);
  31. data_in : in std_logic_vector(7 downto 0);
  32. data_out : out std_logic_vector(7 downto 0);
  33. -- interrupts
  34. interrupt : in std_logic;
  35. nmi : in std_logic
  36. );
  37. end Z80cpu;
  38. architecture behavioural of Z80cpu is
  39. signal RESET_n : std_logic;
  40. signal WAIT_n : std_logic;
  41. signal INT_n : std_logic;
  42. signal NMI_n : std_logic;
  43. signal M1_n : std_logic;
  44. signal MREQ_n : std_logic;
  45. signal IORQ_n : std_logic;
  46. signal RFSH_n : std_logic;
  47. signal RD_n : std_logic;
  48. signal WR_n : std_logic;
  49. begin
  50. RESET_n <= not reset;
  51. WAIT_n <= not mem_wait;
  52. INT_n <= not interrupt;
  53. NMI_n <= not nmi;
  54. m1_cycle <= not M1_n;
  55. req_mem <= (not MREQ_n) and (RFSH_n);
  56. req_io <= (not IORQ_n) and (M1_n); -- IORQ is active during M1 when handling interrupts (it's well documented, but I found out the hard way...)
  57. req_read <= (not RD_n) and (RFSH_n);
  58. req_write <= (not WR_n);
  59. cpu : entity work.T80se
  60. generic map (
  61. Mode => 1, -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
  62. T2Write => 1, -- 0 => WR_n active in T3, /=0 => WR_n active in T2
  63. IOWait => 0 -- 0 => single cycle I/O, 1 => standard I/O cycle
  64. )
  65. port map (
  66. RESET_n => RESET_n,
  67. CLK_n => clk,
  68. CLKEN => clk_enable,
  69. WAIT_n => WAIT_n,
  70. INT_n => INT_n,
  71. NMI_n => NMI_n,
  72. BUSRQ_n => '1',
  73. BUSAK_n => open,
  74. M1_n => M1_n,
  75. MREQ_n => MREQ_n,
  76. IORQ_n => IORQ_n,
  77. RD_n => RD_n,
  78. WR_n => WR_n,
  79. RFSH_n => RFSH_n,
  80. HALT_n => open,
  81. A => address,
  82. DI => data_in,
  83. DO => data_out
  84. );
  85. end;