T80se.vhd 5.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192
  1. -- ****
  2. -- T80(b) core. In an effort to merge and maintain bug fixes ....
  3. --
  4. --
  5. -- Ver 300 started tidyup
  6. -- MikeJ March 2005
  7. -- Latest version from www.fpgaarcade.com (original www.opencores.org)
  8. --
  9. -- ****
  10. --
  11. -- Z80 compatible microprocessor core, synchronous top level with clock enable
  12. -- Different timing than the original z80
  13. -- Inputs needs to be synchronous and outputs may glitch
  14. --
  15. -- Version : 0240
  16. --
  17. -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
  18. --
  19. -- All rights reserved
  20. --
  21. -- Redistribution and use in source and synthezised forms, with or without
  22. -- modification, are permitted provided that the following conditions are met:
  23. --
  24. -- Redistributions of source code must retain the above copyright notice,
  25. -- this list of conditions and the following disclaimer.
  26. --
  27. -- Redistributions in synthesized form must reproduce the above copyright
  28. -- notice, this list of conditions and the following disclaimer in the
  29. -- documentation and/or other materials provided with the distribution.
  30. --
  31. -- Neither the name of the author nor the names of other contributors may
  32. -- be used to endorse or promote products derived from this software without
  33. -- specific prior written permission.
  34. --
  35. -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  36. -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  37. -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  38. -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
  39. -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  40. -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  41. -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  42. -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  43. -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  44. -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  45. -- POSSIBILITY OF SUCH DAMAGE.
  46. --
  47. -- Please report bugs to the author, but before you do so, please
  48. -- make sure that this is not a derivative work and that
  49. -- you have the latest version of this file.
  50. --
  51. -- The latest version of this file can be found at:
  52. -- http://www.opencores.org/cvsweb.shtml/t80/
  53. --
  54. -- Limitations :
  55. --
  56. -- File history :
  57. --
  58. -- 0235 : First release
  59. --
  60. -- 0236 : Added T2Write generic
  61. --
  62. -- 0237 : Fixed T2Write with wait state
  63. --
  64. -- 0238 : Updated for T80 interface change
  65. --
  66. -- 0240 : Updated for T80 interface change
  67. --
  68. -- 0242 : Updated for T80 interface change
  69. --
  70. library IEEE;
  71. use IEEE.std_logic_1164.all;
  72. use IEEE.numeric_std.all;
  73. use work.T80_Pack.all;
  74. entity T80se is
  75. generic(
  76. Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
  77. T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
  78. IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
  79. );
  80. port(
  81. RESET_n : in std_logic;
  82. CLK_n : in std_logic;
  83. CLKEN : in std_logic;
  84. WAIT_n : in std_logic;
  85. INT_n : in std_logic;
  86. NMI_n : in std_logic;
  87. BUSRQ_n : in std_logic;
  88. M1_n : out std_logic;
  89. MREQ_n : out std_logic;
  90. IORQ_n : out std_logic;
  91. RD_n : out std_logic;
  92. WR_n : out std_logic;
  93. RFSH_n : out std_logic;
  94. HALT_n : out std_logic;
  95. BUSAK_n : out std_logic;
  96. A : out std_logic_vector(15 downto 0);
  97. DI : in std_logic_vector(7 downto 0);
  98. DO : out std_logic_vector(7 downto 0)
  99. );
  100. end T80se;
  101. architecture rtl of T80se is
  102. signal IntCycle_n : std_logic;
  103. signal NoRead : std_logic;
  104. signal Write : std_logic;
  105. signal IORQ : std_logic;
  106. signal DI_Reg : std_logic_vector(7 downto 0);
  107. signal MCycle : std_logic_vector(2 downto 0);
  108. signal TState : std_logic_vector(2 downto 0);
  109. begin
  110. u0 : T80
  111. generic map(
  112. Mode => Mode,
  113. IOWait => IOWait)
  114. port map(
  115. CEN => CLKEN,
  116. M1_n => M1_n,
  117. IORQ => IORQ,
  118. NoRead => NoRead,
  119. Write => Write,
  120. RFSH_n => RFSH_n,
  121. HALT_n => HALT_n,
  122. WAIT_n => Wait_n,
  123. INT_n => INT_n,
  124. NMI_n => NMI_n,
  125. RESET_n => RESET_n,
  126. BUSRQ_n => BUSRQ_n,
  127. BUSAK_n => BUSAK_n,
  128. CLK_n => CLK_n,
  129. A => A,
  130. DInst => DI,
  131. DI => DI_Reg,
  132. DO => DO,
  133. MC => MCycle,
  134. TS => TState,
  135. IntCycle_n => IntCycle_n);
  136. process (RESET_n, CLK_n)
  137. begin
  138. if RESET_n = '0' then
  139. RD_n <= '1';
  140. WR_n <= '1';
  141. IORQ_n <= '1';
  142. MREQ_n <= '1';
  143. DI_Reg <= "00000000";
  144. elsif CLK_n'event and CLK_n = '1' then
  145. if CLKEN = '1' then
  146. RD_n <= '1';
  147. WR_n <= '1';
  148. IORQ_n <= '1';
  149. MREQ_n <= '1';
  150. if MCycle = "001" then
  151. if TState = "001" or (TState = "010" and Wait_n = '0') then
  152. RD_n <= not IntCycle_n;
  153. MREQ_n <= not IntCycle_n;
  154. IORQ_n <= IntCycle_n;
  155. end if;
  156. if TState = "011" then
  157. MREQ_n <= '0';
  158. end if;
  159. else
  160. if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
  161. RD_n <= '0';
  162. IORQ_n <= not IORQ;
  163. MREQ_n <= IORQ;
  164. end if;
  165. if T2Write = 0 then
  166. if TState = "010" and Write = '1' then
  167. WR_n <= '0';
  168. IORQ_n <= not IORQ;
  169. MREQ_n <= IORQ;
  170. end if;
  171. else
  172. if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
  173. WR_n <= '0';
  174. IORQ_n <= not IORQ;
  175. MREQ_n <= IORQ;
  176. end if;
  177. end if;
  178. end if;
  179. if TState = "010" and Wait_n = '1' then
  180. DI_Reg <= DI;
  181. end if;
  182. end if;
  183. end if;
  184. end process;
  185. end;