T80_MCode.vhd 53 KB

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  1. -- ****
  2. -- T80(b) core. In an effort to merge and maintain bug fixes ....
  3. --
  4. --
  5. -- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
  6. -- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
  7. -- Ver 300 started tidyup
  8. -- MikeJ March 2005
  9. -- Latest version from www.fpgaarcade.com (original www.opencores.org)
  10. --
  11. -- ****
  12. --
  13. -- Z80 compatible microprocessor core
  14. --
  15. -- Version : 0242
  16. --
  17. -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
  18. --
  19. -- All rights reserved
  20. --
  21. -- Redistribution and use in source and synthezised forms, with or without
  22. -- modification, are permitted provided that the following conditions are met:
  23. --
  24. -- Redistributions of source code must retain the above copyright notice,
  25. -- this list of conditions and the following disclaimer.
  26. --
  27. -- Redistributions in synthesized form must reproduce the above copyright
  28. -- notice, this list of conditions and the following disclaimer in the
  29. -- documentation and/or other materials provided with the distribution.
  30. --
  31. -- Neither the name of the author nor the names of other contributors may
  32. -- be used to endorse or promote products derived from this software without
  33. -- specific prior written permission.
  34. --
  35. -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  36. -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  37. -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  38. -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
  39. -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  40. -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  41. -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  42. -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  43. -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  44. -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  45. -- POSSIBILITY OF SUCH DAMAGE.
  46. --
  47. -- Please report bugs to the author, but before you do so, please
  48. -- make sure that this is not a derivative work and that
  49. -- you have the latest version of this file.
  50. --
  51. -- The latest version of this file can be found at:
  52. -- http://www.opencores.org/cvsweb.shtml/t80/
  53. --
  54. -- Limitations :
  55. --
  56. -- File history :
  57. --
  58. -- 0208 : First complete release
  59. --
  60. -- 0211 : Fixed IM 1
  61. --
  62. -- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
  63. --
  64. -- 0235 : Added IM 2 fix by Mike Johnson
  65. --
  66. -- 0238 : Added NoRead signal
  67. --
  68. -- 0238b: Fixed instruction timing for POP and DJNZ
  69. --
  70. -- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
  71. -- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
  72. --
  73. -- 0242 : Fixed I/O instruction timing, cleanup
  74. --
  75. library IEEE;
  76. use IEEE.std_logic_1164.all;
  77. use IEEE.numeric_std.all;
  78. use work.T80_Pack.all;
  79. entity T80_MCode is
  80. generic(
  81. Mode : integer := 0;
  82. Flag_C : integer := 0;
  83. Flag_N : integer := 1;
  84. Flag_P : integer := 2;
  85. Flag_X : integer := 3;
  86. Flag_H : integer := 4;
  87. Flag_Y : integer := 5;
  88. Flag_Z : integer := 6;
  89. Flag_S : integer := 7
  90. );
  91. port(
  92. IR : in std_logic_vector(7 downto 0);
  93. ISet : in std_logic_vector(1 downto 0);
  94. MCycle : in std_logic_vector(2 downto 0);
  95. F : in std_logic_vector(7 downto 0);
  96. NMICycle : in std_logic;
  97. IntCycle : in std_logic;
  98. XY_State : in std_logic_vector(1 downto 0);
  99. MCycles : out std_logic_vector(2 downto 0);
  100. TStates : out std_logic_vector(2 downto 0);
  101. Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
  102. Inc_PC : out std_logic;
  103. Inc_WZ : out std_logic;
  104. IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
  105. Read_To_Reg : out std_logic;
  106. Read_To_Acc : out std_logic;
  107. Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
  108. Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
  109. ALU_Op : out std_logic_vector(3 downto 0);
  110. -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
  111. Save_ALU : out std_logic;
  112. PreserveC : out std_logic;
  113. Arith16 : out std_logic;
  114. Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
  115. IORQ : out std_logic;
  116. Jump : out std_logic;
  117. JumpE : out std_logic;
  118. JumpXY : out std_logic;
  119. Call : out std_logic;
  120. RstP : out std_logic;
  121. LDZ : out std_logic;
  122. LDW : out std_logic;
  123. LDSPHL : out std_logic;
  124. Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
  125. ExchangeDH : out std_logic;
  126. ExchangeRp : out std_logic;
  127. ExchangeAF : out std_logic;
  128. ExchangeRS : out std_logic;
  129. I_DJNZ : out std_logic;
  130. I_CPL : out std_logic;
  131. I_CCF : out std_logic;
  132. I_SCF : out std_logic;
  133. I_RETN : out std_logic;
  134. I_BT : out std_logic;
  135. I_BC : out std_logic;
  136. I_BTR : out std_logic;
  137. I_RLD : out std_logic;
  138. I_RRD : out std_logic;
  139. I_INRC : out std_logic;
  140. SetDI : out std_logic;
  141. SetEI : out std_logic;
  142. IMode : out std_logic_vector(1 downto 0);
  143. Halt : out std_logic;
  144. NoRead : out std_logic;
  145. Write : out std_logic;
  146. XYbit_undoc : out std_logic
  147. );
  148. end T80_MCode;
  149. architecture rtl of T80_MCode is
  150. constant aNone : std_logic_vector(2 downto 0) := "111";
  151. constant aBC : std_logic_vector(2 downto 0) := "000";
  152. constant aDE : std_logic_vector(2 downto 0) := "001";
  153. constant aXY : std_logic_vector(2 downto 0) := "010";
  154. constant aIOA : std_logic_vector(2 downto 0) := "100";
  155. constant aSP : std_logic_vector(2 downto 0) := "101";
  156. constant aZI : std_logic_vector(2 downto 0) := "110";
  157. function is_cc_true(
  158. F : std_logic_vector(7 downto 0);
  159. cc : bit_vector(2 downto 0)
  160. ) return boolean is
  161. begin
  162. if Mode = 3 then
  163. case cc is
  164. when "000" => return F(7) = '0'; -- NZ
  165. when "001" => return F(7) = '1'; -- Z
  166. when "010" => return F(4) = '0'; -- NC
  167. when "011" => return F(4) = '1'; -- C
  168. when "100" => return false;
  169. when "101" => return false;
  170. when "110" => return false;
  171. when "111" => return false;
  172. end case;
  173. else
  174. case cc is
  175. when "000" => return F(6) = '0'; -- NZ
  176. when "001" => return F(6) = '1'; -- Z
  177. when "010" => return F(0) = '0'; -- NC
  178. when "011" => return F(0) = '1'; -- C
  179. when "100" => return F(2) = '0'; -- PO
  180. when "101" => return F(2) = '1'; -- PE
  181. when "110" => return F(7) = '0'; -- P
  182. when "111" => return F(7) = '1'; -- M
  183. end case;
  184. end if;
  185. end;
  186. begin
  187. process (IR, ISet, MCycle, F, NMICycle, IntCycle)
  188. variable DDD : std_logic_vector(2 downto 0);
  189. variable SSS : std_logic_vector(2 downto 0);
  190. variable DPair : std_logic_vector(1 downto 0);
  191. variable IRB : bit_vector(7 downto 0);
  192. begin
  193. DDD := IR(5 downto 3);
  194. SSS := IR(2 downto 0);
  195. DPair := IR(5 downto 4);
  196. IRB := to_bitvector(IR);
  197. MCycles <= "001";
  198. if MCycle = "001" then
  199. TStates <= "100";
  200. else
  201. TStates <= "011";
  202. end if;
  203. Prefix <= "00";
  204. Inc_PC <= '0';
  205. Inc_WZ <= '0';
  206. IncDec_16 <= "0000";
  207. Read_To_Acc <= '0';
  208. Read_To_Reg <= '0';
  209. Set_BusB_To <= "0000";
  210. Set_BusA_To <= "0000";
  211. ALU_Op <= "0" & IR(5 downto 3);
  212. Save_ALU <= '0';
  213. PreserveC <= '0';
  214. Arith16 <= '0';
  215. IORQ <= '0';
  216. Set_Addr_To <= aNone;
  217. Jump <= '0';
  218. JumpE <= '0';
  219. JumpXY <= '0';
  220. Call <= '0';
  221. RstP <= '0';
  222. LDZ <= '0';
  223. LDW <= '0';
  224. LDSPHL <= '0';
  225. Special_LD <= "000";
  226. ExchangeDH <= '0';
  227. ExchangeRp <= '0';
  228. ExchangeAF <= '0';
  229. ExchangeRS <= '0';
  230. I_DJNZ <= '0';
  231. I_CPL <= '0';
  232. I_CCF <= '0';
  233. I_SCF <= '0';
  234. I_RETN <= '0';
  235. I_BT <= '0';
  236. I_BC <= '0';
  237. I_BTR <= '0';
  238. I_RLD <= '0';
  239. I_RRD <= '0';
  240. I_INRC <= '0';
  241. SetDI <= '0';
  242. SetEI <= '0';
  243. IMode <= "11";
  244. Halt <= '0';
  245. NoRead <= '0';
  246. Write <= '0';
  247. XYbit_undoc <= '0';
  248. case ISet is
  249. when "00" =>
  250. ------------------------------------------------------------------------------
  251. --
  252. -- Unprefixed instructions
  253. --
  254. ------------------------------------------------------------------------------
  255. case IRB is
  256. -- 8 BIT LOAD GROUP
  257. when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
  258. |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
  259. |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
  260. |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
  261. |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
  262. |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
  263. |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
  264. -- LD r,r'
  265. Set_BusB_To(2 downto 0) <= SSS;
  266. ExchangeRp <= '1';
  267. Set_BusA_To(2 downto 0) <= DDD;
  268. Read_To_Reg <= '1';
  269. when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
  270. -- LD r,n
  271. MCycles <= "010";
  272. case to_integer(unsigned(MCycle)) is
  273. when 2 =>
  274. Inc_PC <= '1';
  275. Set_BusA_To(2 downto 0) <= DDD;
  276. Read_To_Reg <= '1';
  277. when others => null;
  278. end case;
  279. when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
  280. -- LD r,(HL)
  281. MCycles <= "010";
  282. case to_integer(unsigned(MCycle)) is
  283. when 1 =>
  284. Set_Addr_To <= aXY;
  285. when 2 =>
  286. Set_BusA_To(2 downto 0) <= DDD;
  287. Read_To_Reg <= '1';
  288. when others => null;
  289. end case;
  290. when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
  291. -- LD (HL),r
  292. MCycles <= "010";
  293. case to_integer(unsigned(MCycle)) is
  294. when 1 =>
  295. Set_Addr_To <= aXY;
  296. Set_BusB_To(2 downto 0) <= SSS;
  297. Set_BusB_To(3) <= '0';
  298. when 2 =>
  299. Write <= '1';
  300. when others => null;
  301. end case;
  302. when "00110110" =>
  303. -- LD (HL),n
  304. MCycles <= "011";
  305. case to_integer(unsigned(MCycle)) is
  306. when 2 =>
  307. Inc_PC <= '1';
  308. Set_Addr_To <= aXY;
  309. Set_BusB_To(2 downto 0) <= SSS;
  310. Set_BusB_To(3) <= '0';
  311. when 3 =>
  312. Write <= '1';
  313. when others => null;
  314. end case;
  315. when "00001010" =>
  316. -- LD A,(BC)
  317. MCycles <= "010";
  318. case to_integer(unsigned(MCycle)) is
  319. when 1 =>
  320. Set_Addr_To <= aBC;
  321. when 2 =>
  322. Read_To_Acc <= '1';
  323. when others => null;
  324. end case;
  325. when "00011010" =>
  326. -- LD A,(DE)
  327. MCycles <= "010";
  328. case to_integer(unsigned(MCycle)) is
  329. when 1 =>
  330. Set_Addr_To <= aDE;
  331. when 2 =>
  332. Read_To_Acc <= '1';
  333. when others => null;
  334. end case;
  335. when "00111010" =>
  336. if Mode = 3 then
  337. -- LDD A,(HL)
  338. MCycles <= "010";
  339. case to_integer(unsigned(MCycle)) is
  340. when 1 =>
  341. Set_Addr_To <= aXY;
  342. when 2 =>
  343. Read_To_Acc <= '1';
  344. IncDec_16 <= "1110";
  345. when others => null;
  346. end case;
  347. else
  348. -- LD A,(nn)
  349. MCycles <= "100";
  350. case to_integer(unsigned(MCycle)) is
  351. when 2 =>
  352. Inc_PC <= '1';
  353. LDZ <= '1';
  354. when 3 =>
  355. Set_Addr_To <= aZI;
  356. Inc_PC <= '1';
  357. when 4 =>
  358. Read_To_Acc <= '1';
  359. when others => null;
  360. end case;
  361. end if;
  362. when "00000010" =>
  363. -- LD (BC),A
  364. MCycles <= "010";
  365. case to_integer(unsigned(MCycle)) is
  366. when 1 =>
  367. Set_Addr_To <= aBC;
  368. Set_BusB_To <= "0111";
  369. when 2 =>
  370. Write <= '1';
  371. when others => null;
  372. end case;
  373. when "00010010" =>
  374. -- LD (DE),A
  375. MCycles <= "010";
  376. case to_integer(unsigned(MCycle)) is
  377. when 1 =>
  378. Set_Addr_To <= aDE;
  379. Set_BusB_To <= "0111";
  380. when 2 =>
  381. Write <= '1';
  382. when others => null;
  383. end case;
  384. when "00110010" =>
  385. if Mode = 3 then
  386. -- LDD (HL),A
  387. MCycles <= "010";
  388. case to_integer(unsigned(MCycle)) is
  389. when 1 =>
  390. Set_Addr_To <= aXY;
  391. Set_BusB_To <= "0111";
  392. when 2 =>
  393. Write <= '1';
  394. IncDec_16 <= "1110";
  395. when others => null;
  396. end case;
  397. else
  398. -- LD (nn),A
  399. MCycles <= "100";
  400. case to_integer(unsigned(MCycle)) is
  401. when 2 =>
  402. Inc_PC <= '1';
  403. LDZ <= '1';
  404. when 3 =>
  405. Set_Addr_To <= aZI;
  406. Inc_PC <= '1';
  407. Set_BusB_To <= "0111";
  408. when 4 =>
  409. Write <= '1';
  410. when others => null;
  411. end case;
  412. end if;
  413. -- 16 BIT LOAD GROUP
  414. when "00000001"|"00010001"|"00100001"|"00110001" =>
  415. -- LD dd,nn
  416. MCycles <= "011";
  417. case to_integer(unsigned(MCycle)) is
  418. when 2 =>
  419. Inc_PC <= '1';
  420. Read_To_Reg <= '1';
  421. if DPAIR = "11" then
  422. Set_BusA_To(3 downto 0) <= "1000";
  423. else
  424. Set_BusA_To(2 downto 1) <= DPAIR;
  425. Set_BusA_To(0) <= '1';
  426. end if;
  427. when 3 =>
  428. Inc_PC <= '1';
  429. Read_To_Reg <= '1';
  430. if DPAIR = "11" then
  431. Set_BusA_To(3 downto 0) <= "1001";
  432. else
  433. Set_BusA_To(2 downto 1) <= DPAIR;
  434. Set_BusA_To(0) <= '0';
  435. end if;
  436. when others => null;
  437. end case;
  438. when "00101010" =>
  439. if Mode = 3 then
  440. -- LDI A,(HL)
  441. MCycles <= "010";
  442. case to_integer(unsigned(MCycle)) is
  443. when 1 =>
  444. Set_Addr_To <= aXY;
  445. when 2 =>
  446. Read_To_Acc <= '1';
  447. IncDec_16 <= "0110";
  448. when others => null;
  449. end case;
  450. else
  451. -- LD HL,(nn)
  452. MCycles <= "101";
  453. case to_integer(unsigned(MCycle)) is
  454. when 2 =>
  455. Inc_PC <= '1';
  456. LDZ <= '1';
  457. when 3 =>
  458. Set_Addr_To <= aZI;
  459. Inc_PC <= '1';
  460. LDW <= '1';
  461. when 4 =>
  462. Set_BusA_To(2 downto 0) <= "101"; -- L
  463. Read_To_Reg <= '1';
  464. Inc_WZ <= '1';
  465. Set_Addr_To <= aZI;
  466. when 5 =>
  467. Set_BusA_To(2 downto 0) <= "100"; -- H
  468. Read_To_Reg <= '1';
  469. when others => null;
  470. end case;
  471. end if;
  472. when "00100010" =>
  473. if Mode = 3 then
  474. -- LDI (HL),A
  475. MCycles <= "010";
  476. case to_integer(unsigned(MCycle)) is
  477. when 1 =>
  478. Set_Addr_To <= aXY;
  479. Set_BusB_To <= "0111";
  480. when 2 =>
  481. Write <= '1';
  482. IncDec_16 <= "0110";
  483. when others => null;
  484. end case;
  485. else
  486. -- LD (nn),HL
  487. MCycles <= "101";
  488. case to_integer(unsigned(MCycle)) is
  489. when 2 =>
  490. Inc_PC <= '1';
  491. LDZ <= '1';
  492. when 3 =>
  493. Set_Addr_To <= aZI;
  494. Inc_PC <= '1';
  495. LDW <= '1';
  496. Set_BusB_To <= "0101"; -- L
  497. when 4 =>
  498. Inc_WZ <= '1';
  499. Set_Addr_To <= aZI;
  500. Write <= '1';
  501. Set_BusB_To <= "0100"; -- H
  502. when 5 =>
  503. Write <= '1';
  504. when others => null;
  505. end case;
  506. end if;
  507. when "11111001" =>
  508. -- LD SP,HL
  509. TStates <= "110";
  510. LDSPHL <= '1';
  511. when "11000101"|"11010101"|"11100101"|"11110101" =>
  512. -- PUSH qq
  513. MCycles <= "011";
  514. case to_integer(unsigned(MCycle)) is
  515. when 1 =>
  516. TStates <= "101";
  517. IncDec_16 <= "1111";
  518. Set_Addr_TO <= aSP;
  519. if DPAIR = "11" then
  520. Set_BusB_To <= "0111";
  521. else
  522. Set_BusB_To(2 downto 1) <= DPAIR;
  523. Set_BusB_To(0) <= '0';
  524. Set_BusB_To(3) <= '0';
  525. end if;
  526. when 2 =>
  527. IncDec_16 <= "1111";
  528. Set_Addr_To <= aSP;
  529. if DPAIR = "11" then
  530. Set_BusB_To <= "1011";
  531. else
  532. Set_BusB_To(2 downto 1) <= DPAIR;
  533. Set_BusB_To(0) <= '1';
  534. Set_BusB_To(3) <= '0';
  535. end if;
  536. Write <= '1';
  537. when 3 =>
  538. Write <= '1';
  539. when others => null;
  540. end case;
  541. when "11000001"|"11010001"|"11100001"|"11110001" =>
  542. -- POP qq
  543. MCycles <= "011";
  544. case to_integer(unsigned(MCycle)) is
  545. when 1 =>
  546. Set_Addr_To <= aSP;
  547. when 2 =>
  548. IncDec_16 <= "0111";
  549. Set_Addr_To <= aSP;
  550. Read_To_Reg <= '1';
  551. if DPAIR = "11" then
  552. Set_BusA_To(3 downto 0) <= "1011";
  553. else
  554. Set_BusA_To(2 downto 1) <= DPAIR;
  555. Set_BusA_To(0) <= '1';
  556. end if;
  557. when 3 =>
  558. IncDec_16 <= "0111";
  559. Read_To_Reg <= '1';
  560. if DPAIR = "11" then
  561. Set_BusA_To(3 downto 0) <= "0111";
  562. else
  563. Set_BusA_To(2 downto 1) <= DPAIR;
  564. Set_BusA_To(0) <= '0';
  565. end if;
  566. when others => null;
  567. end case;
  568. -- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
  569. when "11101011" =>
  570. if Mode /= 3 then
  571. -- EX DE,HL
  572. ExchangeDH <= '1';
  573. end if;
  574. when "00001000" =>
  575. if Mode = 3 then
  576. -- LD (nn),SP
  577. MCycles <= "101";
  578. case to_integer(unsigned(MCycle)) is
  579. when 2 =>
  580. Inc_PC <= '1';
  581. LDZ <= '1';
  582. when 3 =>
  583. Set_Addr_To <= aZI;
  584. Inc_PC <= '1';
  585. LDW <= '1';
  586. Set_BusB_To <= "1000";
  587. when 4 =>
  588. Inc_WZ <= '1';
  589. Set_Addr_To <= aZI;
  590. Write <= '1';
  591. Set_BusB_To <= "1001";
  592. when 5 =>
  593. Write <= '1';
  594. when others => null;
  595. end case;
  596. elsif Mode < 2 then
  597. -- EX AF,AF'
  598. ExchangeAF <= '1';
  599. end if;
  600. when "11011001" =>
  601. if Mode = 3 then
  602. -- RETI
  603. MCycles <= "011";
  604. case to_integer(unsigned(MCycle)) is
  605. when 1 =>
  606. Set_Addr_TO <= aSP;
  607. when 2 =>
  608. IncDec_16 <= "0111";
  609. Set_Addr_To <= aSP;
  610. LDZ <= '1';
  611. when 3 =>
  612. Jump <= '1';
  613. IncDec_16 <= "0111";
  614. I_RETN <= '1';
  615. SetEI <= '1';
  616. when others => null;
  617. end case;
  618. elsif Mode < 2 then
  619. -- EXX
  620. ExchangeRS <= '1';
  621. end if;
  622. when "11100011" =>
  623. if Mode /= 3 then
  624. -- EX (SP),HL
  625. MCycles <= "101";
  626. case to_integer(unsigned(MCycle)) is
  627. when 1 =>
  628. Set_Addr_To <= aSP;
  629. when 2 =>
  630. Read_To_Reg <= '1';
  631. Set_BusA_To <= "0101";
  632. Set_BusB_To <= "0101";
  633. Set_Addr_To <= aSP;
  634. when 3 =>
  635. IncDec_16 <= "0111";
  636. Set_Addr_To <= aSP;
  637. TStates <= "100";
  638. Write <= '1';
  639. when 4 =>
  640. Read_To_Reg <= '1';
  641. Set_BusA_To <= "0100";
  642. Set_BusB_To <= "0100";
  643. Set_Addr_To <= aSP;
  644. when 5 =>
  645. IncDec_16 <= "1111";
  646. TStates <= "101";
  647. Write <= '1';
  648. when others => null;
  649. end case;
  650. end if;
  651. -- 8 BIT ARITHMETIC AND LOGICAL GROUP
  652. when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
  653. |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
  654. |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
  655. |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
  656. |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
  657. |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
  658. |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
  659. |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
  660. -- ADD A,r
  661. -- ADC A,r
  662. -- SUB A,r
  663. -- SBC A,r
  664. -- AND A,r
  665. -- OR A,r
  666. -- XOR A,r
  667. -- CP A,r
  668. Set_BusB_To(2 downto 0) <= SSS;
  669. Set_BusA_To(2 downto 0) <= "111";
  670. Read_To_Reg <= '1';
  671. Save_ALU <= '1';
  672. when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
  673. -- ADD A,(HL)
  674. -- ADC A,(HL)
  675. -- SUB A,(HL)
  676. -- SBC A,(HL)
  677. -- AND A,(HL)
  678. -- OR A,(HL)
  679. -- XOR A,(HL)
  680. -- CP A,(HL)
  681. MCycles <= "010";
  682. case to_integer(unsigned(MCycle)) is
  683. when 1 =>
  684. Set_Addr_To <= aXY;
  685. when 2 =>
  686. Read_To_Reg <= '1';
  687. Save_ALU <= '1';
  688. Set_BusB_To(2 downto 0) <= SSS;
  689. Set_BusA_To(2 downto 0) <= "111";
  690. when others => null;
  691. end case;
  692. when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
  693. -- ADD A,n
  694. -- ADC A,n
  695. -- SUB A,n
  696. -- SBC A,n
  697. -- AND A,n
  698. -- OR A,n
  699. -- XOR A,n
  700. -- CP A,n
  701. MCycles <= "010";
  702. if MCycle = "010" then
  703. Inc_PC <= '1';
  704. Read_To_Reg <= '1';
  705. Save_ALU <= '1';
  706. Set_BusB_To(2 downto 0) <= SSS;
  707. Set_BusA_To(2 downto 0) <= "111";
  708. end if;
  709. when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
  710. -- INC r
  711. Set_BusB_To <= "1010";
  712. Set_BusA_To(2 downto 0) <= DDD;
  713. Read_To_Reg <= '1';
  714. Save_ALU <= '1';
  715. PreserveC <= '1';
  716. ALU_Op <= "0000";
  717. when "00110100" =>
  718. -- INC (HL)
  719. MCycles <= "011";
  720. case to_integer(unsigned(MCycle)) is
  721. when 1 =>
  722. Set_Addr_To <= aXY;
  723. when 2 =>
  724. TStates <= "100";
  725. Set_Addr_To <= aXY;
  726. Read_To_Reg <= '1';
  727. Save_ALU <= '1';
  728. PreserveC <= '1';
  729. ALU_Op <= "0000";
  730. Set_BusB_To <= "1010";
  731. Set_BusA_To(2 downto 0) <= DDD;
  732. when 3 =>
  733. Write <= '1';
  734. when others => null;
  735. end case;
  736. when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
  737. -- DEC r
  738. Set_BusB_To <= "1010";
  739. Set_BusA_To(2 downto 0) <= DDD;
  740. Read_To_Reg <= '1';
  741. Save_ALU <= '1';
  742. PreserveC <= '1';
  743. ALU_Op <= "0010";
  744. when "00110101" =>
  745. -- DEC (HL)
  746. MCycles <= "011";
  747. case to_integer(unsigned(MCycle)) is
  748. when 1 =>
  749. Set_Addr_To <= aXY;
  750. when 2 =>
  751. TStates <= "100";
  752. Set_Addr_To <= aXY;
  753. ALU_Op <= "0010";
  754. Read_To_Reg <= '1';
  755. Save_ALU <= '1';
  756. PreserveC <= '1';
  757. Set_BusB_To <= "1010";
  758. Set_BusA_To(2 downto 0) <= DDD;
  759. when 3 =>
  760. Write <= '1';
  761. when others => null;
  762. end case;
  763. -- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
  764. when "00100111" =>
  765. -- DAA
  766. Set_BusA_To(2 downto 0) <= "111";
  767. Read_To_Reg <= '1';
  768. ALU_Op <= "1100";
  769. Save_ALU <= '1';
  770. when "00101111" =>
  771. -- CPL
  772. I_CPL <= '1';
  773. when "00111111" =>
  774. -- CCF
  775. I_CCF <= '1';
  776. when "00110111" =>
  777. -- SCF
  778. I_SCF <= '1';
  779. when "00000000" =>
  780. if NMICycle = '1' then
  781. -- NMI
  782. MCycles <= "011";
  783. case to_integer(unsigned(MCycle)) is
  784. when 1 =>
  785. TStates <= "101";
  786. IncDec_16 <= "1111";
  787. Set_Addr_To <= aSP;
  788. Set_BusB_To <= "1101";
  789. when 2 =>
  790. TStates <= "100";
  791. Write <= '1';
  792. IncDec_16 <= "1111";
  793. Set_Addr_To <= aSP;
  794. Set_BusB_To <= "1100";
  795. when 3 =>
  796. TStates <= "100";
  797. Write <= '1';
  798. when others => null;
  799. end case;
  800. elsif IntCycle = '1' then
  801. -- INT (IM 2)
  802. MCycles <= "101";
  803. case to_integer(unsigned(MCycle)) is
  804. when 1 =>
  805. LDZ <= '1';
  806. TStates <= "101";
  807. IncDec_16 <= "1111";
  808. Set_Addr_To <= aSP;
  809. Set_BusB_To <= "1101";
  810. when 2 =>
  811. TStates <= "100";
  812. Write <= '1';
  813. IncDec_16 <= "1111";
  814. Set_Addr_To <= aSP;
  815. Set_BusB_To <= "1100";
  816. when 3 =>
  817. TStates <= "100";
  818. Write <= '1';
  819. when 4 =>
  820. Inc_PC <= '1';
  821. LDZ <= '1';
  822. when 5 =>
  823. Jump <= '1';
  824. when others => null;
  825. end case;
  826. else
  827. -- NOP
  828. end if;
  829. when "01110110" =>
  830. -- HALT
  831. Halt <= '1';
  832. when "11110011" =>
  833. -- DI
  834. SetDI <= '1';
  835. when "11111011" =>
  836. -- EI
  837. SetEI <= '1';
  838. -- 16 BIT ARITHMETIC GROUP
  839. when "00001001"|"00011001"|"00101001"|"00111001" =>
  840. -- ADD HL,ss
  841. MCycles <= "011";
  842. case to_integer(unsigned(MCycle)) is
  843. when 2 =>
  844. NoRead <= '1';
  845. ALU_Op <= "0000";
  846. Read_To_Reg <= '1';
  847. Save_ALU <= '1';
  848. Set_BusA_To(2 downto 0) <= "101";
  849. case to_integer(unsigned(IR(5 downto 4))) is
  850. when 0|1|2 =>
  851. Set_BusB_To(2 downto 1) <= IR(5 downto 4);
  852. Set_BusB_To(0) <= '1';
  853. when others =>
  854. Set_BusB_To <= "1000";
  855. end case;
  856. TStates <= "100";
  857. Arith16 <= '1';
  858. when 3 =>
  859. NoRead <= '1';
  860. Read_To_Reg <= '1';
  861. Save_ALU <= '1';
  862. ALU_Op <= "0001";
  863. Set_BusA_To(2 downto 0) <= "100";
  864. case to_integer(unsigned(IR(5 downto 4))) is
  865. when 0|1|2 =>
  866. Set_BusB_To(2 downto 1) <= IR(5 downto 4);
  867. when others =>
  868. Set_BusB_To <= "1001";
  869. end case;
  870. Arith16 <= '1';
  871. when others =>
  872. end case;
  873. when "00000011"|"00010011"|"00100011"|"00110011" =>
  874. -- INC ss
  875. TStates <= "110";
  876. IncDec_16(3 downto 2) <= "01";
  877. IncDec_16(1 downto 0) <= DPair;
  878. when "00001011"|"00011011"|"00101011"|"00111011" =>
  879. -- DEC ss
  880. TStates <= "110";
  881. IncDec_16(3 downto 2) <= "11";
  882. IncDec_16(1 downto 0) <= DPair;
  883. -- ROTATE AND SHIFT GROUP
  884. when "00000111"
  885. -- RLCA
  886. |"00010111"
  887. -- RLA
  888. |"00001111"
  889. -- RRCA
  890. |"00011111" =>
  891. -- RRA
  892. Set_BusA_To(2 downto 0) <= "111";
  893. ALU_Op <= "1000";
  894. Read_To_Reg <= '1';
  895. Save_ALU <= '1';
  896. -- JUMP GROUP
  897. when "11000011" =>
  898. -- JP nn
  899. MCycles <= "011";
  900. case to_integer(unsigned(MCycle)) is
  901. when 2 =>
  902. Inc_PC <= '1';
  903. LDZ <= '1';
  904. when 3 =>
  905. Inc_PC <= '1';
  906. Jump <= '1';
  907. when others => null;
  908. end case;
  909. when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
  910. if IR(5) = '1' and Mode = 3 then
  911. case IRB(4 downto 3) is
  912. when "00" =>
  913. -- LD ($FF00+C),A
  914. MCycles <= "010";
  915. case to_integer(unsigned(MCycle)) is
  916. when 1 =>
  917. Set_Addr_To <= aBC;
  918. Set_BusB_To <= "0111";
  919. when 2 =>
  920. Write <= '1';
  921. IORQ <= '1';
  922. when others =>
  923. end case;
  924. when "01" =>
  925. -- LD (nn),A
  926. MCycles <= "100";
  927. case to_integer(unsigned(MCycle)) is
  928. when 2 =>
  929. Inc_PC <= '1';
  930. LDZ <= '1';
  931. when 3 =>
  932. Set_Addr_To <= aZI;
  933. Inc_PC <= '1';
  934. Set_BusB_To <= "0111";
  935. when 4 =>
  936. Write <= '1';
  937. when others => null;
  938. end case;
  939. when "10" =>
  940. -- LD A,($FF00+C)
  941. MCycles <= "010";
  942. case to_integer(unsigned(MCycle)) is
  943. when 1 =>
  944. Set_Addr_To <= aBC;
  945. when 2 =>
  946. Read_To_Acc <= '1';
  947. IORQ <= '1';
  948. when others =>
  949. end case;
  950. when "11" =>
  951. -- LD A,(nn)
  952. MCycles <= "100";
  953. case to_integer(unsigned(MCycle)) is
  954. when 2 =>
  955. Inc_PC <= '1';
  956. LDZ <= '1';
  957. when 3 =>
  958. Set_Addr_To <= aZI;
  959. Inc_PC <= '1';
  960. when 4 =>
  961. Read_To_Acc <= '1';
  962. when others => null;
  963. end case;
  964. end case;
  965. else
  966. -- JP cc,nn
  967. MCycles <= "011";
  968. case to_integer(unsigned(MCycle)) is
  969. when 2 =>
  970. Inc_PC <= '1';
  971. LDZ <= '1';
  972. when 3 =>
  973. Inc_PC <= '1';
  974. if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
  975. Jump <= '1';
  976. end if;
  977. when others => null;
  978. end case;
  979. end if;
  980. when "00011000" =>
  981. if Mode /= 2 then
  982. -- JR e
  983. MCycles <= "011";
  984. case to_integer(unsigned(MCycle)) is
  985. when 2 =>
  986. Inc_PC <= '1';
  987. when 3 =>
  988. NoRead <= '1';
  989. JumpE <= '1';
  990. TStates <= "101";
  991. when others => null;
  992. end case;
  993. end if;
  994. when "00111000" =>
  995. if Mode /= 2 then
  996. -- JR C,e
  997. MCycles <= "011";
  998. case to_integer(unsigned(MCycle)) is
  999. when 2 =>
  1000. Inc_PC <= '1';
  1001. if F(Flag_C) = '0' then
  1002. MCycles <= "010";
  1003. end if;
  1004. when 3 =>
  1005. NoRead <= '1';
  1006. JumpE <= '1';
  1007. TStates <= "101";
  1008. when others => null;
  1009. end case;
  1010. end if;
  1011. when "00110000" =>
  1012. if Mode /= 2 then
  1013. -- JR NC,e
  1014. MCycles <= "011";
  1015. case to_integer(unsigned(MCycle)) is
  1016. when 2 =>
  1017. Inc_PC <= '1';
  1018. if F(Flag_C) = '1' then
  1019. MCycles <= "010";
  1020. end if;
  1021. when 3 =>
  1022. NoRead <= '1';
  1023. JumpE <= '1';
  1024. TStates <= "101";
  1025. when others => null;
  1026. end case;
  1027. end if;
  1028. when "00101000" =>
  1029. if Mode /= 2 then
  1030. -- JR Z,e
  1031. MCycles <= "011";
  1032. case to_integer(unsigned(MCycle)) is
  1033. when 2 =>
  1034. Inc_PC <= '1';
  1035. if F(Flag_Z) = '0' then
  1036. MCycles <= "010";
  1037. end if;
  1038. when 3 =>
  1039. NoRead <= '1';
  1040. JumpE <= '1';
  1041. TStates <= "101";
  1042. when others => null;
  1043. end case;
  1044. end if;
  1045. when "00100000" =>
  1046. if Mode /= 2 then
  1047. -- JR NZ,e
  1048. MCycles <= "011";
  1049. case to_integer(unsigned(MCycle)) is
  1050. when 2 =>
  1051. Inc_PC <= '1';
  1052. if F(Flag_Z) = '1' then
  1053. MCycles <= "010";
  1054. end if;
  1055. when 3 =>
  1056. NoRead <= '1';
  1057. JumpE <= '1';
  1058. TStates <= "101";
  1059. when others => null;
  1060. end case;
  1061. end if;
  1062. when "11101001" =>
  1063. -- JP (HL)
  1064. JumpXY <= '1';
  1065. when "00010000" =>
  1066. if Mode = 3 then
  1067. I_DJNZ <= '1';
  1068. elsif Mode < 2 then
  1069. -- DJNZ,e
  1070. MCycles <= "011";
  1071. case to_integer(unsigned(MCycle)) is
  1072. when 1 =>
  1073. TStates <= "101";
  1074. I_DJNZ <= '1';
  1075. Set_BusB_To <= "1010";
  1076. Set_BusA_To(2 downto 0) <= "000";
  1077. Read_To_Reg <= '1';
  1078. Save_ALU <= '1';
  1079. ALU_Op <= "0010";
  1080. when 2 =>
  1081. I_DJNZ <= '1';
  1082. Inc_PC <= '1';
  1083. when 3 =>
  1084. NoRead <= '1';
  1085. JumpE <= '1';
  1086. TStates <= "101";
  1087. when others => null;
  1088. end case;
  1089. end if;
  1090. -- CALL AND RETURN GROUP
  1091. when "11001101" =>
  1092. -- CALL nn
  1093. MCycles <= "101";
  1094. case to_integer(unsigned(MCycle)) is
  1095. when 2 =>
  1096. Inc_PC <= '1';
  1097. LDZ <= '1';
  1098. when 3 =>
  1099. IncDec_16 <= "1111";
  1100. Inc_PC <= '1';
  1101. TStates <= "100";
  1102. Set_Addr_To <= aSP;
  1103. LDW <= '1';
  1104. Set_BusB_To <= "1101";
  1105. when 4 =>
  1106. Write <= '1';
  1107. IncDec_16 <= "1111";
  1108. Set_Addr_To <= aSP;
  1109. Set_BusB_To <= "1100";
  1110. when 5 =>
  1111. Write <= '1';
  1112. Call <= '1';
  1113. when others => null;
  1114. end case;
  1115. when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
  1116. if IR(5) = '0' or Mode /= 3 then
  1117. -- CALL cc,nn
  1118. MCycles <= "101";
  1119. case to_integer(unsigned(MCycle)) is
  1120. when 2 =>
  1121. Inc_PC <= '1';
  1122. LDZ <= '1';
  1123. when 3 =>
  1124. Inc_PC <= '1';
  1125. LDW <= '1';
  1126. if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
  1127. IncDec_16 <= "1111";
  1128. Set_Addr_TO <= aSP;
  1129. TStates <= "100";
  1130. Set_BusB_To <= "1101";
  1131. else
  1132. MCycles <= "011";
  1133. end if;
  1134. when 4 =>
  1135. Write <= '1';
  1136. IncDec_16 <= "1111";
  1137. Set_Addr_To <= aSP;
  1138. Set_BusB_To <= "1100";
  1139. when 5 =>
  1140. Write <= '1';
  1141. Call <= '1';
  1142. when others => null;
  1143. end case;
  1144. end if;
  1145. when "11001001" =>
  1146. -- RET
  1147. MCycles <= "011";
  1148. case to_integer(unsigned(MCycle)) is
  1149. when 1 =>
  1150. Set_Addr_TO <= aSP;
  1151. when 2 =>
  1152. IncDec_16 <= "0111";
  1153. Set_Addr_To <= aSP;
  1154. LDZ <= '1';
  1155. when 3 =>
  1156. Jump <= '1';
  1157. IncDec_16 <= "0111";
  1158. when others => null;
  1159. end case;
  1160. when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
  1161. if IR(5) = '1' and Mode = 3 then
  1162. case IRB(4 downto 3) is
  1163. when "00" =>
  1164. -- LD ($FF00+nn),A
  1165. MCycles <= "011";
  1166. case to_integer(unsigned(MCycle)) is
  1167. when 2 =>
  1168. Inc_PC <= '1';
  1169. Set_Addr_To <= aIOA;
  1170. Set_BusB_To <= "0111";
  1171. when 3 =>
  1172. Write <= '1';
  1173. when others => null;
  1174. end case;
  1175. when "01" =>
  1176. -- ADD SP,n
  1177. MCycles <= "011";
  1178. case to_integer(unsigned(MCycle)) is
  1179. when 2 =>
  1180. ALU_Op <= "0000";
  1181. Inc_PC <= '1';
  1182. Read_To_Reg <= '1';
  1183. Save_ALU <= '1';
  1184. Set_BusA_To <= "1000";
  1185. Set_BusB_To <= "0110";
  1186. when 3 =>
  1187. NoRead <= '1';
  1188. Read_To_Reg <= '1';
  1189. Save_ALU <= '1';
  1190. ALU_Op <= "0001";
  1191. Set_BusA_To <= "1001";
  1192. Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
  1193. when others =>
  1194. end case;
  1195. when "10" =>
  1196. -- LD A,($FF00+nn)
  1197. MCycles <= "011";
  1198. case to_integer(unsigned(MCycle)) is
  1199. when 2 =>
  1200. Inc_PC <= '1';
  1201. Set_Addr_To <= aIOA;
  1202. when 3 =>
  1203. Read_To_Acc <= '1';
  1204. when others => null;
  1205. end case;
  1206. when "11" =>
  1207. -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
  1208. MCycles <= "101";
  1209. case to_integer(unsigned(MCycle)) is
  1210. when 2 =>
  1211. Inc_PC <= '1';
  1212. LDZ <= '1';
  1213. when 3 =>
  1214. Set_Addr_To <= aZI;
  1215. Inc_PC <= '1';
  1216. LDW <= '1';
  1217. when 4 =>
  1218. Set_BusA_To(2 downto 0) <= "101"; -- L
  1219. Read_To_Reg <= '1';
  1220. Inc_WZ <= '1';
  1221. Set_Addr_To <= aZI;
  1222. when 5 =>
  1223. Set_BusA_To(2 downto 0) <= "100"; -- H
  1224. Read_To_Reg <= '1';
  1225. when others => null;
  1226. end case;
  1227. end case;
  1228. else
  1229. -- RET cc
  1230. MCycles <= "011";
  1231. case to_integer(unsigned(MCycle)) is
  1232. when 1 =>
  1233. if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
  1234. Set_Addr_TO <= aSP;
  1235. else
  1236. MCycles <= "001";
  1237. end if;
  1238. TStates <= "101";
  1239. when 2 =>
  1240. IncDec_16 <= "0111";
  1241. Set_Addr_To <= aSP;
  1242. LDZ <= '1';
  1243. when 3 =>
  1244. Jump <= '1';
  1245. IncDec_16 <= "0111";
  1246. when others => null;
  1247. end case;
  1248. end if;
  1249. when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
  1250. -- RST p
  1251. MCycles <= "011";
  1252. case to_integer(unsigned(MCycle)) is
  1253. when 1 =>
  1254. TStates <= "101";
  1255. IncDec_16 <= "1111";
  1256. Set_Addr_To <= aSP;
  1257. Set_BusB_To <= "1101";
  1258. when 2 =>
  1259. Write <= '1';
  1260. IncDec_16 <= "1111";
  1261. Set_Addr_To <= aSP;
  1262. Set_BusB_To <= "1100";
  1263. when 3 =>
  1264. Write <= '1';
  1265. RstP <= '1';
  1266. when others => null;
  1267. end case;
  1268. -- INPUT AND OUTPUT GROUP
  1269. when "11011011" =>
  1270. if Mode /= 3 then
  1271. -- IN A,(n)
  1272. MCycles <= "011";
  1273. case to_integer(unsigned(MCycle)) is
  1274. when 2 =>
  1275. Inc_PC <= '1';
  1276. Set_Addr_To <= aIOA;
  1277. when 3 =>
  1278. Read_To_Acc <= '1';
  1279. IORQ <= '1';
  1280. TStates <= "100"; -- MIKEJ should be 4 for IO cycle
  1281. when others => null;
  1282. end case;
  1283. end if;
  1284. when "11010011" =>
  1285. if Mode /= 3 then
  1286. -- OUT (n),A
  1287. MCycles <= "011";
  1288. case to_integer(unsigned(MCycle)) is
  1289. when 2 =>
  1290. Inc_PC <= '1';
  1291. Set_Addr_To <= aIOA;
  1292. Set_BusB_To <= "0111";
  1293. when 3 =>
  1294. Write <= '1';
  1295. IORQ <= '1';
  1296. TStates <= "100"; -- MIKEJ should be 4 for IO cycle
  1297. when others => null;
  1298. end case;
  1299. end if;
  1300. ------------------------------------------------------------------------------
  1301. ------------------------------------------------------------------------------
  1302. -- MULTIBYTE INSTRUCTIONS
  1303. ------------------------------------------------------------------------------
  1304. ------------------------------------------------------------------------------
  1305. when "11001011" =>
  1306. if Mode /= 2 then
  1307. Prefix <= "01";
  1308. end if;
  1309. when "11101101" =>
  1310. if Mode < 2 then
  1311. Prefix <= "10";
  1312. end if;
  1313. when "11011101"|"11111101" =>
  1314. if Mode < 2 then
  1315. Prefix <= "11";
  1316. end if;
  1317. end case;
  1318. when "01" =>
  1319. ------------------------------------------------------------------------------
  1320. --
  1321. -- CB prefixed instructions
  1322. --
  1323. ------------------------------------------------------------------------------
  1324. Set_BusA_To(2 downto 0) <= IR(2 downto 0);
  1325. Set_BusB_To(2 downto 0) <= IR(2 downto 0);
  1326. case IRB is
  1327. when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
  1328. |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
  1329. |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
  1330. |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
  1331. |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
  1332. |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
  1333. |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
  1334. |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
  1335. -- RLC r
  1336. -- RL r
  1337. -- RRC r
  1338. -- RR r
  1339. -- SLA r
  1340. -- SRA r
  1341. -- SRL r
  1342. -- SLL r (Undocumented) / SWAP r
  1343. if XY_State="00" then
  1344. if MCycle = "001" then
  1345. ALU_Op <= "1000";
  1346. Read_To_Reg <= '1';
  1347. Save_ALU <= '1';
  1348. end if;
  1349. else
  1350. -- R/S (IX+d),Reg, undocumented
  1351. MCycles <= "011";
  1352. XYbit_undoc <= '1';
  1353. case to_integer(unsigned(MCycle)) is
  1354. when 1 | 7=>
  1355. Set_Addr_To <= aXY;
  1356. when 2 =>
  1357. ALU_Op <= "1000";
  1358. Read_To_Reg <= '1';
  1359. Save_ALU <= '1';
  1360. Set_Addr_To <= aXY;
  1361. TStates <= "100";
  1362. when 3 =>
  1363. Write <= '1';
  1364. when others => null;
  1365. end case;
  1366. end if;
  1367. when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
  1368. -- RLC (HL)
  1369. -- RL (HL)
  1370. -- RRC (HL)
  1371. -- RR (HL)
  1372. -- SRA (HL)
  1373. -- SRL (HL)
  1374. -- SLA (HL)
  1375. -- SLL (HL) (Undocumented) / SWAP (HL)
  1376. MCycles <= "011";
  1377. case to_integer(unsigned(MCycle)) is
  1378. when 1 | 7 =>
  1379. Set_Addr_To <= aXY;
  1380. when 2 =>
  1381. ALU_Op <= "1000";
  1382. Read_To_Reg <= '1';
  1383. Save_ALU <= '1';
  1384. Set_Addr_To <= aXY;
  1385. TStates <= "100";
  1386. when 3 =>
  1387. Write <= '1';
  1388. when others =>
  1389. end case;
  1390. when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
  1391. |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
  1392. |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
  1393. |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
  1394. |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
  1395. |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
  1396. |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
  1397. |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
  1398. -- BIT b,r
  1399. if XY_State="00" then
  1400. if MCycle = "001" then
  1401. Set_BusB_To(2 downto 0) <= IR(2 downto 0);
  1402. ALU_Op <= "1001";
  1403. end if;
  1404. else
  1405. -- BIT b,(IX+d), undocumented
  1406. MCycles <= "010";
  1407. XYbit_undoc <= '1';
  1408. case to_integer(unsigned(MCycle)) is
  1409. when 1 | 7=>
  1410. Set_Addr_To <= aXY;
  1411. when 2 =>
  1412. ALU_Op <= "1001";
  1413. TStates <= "100";
  1414. when others => null;
  1415. end case;
  1416. end if;
  1417. when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
  1418. -- BIT b,(HL)
  1419. MCycles <= "010";
  1420. case to_integer(unsigned(MCycle)) is
  1421. when 1 | 7=>
  1422. Set_Addr_To <= aXY;
  1423. when 2 =>
  1424. ALU_Op <= "1001";
  1425. TStates <= "100";
  1426. when others => null;
  1427. end case;
  1428. when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
  1429. |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
  1430. |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
  1431. |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
  1432. |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
  1433. |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
  1434. |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
  1435. |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
  1436. -- SET b,r
  1437. if XY_State="00" then
  1438. if MCycle = "001" then
  1439. ALU_Op <= "1010";
  1440. Read_To_Reg <= '1';
  1441. Save_ALU <= '1';
  1442. end if;
  1443. else
  1444. -- SET b,(IX+d),Reg, undocumented
  1445. MCycles <= "011";
  1446. XYbit_undoc <= '1';
  1447. case to_integer(unsigned(MCycle)) is
  1448. when 1 | 7=>
  1449. Set_Addr_To <= aXY;
  1450. when 2 =>
  1451. ALU_Op <= "1010";
  1452. Read_To_Reg <= '1';
  1453. Save_ALU <= '1';
  1454. Set_Addr_To <= aXY;
  1455. TStates <= "100";
  1456. when 3 =>
  1457. Write <= '1';
  1458. when others => null;
  1459. end case;
  1460. end if;
  1461. when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
  1462. -- SET b,(HL)
  1463. MCycles <= "011";
  1464. case to_integer(unsigned(MCycle)) is
  1465. when 1 | 7=>
  1466. Set_Addr_To <= aXY;
  1467. when 2 =>
  1468. ALU_Op <= "1010";
  1469. Read_To_Reg <= '1';
  1470. Save_ALU <= '1';
  1471. Set_Addr_To <= aXY;
  1472. TStates <= "100";
  1473. when 3 =>
  1474. Write <= '1';
  1475. when others => null;
  1476. end case;
  1477. when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
  1478. |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
  1479. |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
  1480. |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
  1481. |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
  1482. |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
  1483. |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
  1484. |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
  1485. -- RES b,r
  1486. if XY_State="00" then
  1487. if MCycle = "001" then
  1488. ALU_Op <= "1011";
  1489. Read_To_Reg <= '1';
  1490. Save_ALU <= '1';
  1491. end if;
  1492. else
  1493. -- RES b,(IX+d),Reg, undocumented
  1494. MCycles <= "011";
  1495. XYbit_undoc <= '1';
  1496. case to_integer(unsigned(MCycle)) is
  1497. when 1 | 7=>
  1498. Set_Addr_To <= aXY;
  1499. when 2 =>
  1500. ALU_Op <= "1011";
  1501. Read_To_Reg <= '1';
  1502. Save_ALU <= '1';
  1503. Set_Addr_To <= aXY;
  1504. TStates <= "100";
  1505. when 3 =>
  1506. Write <= '1';
  1507. when others => null;
  1508. end case;
  1509. end if;
  1510. when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
  1511. -- RES b,(HL)
  1512. MCycles <= "011";
  1513. case to_integer(unsigned(MCycle)) is
  1514. when 1 | 7 =>
  1515. Set_Addr_To <= aXY;
  1516. when 2 =>
  1517. ALU_Op <= "1011";
  1518. Read_To_Reg <= '1';
  1519. Save_ALU <= '1';
  1520. Set_Addr_To <= aXY;
  1521. TStates <= "100";
  1522. when 3 =>
  1523. Write <= '1';
  1524. when others => null;
  1525. end case;
  1526. end case;
  1527. when others =>
  1528. ------------------------------------------------------------------------------
  1529. --
  1530. -- ED prefixed instructions
  1531. --
  1532. ------------------------------------------------------------------------------
  1533. case IRB is
  1534. when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
  1535. |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
  1536. |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
  1537. |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
  1538. |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
  1539. |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
  1540. |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
  1541. |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
  1542. |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
  1543. |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
  1544. |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
  1545. |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
  1546. | "10100100"|"10100101"|"10100110"|"10100111"
  1547. | "10101100"|"10101101"|"10101110"|"10101111"
  1548. | "10110100"|"10110101"|"10110110"|"10110111"
  1549. | "10111100"|"10111101"|"10111110"|"10111111"
  1550. |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
  1551. |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
  1552. |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
  1553. |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
  1554. |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
  1555. |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
  1556. |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
  1557. |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
  1558. null; -- NOP, undocumented
  1559. when "01111110"|"01111111" =>
  1560. -- NOP, undocumented
  1561. null;
  1562. -- 8 BIT LOAD GROUP
  1563. when "01010111" =>
  1564. -- LD A,I
  1565. Special_LD <= "100";
  1566. TStates <= "101";
  1567. when "01011111" =>
  1568. -- LD A,R
  1569. Special_LD <= "101";
  1570. TStates <= "101";
  1571. when "01000111" =>
  1572. -- LD I,A
  1573. Special_LD <= "110";
  1574. TStates <= "101";
  1575. when "01001111" =>
  1576. -- LD R,A
  1577. Special_LD <= "111";
  1578. TStates <= "101";
  1579. -- 16 BIT LOAD GROUP
  1580. when "01001011"|"01011011"|"01101011"|"01111011" =>
  1581. -- LD dd,(nn)
  1582. MCycles <= "101";
  1583. case to_integer(unsigned(MCycle)) is
  1584. when 2 =>
  1585. Inc_PC <= '1';
  1586. LDZ <= '1';
  1587. when 3 =>
  1588. Set_Addr_To <= aZI;
  1589. Inc_PC <= '1';
  1590. LDW <= '1';
  1591. when 4 =>
  1592. Read_To_Reg <= '1';
  1593. if IR(5 downto 4) = "11" then
  1594. Set_BusA_To <= "1000";
  1595. else
  1596. Set_BusA_To(2 downto 1) <= IR(5 downto 4);
  1597. Set_BusA_To(0) <= '1';
  1598. end if;
  1599. Inc_WZ <= '1';
  1600. Set_Addr_To <= aZI;
  1601. when 5 =>
  1602. Read_To_Reg <= '1';
  1603. if IR(5 downto 4) = "11" then
  1604. Set_BusA_To <= "1001";
  1605. else
  1606. Set_BusA_To(2 downto 1) <= IR(5 downto 4);
  1607. Set_BusA_To(0) <= '0';
  1608. end if;
  1609. when others => null;
  1610. end case;
  1611. when "01000011"|"01010011"|"01100011"|"01110011" =>
  1612. -- LD (nn),dd
  1613. MCycles <= "101";
  1614. case to_integer(unsigned(MCycle)) is
  1615. when 2 =>
  1616. Inc_PC <= '1';
  1617. LDZ <= '1';
  1618. when 3 =>
  1619. Set_Addr_To <= aZI;
  1620. Inc_PC <= '1';
  1621. LDW <= '1';
  1622. if IR(5 downto 4) = "11" then
  1623. Set_BusB_To <= "1000";
  1624. else
  1625. Set_BusB_To(2 downto 1) <= IR(5 downto 4);
  1626. Set_BusB_To(0) <= '1';
  1627. Set_BusB_To(3) <= '0';
  1628. end if;
  1629. when 4 =>
  1630. Inc_WZ <= '1';
  1631. Set_Addr_To <= aZI;
  1632. Write <= '1';
  1633. if IR(5 downto 4) = "11" then
  1634. Set_BusB_To <= "1001";
  1635. else
  1636. Set_BusB_To(2 downto 1) <= IR(5 downto 4);
  1637. Set_BusB_To(0) <= '0';
  1638. Set_BusB_To(3) <= '0';
  1639. end if;
  1640. when 5 =>
  1641. Write <= '1';
  1642. when others => null;
  1643. end case;
  1644. when "10100000" | "10101000" | "10110000" | "10111000" =>
  1645. -- LDI, LDD, LDIR, LDDR
  1646. MCycles <= "100";
  1647. case to_integer(unsigned(MCycle)) is
  1648. when 1 =>
  1649. Set_Addr_To <= aXY;
  1650. IncDec_16 <= "1100"; -- BC
  1651. when 2 =>
  1652. Set_BusB_To <= "0110";
  1653. Set_BusA_To(2 downto 0) <= "111";
  1654. ALU_Op <= "0000";
  1655. Set_Addr_To <= aDE;
  1656. if IR(3) = '0' then
  1657. IncDec_16 <= "0110"; -- IX
  1658. else
  1659. IncDec_16 <= "1110";
  1660. end if;
  1661. when 3 =>
  1662. I_BT <= '1';
  1663. TStates <= "101";
  1664. Write <= '1';
  1665. if IR(3) = '0' then
  1666. IncDec_16 <= "0101"; -- DE
  1667. else
  1668. IncDec_16 <= "1101";
  1669. end if;
  1670. when 4 =>
  1671. NoRead <= '1';
  1672. TStates <= "101";
  1673. when others => null;
  1674. end case;
  1675. when "10100001" | "10101001" | "10110001" | "10111001" =>
  1676. -- CPI, CPD, CPIR, CPDR
  1677. MCycles <= "100";
  1678. case to_integer(unsigned(MCycle)) is
  1679. when 1 =>
  1680. Set_Addr_To <= aXY;
  1681. IncDec_16 <= "1100"; -- BC
  1682. when 2 =>
  1683. Set_BusB_To <= "0110";
  1684. Set_BusA_To(2 downto 0) <= "111";
  1685. ALU_Op <= "0111";
  1686. Save_ALU <= '1';
  1687. PreserveC <= '1';
  1688. if IR(3) = '0' then
  1689. IncDec_16 <= "0110";
  1690. else
  1691. IncDec_16 <= "1110";
  1692. end if;
  1693. when 3 =>
  1694. NoRead <= '1';
  1695. I_BC <= '1';
  1696. TStates <= "101";
  1697. when 4 =>
  1698. NoRead <= '1';
  1699. TStates <= "101";
  1700. when others => null;
  1701. end case;
  1702. when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
  1703. -- NEG
  1704. Alu_OP <= "0010";
  1705. Set_BusB_To <= "0111";
  1706. Set_BusA_To <= "1010";
  1707. Read_To_Acc <= '1';
  1708. Save_ALU <= '1';
  1709. when "01000110"|"01001110"|"01100110"|"01101110" =>
  1710. -- IM 0
  1711. IMode <= "00";
  1712. when "01010110"|"01110110" =>
  1713. -- IM 1
  1714. IMode <= "01";
  1715. when "01011110"|"01110111" =>
  1716. -- IM 2
  1717. IMode <= "10";
  1718. -- 16 bit arithmetic
  1719. when "01001010"|"01011010"|"01101010"|"01111010" =>
  1720. -- ADC HL,ss
  1721. MCycles <= "011";
  1722. case to_integer(unsigned(MCycle)) is
  1723. when 2 =>
  1724. NoRead <= '1';
  1725. ALU_Op <= "0001";
  1726. Read_To_Reg <= '1';
  1727. Save_ALU <= '1';
  1728. Set_BusA_To(2 downto 0) <= "101";
  1729. case to_integer(unsigned(IR(5 downto 4))) is
  1730. when 0|1|2 =>
  1731. Set_BusB_To(2 downto 1) <= IR(5 downto 4);
  1732. Set_BusB_To(0) <= '1';
  1733. when others =>
  1734. Set_BusB_To <= "1000";
  1735. end case;
  1736. TStates <= "100";
  1737. when 3 =>
  1738. NoRead <= '1';
  1739. Read_To_Reg <= '1';
  1740. Save_ALU <= '1';
  1741. ALU_Op <= "0001";
  1742. Set_BusA_To(2 downto 0) <= "100";
  1743. case to_integer(unsigned(IR(5 downto 4))) is
  1744. when 0|1|2 =>
  1745. Set_BusB_To(2 downto 1) <= IR(5 downto 4);
  1746. Set_BusB_To(0) <= '0';
  1747. when others =>
  1748. Set_BusB_To <= "1001";
  1749. end case;
  1750. when others =>
  1751. end case;
  1752. when "01000010"|"01010010"|"01100010"|"01110010" =>
  1753. -- SBC HL,ss
  1754. MCycles <= "011";
  1755. case to_integer(unsigned(MCycle)) is
  1756. when 2 =>
  1757. NoRead <= '1';
  1758. ALU_Op <= "0011";
  1759. Read_To_Reg <= '1';
  1760. Save_ALU <= '1';
  1761. Set_BusA_To(2 downto 0) <= "101";
  1762. case to_integer(unsigned(IR(5 downto 4))) is
  1763. when 0|1|2 =>
  1764. Set_BusB_To(2 downto 1) <= IR(5 downto 4);
  1765. Set_BusB_To(0) <= '1';
  1766. when others =>
  1767. Set_BusB_To <= "1000";
  1768. end case;
  1769. TStates <= "100";
  1770. when 3 =>
  1771. NoRead <= '1';
  1772. ALU_Op <= "0011";
  1773. Read_To_Reg <= '1';
  1774. Save_ALU <= '1';
  1775. Set_BusA_To(2 downto 0) <= "100";
  1776. case to_integer(unsigned(IR(5 downto 4))) is
  1777. when 0|1|2 =>
  1778. Set_BusB_To(2 downto 1) <= IR(5 downto 4);
  1779. when others =>
  1780. Set_BusB_To <= "1001";
  1781. end case;
  1782. when others =>
  1783. end case;
  1784. when "01101111" =>
  1785. -- RLD
  1786. MCycles <= "100";
  1787. case to_integer(unsigned(MCycle)) is
  1788. when 2 =>
  1789. NoRead <= '1';
  1790. Set_Addr_To <= aXY;
  1791. when 3 =>
  1792. Read_To_Reg <= '1';
  1793. Set_BusB_To(2 downto 0) <= "110";
  1794. Set_BusA_To(2 downto 0) <= "111";
  1795. ALU_Op <= "1101";
  1796. TStates <= "100";
  1797. Set_Addr_To <= aXY;
  1798. Save_ALU <= '1';
  1799. when 4 =>
  1800. I_RLD <= '1';
  1801. Write <= '1';
  1802. when others =>
  1803. end case;
  1804. when "01100111" =>
  1805. -- RRD
  1806. MCycles <= "100";
  1807. case to_integer(unsigned(MCycle)) is
  1808. when 2 =>
  1809. Set_Addr_To <= aXY;
  1810. when 3 =>
  1811. Read_To_Reg <= '1';
  1812. Set_BusB_To(2 downto 0) <= "110";
  1813. Set_BusA_To(2 downto 0) <= "111";
  1814. ALU_Op <= "1110";
  1815. TStates <= "100";
  1816. Set_Addr_To <= aXY;
  1817. Save_ALU <= '1';
  1818. when 4 =>
  1819. I_RRD <= '1';
  1820. Write <= '1';
  1821. when others =>
  1822. end case;
  1823. when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
  1824. -- RETI, RETN
  1825. MCycles <= "011";
  1826. case to_integer(unsigned(MCycle)) is
  1827. when 1 =>
  1828. Set_Addr_TO <= aSP;
  1829. when 2 =>
  1830. IncDec_16 <= "0111";
  1831. Set_Addr_To <= aSP;
  1832. LDZ <= '1';
  1833. when 3 =>
  1834. Jump <= '1';
  1835. IncDec_16 <= "0111";
  1836. I_RETN <= '1';
  1837. when others => null;
  1838. end case;
  1839. when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
  1840. -- IN r,(C)
  1841. MCycles <= "010";
  1842. case to_integer(unsigned(MCycle)) is
  1843. when 1 =>
  1844. Set_Addr_To <= aBC;
  1845. when 2 =>
  1846. TStates <= "100"; -- MIKEJ should be 4 for IO cycle
  1847. IORQ <= '1';
  1848. if IR(5 downto 3) /= "110" then
  1849. Read_To_Reg <= '1';
  1850. Set_BusA_To(2 downto 0) <= IR(5 downto 3);
  1851. end if;
  1852. I_INRC <= '1';
  1853. when others =>
  1854. end case;
  1855. when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
  1856. -- OUT (C),r
  1857. -- OUT (C),0
  1858. MCycles <= "010";
  1859. case to_integer(unsigned(MCycle)) is
  1860. when 1 =>
  1861. Set_Addr_To <= aBC;
  1862. Set_BusB_To(2 downto 0) <= IR(5 downto 3);
  1863. if IR(5 downto 3) = "110" then
  1864. Set_BusB_To(3) <= '1';
  1865. end if;
  1866. when 2 =>
  1867. TStates <= "100"; -- MIKEJ should be 4 for IO cycle
  1868. Write <= '1';
  1869. IORQ <= '1';
  1870. when others =>
  1871. end case;
  1872. when "10100010" | "10101010" | "10110010" | "10111010" =>
  1873. -- INI, IND, INIR, INDR
  1874. -- note B is decremented AFTER being put on the bus
  1875. MCycles <= "100";
  1876. case to_integer(unsigned(MCycle)) is
  1877. when 1 =>
  1878. Set_Addr_To <= aBC;
  1879. Set_BusB_To <= "1010";
  1880. Set_BusA_To <= "0000";
  1881. Read_To_Reg <= '1';
  1882. Save_ALU <= '1';
  1883. ALU_Op <= "0010";
  1884. when 2 =>
  1885. TStates <= "100"; -- MIKEJ should be 4 for IO cycle
  1886. IORQ <= '1';
  1887. Set_BusB_To <= "0110";
  1888. Set_Addr_To <= aXY;
  1889. when 3 =>
  1890. if IR(3) = '0' then
  1891. --IncDec_16 <= "0010";
  1892. IncDec_16 <= "0110";
  1893. else
  1894. --IncDec_16 <= "1010";
  1895. IncDec_16 <= "1110";
  1896. end if;
  1897. TStates <= "100";
  1898. Write <= '1';
  1899. I_BTR <= '1';
  1900. when 4 =>
  1901. NoRead <= '1';
  1902. TStates <= "101";
  1903. when others => null;
  1904. end case;
  1905. when "10100011" | "10101011" | "10110011" | "10111011" =>
  1906. -- OUTI, OUTD, OTIR, OTDR
  1907. -- note B is decremented BEFORE being put on the bus.
  1908. -- mikej fix for hl inc
  1909. MCycles <= "100";
  1910. case to_integer(unsigned(MCycle)) is
  1911. when 1 =>
  1912. TStates <= "101";
  1913. Set_Addr_To <= aXY;
  1914. Set_BusB_To <= "1010";
  1915. Set_BusA_To <= "0000";
  1916. Read_To_Reg <= '1';
  1917. Save_ALU <= '1';
  1918. ALU_Op <= "0010";
  1919. when 2 =>
  1920. Set_BusB_To <= "0110";
  1921. Set_Addr_To <= aBC;
  1922. when 3 =>
  1923. if IR(3) = '0' then
  1924. IncDec_16 <= "0110"; -- mikej
  1925. else
  1926. IncDec_16 <= "1110"; -- mikej
  1927. end if;
  1928. TStates <= "100"; -- MIKEJ should be 4 for IO cycle
  1929. IORQ <= '1';
  1930. Write <= '1';
  1931. I_BTR <= '1';
  1932. when 4 =>
  1933. NoRead <= '1';
  1934. TStates <= "101";
  1935. when others => null;
  1936. end case;
  1937. end case;
  1938. end case;
  1939. if Mode = 1 then
  1940. if MCycle = "001" then
  1941. -- TStates <= "100";
  1942. else
  1943. TStates <= "011";
  1944. end if;
  1945. end if;
  1946. if Mode = 3 then
  1947. if MCycle = "001" then
  1948. -- TStates <= "100";
  1949. else
  1950. TStates <= "100";
  1951. end if;
  1952. end if;
  1953. if Mode < 2 then
  1954. if MCycle = "110" then
  1955. Inc_PC <= '1';
  1956. if Mode = 1 then
  1957. Set_Addr_To <= aXY;
  1958. TStates <= "100";
  1959. Set_BusB_To(2 downto 0) <= SSS;
  1960. Set_BusB_To(3) <= '0';
  1961. end if;
  1962. if IRB = "00110110" or IRB = "11001011" then
  1963. Set_Addr_To <= aNone;
  1964. end if;
  1965. end if;
  1966. if MCycle = "111" then
  1967. if Mode = 0 then
  1968. TStates <= "101";
  1969. end if;
  1970. if ISet /= "01" then
  1971. Set_Addr_To <= aXY;
  1972. end if;
  1973. Set_BusB_To(2 downto 0) <= SSS;
  1974. Set_BusB_To(3) <= '0';
  1975. if IRB = "00110110" or ISet = "01" then
  1976. -- LD (HL),n
  1977. Inc_PC <= '1';
  1978. else
  1979. NoRead <= '1';
  1980. end if;
  1981. end if;
  1982. end if;
  1983. end process;
  1984. end;