T80.vhd 31 KB

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  1. -- ****
  2. -- T80(b) core. In an effort to merge and maintain bug fixes ....
  3. --
  4. --
  5. -- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
  6. -- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
  7. -- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
  8. -- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
  9. --
  10. -- MikeJ March 2005
  11. -- Latest version from www.fpgaarcade.com (original www.opencores.org)
  12. --
  13. -- ****
  14. --
  15. -- Z80 compatible microprocessor core
  16. --
  17. -- Version : 0247
  18. --
  19. -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
  20. --
  21. -- All rights reserved
  22. --
  23. -- Redistribution and use in source and synthezised forms, with or without
  24. -- modification, are permitted provided that the following conditions are met:
  25. --
  26. -- Redistributions of source code must retain the above copyright notice,
  27. -- this list of conditions and the following disclaimer.
  28. --
  29. -- Redistributions in synthesized form must reproduce the above copyright
  30. -- notice, this list of conditions and the following disclaimer in the
  31. -- documentation and/or other materials provided with the distribution.
  32. --
  33. -- Neither the name of the author nor the names of other contributors may
  34. -- be used to endorse or promote products derived from this software without
  35. -- specific prior written permission.
  36. --
  37. -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  38. -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  39. -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  40. -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
  41. -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  42. -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  43. -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  44. -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  45. -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  46. -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  47. -- POSSIBILITY OF SUCH DAMAGE.
  48. --
  49. -- Please report bugs to the author, but before you do so, please
  50. -- make sure that this is not a derivative work and that
  51. -- you have the latest version of this file.
  52. --
  53. -- The latest version of this file can be found at:
  54. -- http://www.opencores.org/cvsweb.shtml/t80/
  55. --
  56. -- Limitations :
  57. --
  58. -- File history :
  59. --
  60. -- 0208 : First complete release
  61. --
  62. -- 0210 : Fixed wait and halt
  63. --
  64. -- 0211 : Fixed Refresh addition and IM 1
  65. --
  66. -- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
  67. --
  68. -- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
  69. --
  70. -- 0235 : Added clock enable and IM 2 fix by Mike Johnson
  71. --
  72. -- 0237 : Changed 8080 I/O address output, added IntE output
  73. --
  74. -- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
  75. --
  76. -- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
  77. --
  78. -- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
  79. --
  80. -- 0247 : Fixed bus req/ack cycle
  81. --
  82. library IEEE;
  83. use IEEE.std_logic_1164.all;
  84. use IEEE.numeric_std.all;
  85. use work.T80_Pack.all;
  86. entity T80 is
  87. generic(
  88. Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
  89. IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
  90. Flag_C : integer := 0;
  91. Flag_N : integer := 1;
  92. Flag_P : integer := 2;
  93. Flag_X : integer := 3;
  94. Flag_H : integer := 4;
  95. Flag_Y : integer := 5;
  96. Flag_Z : integer := 6;
  97. Flag_S : integer := 7
  98. );
  99. port(
  100. RESET_n : in std_logic;
  101. CLK_n : in std_logic;
  102. CEN : in std_logic;
  103. WAIT_n : in std_logic;
  104. INT_n : in std_logic;
  105. NMI_n : in std_logic;
  106. BUSRQ_n : in std_logic;
  107. M1_n : out std_logic;
  108. IORQ : out std_logic;
  109. NoRead : out std_logic;
  110. Write : out std_logic;
  111. RFSH_n : out std_logic;
  112. HALT_n : out std_logic;
  113. BUSAK_n : out std_logic;
  114. A : out std_logic_vector(15 downto 0);
  115. DInst : in std_logic_vector(7 downto 0);
  116. DI : in std_logic_vector(7 downto 0);
  117. DO : out std_logic_vector(7 downto 0);
  118. MC : out std_logic_vector(2 downto 0);
  119. TS : out std_logic_vector(2 downto 0);
  120. IntCycle_n : out std_logic;
  121. IntE : out std_logic;
  122. Stop : out std_logic
  123. );
  124. end T80;
  125. architecture rtl of T80 is
  126. constant aNone : std_logic_vector(2 downto 0) := "111";
  127. constant aBC : std_logic_vector(2 downto 0) := "000";
  128. constant aDE : std_logic_vector(2 downto 0) := "001";
  129. constant aXY : std_logic_vector(2 downto 0) := "010";
  130. constant aIOA : std_logic_vector(2 downto 0) := "100";
  131. constant aSP : std_logic_vector(2 downto 0) := "101";
  132. constant aZI : std_logic_vector(2 downto 0) := "110";
  133. -- Registers
  134. signal ACC, F : std_logic_vector(7 downto 0);
  135. signal Ap, Fp : std_logic_vector(7 downto 0);
  136. signal I : std_logic_vector(7 downto 0);
  137. signal R : unsigned(7 downto 0);
  138. signal SP, PC : unsigned(15 downto 0);
  139. signal RegDIH : std_logic_vector(7 downto 0);
  140. signal RegDIL : std_logic_vector(7 downto 0);
  141. signal RegBusA : std_logic_vector(15 downto 0);
  142. signal RegBusB : std_logic_vector(15 downto 0);
  143. signal RegBusC : std_logic_vector(15 downto 0);
  144. signal RegAddrA_r : std_logic_vector(2 downto 0);
  145. signal RegAddrA : std_logic_vector(2 downto 0);
  146. signal RegAddrB_r : std_logic_vector(2 downto 0);
  147. signal RegAddrB : std_logic_vector(2 downto 0);
  148. signal RegAddrC : std_logic_vector(2 downto 0);
  149. signal RegWEH : std_logic;
  150. signal RegWEL : std_logic;
  151. signal Alternate : std_logic;
  152. -- Help Registers
  153. signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
  154. signal IR : std_logic_vector(7 downto 0); -- Instruction register
  155. signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
  156. signal RegBusA_r : std_logic_vector(15 downto 0);
  157. signal ID16 : signed(15 downto 0);
  158. signal Save_Mux : std_logic_vector(7 downto 0);
  159. signal TState : unsigned(2 downto 0);
  160. signal MCycle : std_logic_vector(2 downto 0);
  161. signal IntE_FF1 : std_logic;
  162. signal IntE_FF2 : std_logic;
  163. signal Halt_FF : std_logic;
  164. signal BusReq_s : std_logic;
  165. signal BusAck : std_logic;
  166. signal ClkEn : std_logic;
  167. signal NMI_s : std_logic;
  168. signal INT_s : std_logic;
  169. signal IStatus : std_logic_vector(1 downto 0);
  170. signal DI_Reg : std_logic_vector(7 downto 0);
  171. signal T_Res : std_logic;
  172. signal XY_State : std_logic_vector(1 downto 0);
  173. signal Pre_XY_F_M : std_logic_vector(2 downto 0);
  174. signal NextIs_XY_Fetch : std_logic;
  175. signal XY_Ind : std_logic;
  176. signal No_BTR : std_logic;
  177. signal BTR_r : std_logic;
  178. signal Auto_Wait : std_logic;
  179. signal Auto_Wait_t1 : std_logic;
  180. signal Auto_Wait_t2 : std_logic;
  181. signal IncDecZ : std_logic;
  182. -- ALU signals
  183. signal BusB : std_logic_vector(7 downto 0);
  184. signal BusA : std_logic_vector(7 downto 0);
  185. signal ALU_Q : std_logic_vector(7 downto 0);
  186. signal F_Out : std_logic_vector(7 downto 0);
  187. -- Registered micro code outputs
  188. signal Read_To_Reg_r : std_logic_vector(4 downto 0);
  189. signal Arith16_r : std_logic;
  190. signal Z16_r : std_logic;
  191. signal ALU_Op_r : std_logic_vector(3 downto 0);
  192. signal Save_ALU_r : std_logic;
  193. signal PreserveC_r : std_logic;
  194. signal MCycles : std_logic_vector(2 downto 0);
  195. -- Micro code outputs
  196. signal MCycles_d : std_logic_vector(2 downto 0);
  197. signal TStates : std_logic_vector(2 downto 0);
  198. signal IntCycle : std_logic;
  199. signal NMICycle : std_logic;
  200. signal Inc_PC : std_logic;
  201. signal Inc_WZ : std_logic;
  202. signal IncDec_16 : std_logic_vector(3 downto 0);
  203. signal Prefix : std_logic_vector(1 downto 0);
  204. signal Read_To_Acc : std_logic;
  205. signal Read_To_Reg : std_logic;
  206. signal Set_BusB_To : std_logic_vector(3 downto 0);
  207. signal Set_BusA_To : std_logic_vector(3 downto 0);
  208. signal ALU_Op : std_logic_vector(3 downto 0);
  209. signal Save_ALU : std_logic;
  210. signal PreserveC : std_logic;
  211. signal Arith16 : std_logic;
  212. signal Set_Addr_To : std_logic_vector(2 downto 0);
  213. signal Jump : std_logic;
  214. signal JumpE : std_logic;
  215. signal JumpXY : std_logic;
  216. signal Call : std_logic;
  217. signal RstP : std_logic;
  218. signal LDZ : std_logic;
  219. signal LDW : std_logic;
  220. signal LDSPHL : std_logic;
  221. signal IORQ_i : std_logic;
  222. signal Special_LD : std_logic_vector(2 downto 0);
  223. signal ExchangeDH : std_logic;
  224. signal ExchangeRp : std_logic;
  225. signal ExchangeAF : std_logic;
  226. signal ExchangeRS : std_logic;
  227. signal I_DJNZ : std_logic;
  228. signal I_CPL : std_logic;
  229. signal I_CCF : std_logic;
  230. signal I_SCF : std_logic;
  231. signal I_RETN : std_logic;
  232. signal I_BT : std_logic;
  233. signal I_BC : std_logic;
  234. signal I_BTR : std_logic;
  235. signal I_RLD : std_logic;
  236. signal I_RRD : std_logic;
  237. signal I_INRC : std_logic;
  238. signal SetDI : std_logic;
  239. signal SetEI : std_logic;
  240. signal IMode : std_logic_vector(1 downto 0);
  241. signal Halt : std_logic;
  242. signal XYbit_undoc : std_logic;
  243. begin
  244. mcode : T80_MCode
  245. generic map(
  246. Mode => Mode,
  247. Flag_C => Flag_C,
  248. Flag_N => Flag_N,
  249. Flag_P => Flag_P,
  250. Flag_X => Flag_X,
  251. Flag_H => Flag_H,
  252. Flag_Y => Flag_Y,
  253. Flag_Z => Flag_Z,
  254. Flag_S => Flag_S)
  255. port map(
  256. IR => IR,
  257. ISet => ISet,
  258. MCycle => MCycle,
  259. F => F,
  260. NMICycle => NMICycle,
  261. IntCycle => IntCycle,
  262. XY_State => XY_State,
  263. MCycles => MCycles_d,
  264. TStates => TStates,
  265. Prefix => Prefix,
  266. Inc_PC => Inc_PC,
  267. Inc_WZ => Inc_WZ,
  268. IncDec_16 => IncDec_16,
  269. Read_To_Acc => Read_To_Acc,
  270. Read_To_Reg => Read_To_Reg,
  271. Set_BusB_To => Set_BusB_To,
  272. Set_BusA_To => Set_BusA_To,
  273. ALU_Op => ALU_Op,
  274. Save_ALU => Save_ALU,
  275. PreserveC => PreserveC,
  276. Arith16 => Arith16,
  277. Set_Addr_To => Set_Addr_To,
  278. IORQ => IORQ_i,
  279. Jump => Jump,
  280. JumpE => JumpE,
  281. JumpXY => JumpXY,
  282. Call => Call,
  283. RstP => RstP,
  284. LDZ => LDZ,
  285. LDW => LDW,
  286. LDSPHL => LDSPHL,
  287. Special_LD => Special_LD,
  288. ExchangeDH => ExchangeDH,
  289. ExchangeRp => ExchangeRp,
  290. ExchangeAF => ExchangeAF,
  291. ExchangeRS => ExchangeRS,
  292. I_DJNZ => I_DJNZ,
  293. I_CPL => I_CPL,
  294. I_CCF => I_CCF,
  295. I_SCF => I_SCF,
  296. I_RETN => I_RETN,
  297. I_BT => I_BT,
  298. I_BC => I_BC,
  299. I_BTR => I_BTR,
  300. I_RLD => I_RLD,
  301. I_RRD => I_RRD,
  302. I_INRC => I_INRC,
  303. SetDI => SetDI,
  304. SetEI => SetEI,
  305. IMode => IMode,
  306. Halt => Halt,
  307. NoRead => NoRead,
  308. Write => Write,
  309. XYbit_undoc => XYbit_undoc);
  310. alu : T80_ALU
  311. generic map(
  312. Mode => Mode,
  313. Flag_C => Flag_C,
  314. Flag_N => Flag_N,
  315. Flag_P => Flag_P,
  316. Flag_X => Flag_X,
  317. Flag_H => Flag_H,
  318. Flag_Y => Flag_Y,
  319. Flag_Z => Flag_Z,
  320. Flag_S => Flag_S)
  321. port map(
  322. Arith16 => Arith16_r,
  323. Z16 => Z16_r,
  324. ALU_Op => ALU_Op_r,
  325. IR => IR(5 downto 0),
  326. ISet => ISet,
  327. BusA => BusA,
  328. BusB => BusB,
  329. F_In => F,
  330. Q => ALU_Q,
  331. F_Out => F_Out);
  332. ClkEn <= CEN and not BusAck;
  333. T_Res <= '1' when TState = unsigned(TStates) else '0';
  334. NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
  335. ((Set_Addr_To = aXY) or
  336. (MCycle = "001" and IR = "11001011") or
  337. (MCycle = "001" and IR = "00110110")) else '0';
  338. Save_Mux <= BusB when ExchangeRp = '1' else
  339. DI_Reg when Save_ALU_r = '0' else
  340. ALU_Q;
  341. process (RESET_n, CLK_n)
  342. begin
  343. if RESET_n = '0' then
  344. PC <= (others => '0'); -- Program Counter
  345. A <= (others => '0');
  346. TmpAddr <= (others => '0');
  347. IR <= "00000000";
  348. ISet <= "00";
  349. XY_State <= "00";
  350. IStatus <= "00";
  351. MCycles <= "000";
  352. DO <= "00000000";
  353. ACC <= (others => '1');
  354. F <= (others => '1');
  355. Ap <= (others => '1');
  356. Fp <= (others => '1');
  357. I <= (others => '0');
  358. R <= (others => '0');
  359. SP <= (others => '1');
  360. Alternate <= '0';
  361. Read_To_Reg_r <= "00000";
  362. F <= (others => '1');
  363. Arith16_r <= '0';
  364. BTR_r <= '0';
  365. Z16_r <= '0';
  366. ALU_Op_r <= "0000";
  367. Save_ALU_r <= '0';
  368. PreserveC_r <= '0';
  369. XY_Ind <= '0';
  370. elsif CLK_n'event and CLK_n = '1' then
  371. if ClkEn = '1' then
  372. ALU_Op_r <= "0000";
  373. Save_ALU_r <= '0';
  374. Read_To_Reg_r <= "00000";
  375. MCycles <= MCycles_d;
  376. if IMode /= "11" then
  377. IStatus <= IMode;
  378. end if;
  379. Arith16_r <= Arith16;
  380. PreserveC_r <= PreserveC;
  381. if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
  382. Z16_r <= '1';
  383. else
  384. Z16_r <= '0';
  385. end if;
  386. if MCycle = "001" and TState(2) = '0' then
  387. -- MCycle = 1 and TState = 1, 2, or 3
  388. if TState = 2 and Wait_n = '1' then
  389. if Mode < 2 then
  390. A(7 downto 0) <= std_logic_vector(R);
  391. A(15 downto 8) <= I;
  392. R(6 downto 0) <= R(6 downto 0) + 1;
  393. end if;
  394. if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
  395. PC <= PC + 1;
  396. end if;
  397. if IntCycle = '1' and IStatus = "01" then
  398. IR <= "11111111";
  399. elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
  400. IR <= "00000000";
  401. else
  402. IR <= DInst;
  403. end if;
  404. ISet <= "00";
  405. if Prefix /= "00" then
  406. if Prefix = "11" then
  407. if IR(5) = '1' then
  408. XY_State <= "10";
  409. else
  410. XY_State <= "01";
  411. end if;
  412. else
  413. if Prefix = "10" then
  414. XY_State <= "00";
  415. XY_Ind <= '0';
  416. end if;
  417. ISet <= Prefix;
  418. end if;
  419. else
  420. XY_State <= "00";
  421. XY_Ind <= '0';
  422. end if;
  423. end if;
  424. else
  425. -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
  426. if MCycle = "110" then
  427. XY_Ind <= '1';
  428. if Prefix = "01" then
  429. ISet <= "01";
  430. end if;
  431. end if;
  432. if T_Res = '1' then
  433. BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
  434. if Jump = '1' then
  435. A(15 downto 8) <= DI_Reg;
  436. A(7 downto 0) <= TmpAddr(7 downto 0);
  437. PC(15 downto 8) <= unsigned(DI_Reg);
  438. PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
  439. elsif JumpXY = '1' then
  440. A <= RegBusC;
  441. PC <= unsigned(RegBusC);
  442. elsif Call = '1' or RstP = '1' then
  443. A <= TmpAddr;
  444. PC <= unsigned(TmpAddr);
  445. elsif MCycle = MCycles and NMICycle = '1' then
  446. A <= "0000000001100110";
  447. PC <= "0000000001100110";
  448. elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
  449. A(15 downto 8) <= I;
  450. A(7 downto 0) <= TmpAddr(7 downto 0);
  451. PC(15 downto 8) <= unsigned(I);
  452. PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
  453. else
  454. case Set_Addr_To is
  455. when aXY =>
  456. if XY_State = "00" then
  457. A <= RegBusC;
  458. else
  459. if NextIs_XY_Fetch = '1' then
  460. A <= std_logic_vector(PC);
  461. else
  462. A <= TmpAddr;
  463. end if;
  464. end if;
  465. when aIOA =>
  466. if Mode = 3 then
  467. -- Memory map I/O on GBZ80
  468. A(15 downto 8) <= (others => '1');
  469. elsif Mode = 2 then
  470. -- Duplicate I/O address on 8080
  471. A(15 downto 8) <= DI_Reg;
  472. else
  473. A(15 downto 8) <= ACC;
  474. end if;
  475. A(7 downto 0) <= DI_Reg;
  476. when aSP =>
  477. A <= std_logic_vector(SP);
  478. when aBC =>
  479. if Mode = 3 and IORQ_i = '1' then
  480. -- Memory map I/O on GBZ80
  481. A(15 downto 8) <= (others => '1');
  482. A(7 downto 0) <= RegBusC(7 downto 0);
  483. else
  484. A <= RegBusC;
  485. end if;
  486. when aDE =>
  487. A <= RegBusC;
  488. when aZI =>
  489. if Inc_WZ = '1' then
  490. A <= std_logic_vector(unsigned(TmpAddr) + 1);
  491. else
  492. A(15 downto 8) <= DI_Reg;
  493. A(7 downto 0) <= TmpAddr(7 downto 0);
  494. end if;
  495. when others =>
  496. A <= std_logic_vector(PC);
  497. end case;
  498. end if;
  499. Save_ALU_r <= Save_ALU;
  500. ALU_Op_r <= ALU_Op;
  501. if I_CPL = '1' then
  502. -- CPL
  503. ACC <= not ACC;
  504. F(Flag_Y) <= not ACC(5);
  505. F(Flag_H) <= '1';
  506. F(Flag_X) <= not ACC(3);
  507. F(Flag_N) <= '1';
  508. end if;
  509. if I_CCF = '1' then
  510. -- CCF
  511. F(Flag_C) <= not F(Flag_C);
  512. F(Flag_Y) <= ACC(5);
  513. F(Flag_H) <= F(Flag_C);
  514. F(Flag_X) <= ACC(3);
  515. F(Flag_N) <= '0';
  516. end if;
  517. if I_SCF = '1' then
  518. -- SCF
  519. F(Flag_C) <= '1';
  520. F(Flag_Y) <= ACC(5);
  521. F(Flag_H) <= '0';
  522. F(Flag_X) <= ACC(3);
  523. F(Flag_N) <= '0';
  524. end if;
  525. end if;
  526. if TState = 2 and Wait_n = '1' then
  527. if ISet = "01" and MCycle = "111" then
  528. IR <= DInst;
  529. end if;
  530. if JumpE = '1' then
  531. PC <= unsigned(signed(PC) + signed(DI_Reg));
  532. elsif Inc_PC = '1' then
  533. PC <= PC + 1;
  534. end if;
  535. if BTR_r = '1' then
  536. PC <= PC - 2;
  537. end if;
  538. if RstP = '1' then
  539. TmpAddr <= (others =>'0');
  540. TmpAddr(5 downto 3) <= IR(5 downto 3);
  541. end if;
  542. end if;
  543. if TState = 3 and MCycle = "110" then
  544. TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
  545. end if;
  546. if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
  547. if IncDec_16(2 downto 0) = "111" then
  548. if IncDec_16(3) = '1' then
  549. SP <= SP - 1;
  550. else
  551. SP <= SP + 1;
  552. end if;
  553. end if;
  554. end if;
  555. if LDSPHL = '1' then
  556. SP <= unsigned(RegBusC);
  557. end if;
  558. if ExchangeAF = '1' then
  559. Ap <= ACC;
  560. ACC <= Ap;
  561. Fp <= F;
  562. F <= Fp;
  563. end if;
  564. if ExchangeRS = '1' then
  565. Alternate <= not Alternate;
  566. end if;
  567. end if;
  568. if TState = 3 then
  569. if LDZ = '1' then
  570. TmpAddr(7 downto 0) <= DI_Reg;
  571. end if;
  572. if LDW = '1' then
  573. TmpAddr(15 downto 8) <= DI_Reg;
  574. end if;
  575. if Special_LD(2) = '1' then
  576. case Special_LD(1 downto 0) is
  577. when "00" =>
  578. ACC <= I;
  579. F(Flag_P) <= IntE_FF2;
  580. when "01" =>
  581. ACC <= std_logic_vector(R);
  582. F(Flag_P) <= IntE_FF2;
  583. when "10" =>
  584. I <= ACC;
  585. when others =>
  586. R <= unsigned(ACC);
  587. end case;
  588. end if;
  589. end if;
  590. if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
  591. if Mode = 3 then
  592. F(6) <= F_Out(6);
  593. F(5) <= F_Out(5);
  594. F(7) <= F_Out(7);
  595. if PreserveC_r = '0' then
  596. F(4) <= F_Out(4);
  597. end if;
  598. else
  599. F(7 downto 1) <= F_Out(7 downto 1);
  600. if PreserveC_r = '0' then
  601. F(Flag_C) <= F_Out(0);
  602. end if;
  603. end if;
  604. end if;
  605. if T_Res = '1' and I_INRC = '1' then
  606. F(Flag_H) <= '0';
  607. F(Flag_N) <= '0';
  608. if DI_Reg(7 downto 0) = "00000000" then
  609. F(Flag_Z) <= '1';
  610. else
  611. F(Flag_Z) <= '0';
  612. end if;
  613. F(Flag_S) <= DI_Reg(7);
  614. F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
  615. DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
  616. end if;
  617. if TState = 1 then
  618. DO <= BusB;
  619. if I_RLD = '1' then
  620. DO(3 downto 0) <= BusA(3 downto 0);
  621. DO(7 downto 4) <= BusB(3 downto 0);
  622. end if;
  623. if I_RRD = '1' then
  624. DO(3 downto 0) <= BusB(7 downto 4);
  625. DO(7 downto 4) <= BusA(3 downto 0);
  626. end if;
  627. end if;
  628. if T_Res = '1' then
  629. Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
  630. Read_To_Reg_r(4) <= Read_To_Reg;
  631. if Read_To_Acc = '1' then
  632. Read_To_Reg_r(3 downto 0) <= "0111";
  633. Read_To_Reg_r(4) <= '1';
  634. end if;
  635. end if;
  636. if TState = 1 and I_BT = '1' then
  637. F(Flag_X) <= ALU_Q(3);
  638. F(Flag_Y) <= ALU_Q(1);
  639. F(Flag_H) <= '0';
  640. F(Flag_N) <= '0';
  641. end if;
  642. if I_BC = '1' or I_BT = '1' then
  643. F(Flag_P) <= IncDecZ;
  644. end if;
  645. if (TState = 1 and Save_ALU_r = '0') or
  646. (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
  647. case Read_To_Reg_r is
  648. when "10111" =>
  649. ACC <= Save_Mux;
  650. when "10110" =>
  651. DO <= Save_Mux;
  652. when "11000" =>
  653. SP(7 downto 0) <= unsigned(Save_Mux);
  654. when "11001" =>
  655. SP(15 downto 8) <= unsigned(Save_Mux);
  656. when "11011" =>
  657. F <= Save_Mux;
  658. when others =>
  659. end case;
  660. if XYbit_undoc='1' then
  661. DO <= ALU_Q;
  662. end if;
  663. end if;
  664. end if;
  665. end if;
  666. end process;
  667. ---------------------------------------------------------------------------
  668. --
  669. -- BC('), DE('), HL('), IX and IY
  670. --
  671. ---------------------------------------------------------------------------
  672. process (CLK_n)
  673. begin
  674. if CLK_n'event and CLK_n = '1' then
  675. if ClkEn = '1' then
  676. -- Bus A / Write
  677. RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
  678. if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
  679. RegAddrA_r <= XY_State(1) & "11";
  680. end if;
  681. -- Bus B
  682. RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
  683. if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
  684. RegAddrB_r <= XY_State(1) & "11";
  685. end if;
  686. -- Address from register
  687. RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
  688. -- Jump (HL), LD SP,HL
  689. if (JumpXY = '1' or LDSPHL = '1') then
  690. RegAddrC <= Alternate & "10";
  691. end if;
  692. if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
  693. RegAddrC <= XY_State(1) & "11";
  694. end if;
  695. if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
  696. IncDecZ <= F_Out(Flag_Z);
  697. end if;
  698. if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
  699. if ID16 = 0 then
  700. IncDecZ <= '0';
  701. else
  702. IncDecZ <= '1';
  703. end if;
  704. end if;
  705. RegBusA_r <= RegBusA;
  706. end if;
  707. end if;
  708. end process;
  709. RegAddrA <=
  710. -- 16 bit increment/decrement
  711. Alternate & IncDec_16(1 downto 0) when (TState = 2 or
  712. (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
  713. XY_State(1) & "11" when (TState = 2 or
  714. (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
  715. -- EX HL,DL
  716. Alternate & "10" when ExchangeDH = '1' and TState = 3 else
  717. Alternate & "01" when ExchangeDH = '1' and TState = 4 else
  718. -- Bus A / Write
  719. RegAddrA_r;
  720. RegAddrB <=
  721. -- EX HL,DL
  722. Alternate & "01" when ExchangeDH = '1' and TState = 3 else
  723. -- Bus B
  724. RegAddrB_r;
  725. ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
  726. signed(RegBusA) + 1;
  727. process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
  728. ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
  729. begin
  730. RegWEH <= '0';
  731. RegWEL <= '0';
  732. if (TState = 1 and Save_ALU_r = '0') or
  733. (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
  734. case Read_To_Reg_r is
  735. when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
  736. RegWEH <= not Read_To_Reg_r(0);
  737. RegWEL <= Read_To_Reg_r(0);
  738. when others =>
  739. end case;
  740. end if;
  741. if ExchangeDH = '1' and (TState = 3 or TState = 4) then
  742. RegWEH <= '1';
  743. RegWEL <= '1';
  744. end if;
  745. if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
  746. case IncDec_16(1 downto 0) is
  747. when "00" | "01" | "10" =>
  748. RegWEH <= '1';
  749. RegWEL <= '1';
  750. when others =>
  751. end case;
  752. end if;
  753. end process;
  754. process (Save_Mux, RegBusB, RegBusA_r, ID16,
  755. ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
  756. begin
  757. RegDIH <= Save_Mux;
  758. RegDIL <= Save_Mux;
  759. if ExchangeDH = '1' and TState = 3 then
  760. RegDIH <= RegBusB(15 downto 8);
  761. RegDIL <= RegBusB(7 downto 0);
  762. end if;
  763. if ExchangeDH = '1' and TState = 4 then
  764. RegDIH <= RegBusA_r(15 downto 8);
  765. RegDIL <= RegBusA_r(7 downto 0);
  766. end if;
  767. if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
  768. RegDIH <= std_logic_vector(ID16(15 downto 8));
  769. RegDIL <= std_logic_vector(ID16(7 downto 0));
  770. end if;
  771. end process;
  772. Regs : T80_Reg
  773. port map(
  774. Clk => CLK_n,
  775. CEN => ClkEn,
  776. WEH => RegWEH,
  777. WEL => RegWEL,
  778. AddrA => RegAddrA,
  779. AddrB => RegAddrB,
  780. AddrC => RegAddrC,
  781. DIH => RegDIH,
  782. DIL => RegDIL,
  783. DOAH => RegBusA(15 downto 8),
  784. DOAL => RegBusA(7 downto 0),
  785. DOBH => RegBusB(15 downto 8),
  786. DOBL => RegBusB(7 downto 0),
  787. DOCH => RegBusC(15 downto 8),
  788. DOCL => RegBusC(7 downto 0));
  789. ---------------------------------------------------------------------------
  790. --
  791. -- Buses
  792. --
  793. ---------------------------------------------------------------------------
  794. process (CLK_n)
  795. begin
  796. if CLK_n'event and CLK_n = '1' then
  797. if ClkEn = '1' then
  798. case Set_BusB_To is
  799. when "0111" =>
  800. BusB <= ACC;
  801. when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
  802. if Set_BusB_To(0) = '1' then
  803. BusB <= RegBusB(7 downto 0);
  804. else
  805. BusB <= RegBusB(15 downto 8);
  806. end if;
  807. when "0110" =>
  808. BusB <= DI_Reg;
  809. when "1000" =>
  810. BusB <= std_logic_vector(SP(7 downto 0));
  811. when "1001" =>
  812. BusB <= std_logic_vector(SP(15 downto 8));
  813. when "1010" =>
  814. BusB <= "00000001";
  815. when "1011" =>
  816. BusB <= F;
  817. when "1100" =>
  818. BusB <= std_logic_vector(PC(7 downto 0));
  819. when "1101" =>
  820. BusB <= std_logic_vector(PC(15 downto 8));
  821. when "1110" =>
  822. BusB <= "00000000";
  823. when others =>
  824. BusB <= "--------";
  825. end case;
  826. case Set_BusA_To is
  827. when "0111" =>
  828. BusA <= ACC;
  829. when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
  830. if Set_BusA_To(0) = '1' then
  831. BusA <= RegBusA(7 downto 0);
  832. else
  833. BusA <= RegBusA(15 downto 8);
  834. end if;
  835. when "0110" =>
  836. BusA <= DI_Reg;
  837. when "1000" =>
  838. BusA <= std_logic_vector(SP(7 downto 0));
  839. when "1001" =>
  840. BusA <= std_logic_vector(SP(15 downto 8));
  841. when "1010" =>
  842. BusA <= "00000000";
  843. when others =>
  844. BusB <= "--------";
  845. end case;
  846. if XYbit_undoc='1' then
  847. BusA <= DI_Reg;
  848. BusB <= DI_Reg;
  849. end if;
  850. end if;
  851. end if;
  852. end process;
  853. ---------------------------------------------------------------------------
  854. --
  855. -- Generate external control signals
  856. --
  857. ---------------------------------------------------------------------------
  858. process (RESET_n,CLK_n)
  859. begin
  860. if RESET_n = '0' then
  861. RFSH_n <= '1';
  862. elsif CLK_n'event and CLK_n = '1' then
  863. if CEN = '1' then
  864. if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
  865. RFSH_n <= '0';
  866. else
  867. RFSH_n <= '1';
  868. end if;
  869. end if;
  870. end if;
  871. end process;
  872. MC <= std_logic_vector(MCycle);
  873. TS <= std_logic_vector(TState);
  874. DI_Reg <= DI;
  875. HALT_n <= not Halt_FF;
  876. BUSAK_n <= not BusAck;
  877. IntCycle_n <= not IntCycle;
  878. IntE <= IntE_FF1;
  879. IORQ <= IORQ_i;
  880. Stop <= I_DJNZ;
  881. -------------------------------------------------------------------------
  882. --
  883. -- Syncronise inputs
  884. --
  885. -------------------------------------------------------------------------
  886. process (RESET_n, CLK_n)
  887. variable OldNMI_n : std_logic;
  888. begin
  889. if RESET_n = '0' then
  890. BusReq_s <= '0';
  891. INT_s <= '0';
  892. NMI_s <= '0';
  893. OldNMI_n := '0';
  894. elsif CLK_n'event and CLK_n = '1' then
  895. if CEN = '1' then
  896. BusReq_s <= not BUSRQ_n;
  897. INT_s <= not INT_n;
  898. if NMICycle = '1' then
  899. NMI_s <= '0';
  900. elsif NMI_n = '0' and OldNMI_n = '1' then
  901. NMI_s <= '1';
  902. end if;
  903. OldNMI_n := NMI_n;
  904. end if;
  905. end if;
  906. end process;
  907. -------------------------------------------------------------------------
  908. --
  909. -- Main state machine
  910. --
  911. -------------------------------------------------------------------------
  912. process (RESET_n, CLK_n)
  913. begin
  914. if RESET_n = '0' then
  915. MCycle <= "001";
  916. TState <= "000";
  917. Pre_XY_F_M <= "000";
  918. Halt_FF <= '0';
  919. BusAck <= '0';
  920. NMICycle <= '0';
  921. IntCycle <= '0';
  922. IntE_FF1 <= '0';
  923. IntE_FF2 <= '0';
  924. No_BTR <= '0';
  925. Auto_Wait_t1 <= '0';
  926. Auto_Wait_t2 <= '0';
  927. M1_n <= '1';
  928. elsif CLK_n'event and CLK_n = '1' then
  929. if CEN = '1' then
  930. Auto_Wait_t1 <= Auto_Wait;
  931. Auto_Wait_t2 <= Auto_Wait_t1;
  932. No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
  933. (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
  934. (I_BTR and (not IR(4) or F(Flag_Z)));
  935. if TState = 2 then
  936. if SetEI = '1' then
  937. IntE_FF1 <= '1';
  938. IntE_FF2 <= '1';
  939. end if;
  940. if I_RETN = '1' then
  941. IntE_FF1 <= IntE_FF2;
  942. end if;
  943. end if;
  944. if TState = 3 then
  945. if SetDI = '1' then
  946. IntE_FF1 <= '0';
  947. IntE_FF2 <= '0';
  948. end if;
  949. end if;
  950. if IntCycle = '1' or NMICycle = '1' then
  951. Halt_FF <= '0';
  952. end if;
  953. if MCycle = "001" and TState = 2 and Wait_n = '1' then
  954. M1_n <= '1';
  955. end if;
  956. if BusReq_s = '1' and BusAck = '1' then
  957. else
  958. BusAck <= '0';
  959. if TState = 2 and Wait_n = '0' then
  960. elsif T_Res = '1' then
  961. if Halt = '1' then
  962. Halt_FF <= '1';
  963. end if;
  964. if BusReq_s = '1' then
  965. BusAck <= '1';
  966. else
  967. TState <= "001";
  968. if NextIs_XY_Fetch = '1' then
  969. MCycle <= "110";
  970. Pre_XY_F_M <= MCycle;
  971. if IR = "00110110" and Mode = 0 then
  972. Pre_XY_F_M <= "010";
  973. end if;
  974. elsif (MCycle = "111") or
  975. (MCycle = "110" and Mode = 1 and ISet /= "01") then
  976. MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
  977. elsif (MCycle = MCycles) or
  978. No_BTR = '1' or
  979. (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
  980. M1_n <= '0';
  981. MCycle <= "001";
  982. IntCycle <= '0';
  983. NMICycle <= '0';
  984. if NMI_s = '1' and Prefix = "00" then
  985. NMICycle <= '1';
  986. IntE_FF1 <= '0';
  987. elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
  988. IntCycle <= '1';
  989. IntE_FF1 <= '0';
  990. IntE_FF2 <= '0';
  991. end if;
  992. else
  993. MCycle <= std_logic_vector(unsigned(MCycle) + 1);
  994. end if;
  995. end if;
  996. else
  997. if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
  998. TState <= TState + 1;
  999. end if;
  1000. end if;
  1001. end if;
  1002. if TState = 0 then
  1003. M1_n <= '0';
  1004. end if;
  1005. end if;
  1006. end if;
  1007. end process;
  1008. process (IntCycle, NMICycle, MCycle)
  1009. begin
  1010. Auto_Wait <= '0';
  1011. if IntCycle = '1' or NMICycle = '1' then
  1012. if MCycle = "001" then
  1013. Auto_Wait <= '1';
  1014. end if;
  1015. end if;
  1016. end process;
  1017. end;