SSRAM.vhd 2.9 KB

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  1. --
  2. -- Inferrable Synchronous SRAM for XST synthesis
  3. --
  4. -- Version : 0220
  5. --
  6. -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
  7. --
  8. -- All rights reserved
  9. --
  10. -- Redistribution and use in source and synthezised forms, with or without
  11. -- modification, are permitted provided that the following conditions are met:
  12. --
  13. -- Redistributions of source code must retain the above copyright notice,
  14. -- this list of conditions and the following disclaimer.
  15. --
  16. -- Redistributions in synthesized form must reproduce the above copyright
  17. -- notice, this list of conditions and the following disclaimer in the
  18. -- documentation and/or other materials provided with the distribution.
  19. --
  20. -- Neither the name of the author nor the names of other contributors may
  21. -- be used to endorse or promote products derived from this software without
  22. -- specific prior written permission.
  23. --
  24. -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25. -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26. -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27. -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
  28. -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29. -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30. -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31. -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32. -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33. -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34. -- POSSIBILITY OF SUCH DAMAGE.
  35. --
  36. -- Please report bugs to the author, but before you do so, please
  37. -- make sure that this is not a derivative work and that
  38. -- you have the latest version of this file.
  39. --
  40. -- The latest version of this file can be found at:
  41. -- http://www.opencores.org/cvsweb.shtml/t51/
  42. --
  43. -- Limitations :
  44. --
  45. -- File history :
  46. -- 0208 : Initial release
  47. -- 0218 : Fixed data out at write
  48. -- 0220 : Added support for XST
  49. library IEEE;
  50. use IEEE.std_logic_1164.all;
  51. use IEEE.numeric_std.all;
  52. entity SSRAM is
  53. generic(
  54. AddrWidth : integer := 11;
  55. DataWidth : integer := 8
  56. );
  57. port(
  58. clk : in std_logic;
  59. ce : in std_logic;
  60. we : in std_logic;
  61. A : in std_logic_vector(AddrWidth - 1 downto 0);
  62. DIn : in std_logic_vector(DataWidth - 1 downto 0);
  63. DOut : out std_logic_vector(DataWidth - 1 downto 0)
  64. );
  65. end SSRAM;
  66. architecture behaviour of SSRAM is
  67. type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
  68. signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
  69. signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
  70. begin
  71. process (Clk)
  72. begin
  73. if rising_edge(clk) then
  74. if (ce = '1' and we = '1') then
  75. RAM(to_integer(unsigned(A))) <= DIn;
  76. end if;
  77. A_r <= A;
  78. end if;
  79. end process;
  80. DOut <= RAM(to_integer(unsigned(A_r)));
  81. end;