RAM4K36.vhd 2.0 KB

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  1. --+-----------------------------------+-------------------------------------+--
  2. --| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
  3. --| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
  4. --| / __|/ _ \ / __|_ / _ \| | | | | |--
  5. --| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
  6. --| |___/\___/ \___/___\___/ \___/ | |--
  7. --| | http://sowerbutts.com/ |--
  8. --+-----------------------------------+-------------------------------------+--
  9. --| A 4096 entry deep, 36-bit wide RAM using four RAM4K9 devices (and thus |--
  10. --| eight Xilinx RAMB16BWER devices) |--
  11. --+-------------------------------------------------------------------------+--
  12. library IEEE;
  13. use IEEE.std_logic_1164.all;
  14. use IEEE.numeric_std.all;
  15. library UNISIM;
  16. entity RAM4K36 is
  17. port(
  18. clk : in std_logic;
  19. write : in std_logic;
  20. address : in std_logic_vector(11 downto 0);
  21. data_in : in std_logic_vector(35 downto 0);
  22. data_out : out std_logic_vector(35 downto 0)
  23. );
  24. end RAM4K36;
  25. architecture behaviour of RAM4K36 is
  26. begin
  27. ram0: entity work.RAM4K9
  28. port map (
  29. clock => clk,
  30. wren => write,
  31. address => address,
  32. data => data_in(8 downto 0),
  33. q => data_out(8 downto 0)
  34. );
  35. ram1: entity work.RAM4K9
  36. port map (
  37. clock => clk,
  38. wren => write,
  39. address => address,
  40. data => data_in(17 downto 9),
  41. q => data_out(17 downto 9)
  42. );
  43. ram2: entity work.RAM4K9
  44. port map (
  45. clock => clk,
  46. wren => write,
  47. address => address,
  48. data => data_in(26 downto 18),
  49. q => data_out(26 downto 18)
  50. );
  51. ram3: entity work.RAM4K9
  52. port map (
  53. clock => clk,
  54. wren => write,
  55. address => address,
  56. data => data_in(35 downto 27),
  57. q => data_out(35 downto 27)
  58. );
  59. end;