DRAM.vhd 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391
  1. --+-----------------------------------+-------------------------------------+--
  2. --| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
  3. --| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
  4. --| / __|/ _ \ / __|_ / _ \| | | | | |--
  5. --| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
  6. --| |___/\___/ \___/___\___/ \___/ | |--
  7. --| | http://sowerbutts.com/ |--
  8. --+-----------------------------------+-------------------------------------+--
  9. --| DRAM interface: Connect the CPU to the SDRAM on the Papilio Pro board. |--
  10. --| The SDRAM takes about 10 cycles to respond with data after making a |--
  11. --| request, so this module includes a direct-mapped cache to store |--
  12. --| recently read or written data in order to hide this latency. |--
  13. --+-------------------------------------------------------------------------+--
  14. --
  15. -- The Papilio Pro board has an 8MB SDRAM chip on the board. The socz80 MMU
  16. -- provides a 64MB (26-bit) phyiscal address space. The low 32MB of address space
  17. -- is allocated to the DRAM (the top 32MB being used for other memory devices).
  18. --
  19. -- The low 32MB is divided into two 16MB blocks. Accesses to the first block
  20. -- (starting at 0MB) go through the cache, while accesses to the second
  21. -- block (starting at 16MB) bypass the cache. There is only 8MB SDRAM on the
  22. -- Papilio Pro so it is aliased twice in each block, ie it appears at 0MB,
  23. -- 8MB, 16MB and 24MB.
  24. --
  25. -- The cache is direct mapped, ie the low bits of the address dictate which cache
  26. -- line to use and which byte within that line. When a cache line is written to
  27. -- the top bits of the address are stored in "cache tag" memory. When a cache line
  28. -- is read the top bits of the address are compared to the stored tag to determine
  29. -- if the cached data relates to the same address.
  30. --
  31. -- Each cache line consists of a 45 bits:
  32. -- 32 bits of cached data
  33. -- 4 validity bits to indicate if the cached data is valid or not
  34. -- 9 bits of address tag to indicate the top address bits of the
  35. --
  36. -- bit number (read these two 22222211111111110000000000
  37. -- lines top to bottom) 54321098765432109876543210
  38. --
  39. -- CPU address is 16 bits wide: PPPPOOOOOOOOOOOO (4 bit page, 12 bit offset)
  40. -- physical address is 26 bits wide: FFFFFFFFFFFFFFOOOOOOOOOOOO (14 bit frame, 12 bit offset)
  41. -- DRAM address is 25 bits wide: CIFFFFFFFFFFFOOOOOOOOOOOO (1 bit cache flag, 1 bit ignored, 11 bit frame, 12 bit offset)
  42. -- cached address is 23 bits wide: TTTTTTTTTLLLLLLLLLLLLBB (9 bit cache line tag, 12 bit cache line, 2 bit byte offset)
  43. --
  44. -- cache lines use 4096 x 36 bit BRAM
  45. -- cache tags use 4096 x 9 bit BRAM
  46. library IEEE;
  47. use IEEE.std_logic_1164.all;
  48. use IEEE.numeric_std.all;
  49. entity DRAM is
  50. generic(
  51. sdram_address_width : natural;
  52. sdram_column_bits : natural;
  53. sdram_startup_cycles: natural;
  54. cycles_per_refresh : natural
  55. );
  56. port(
  57. -- interface to the system
  58. clk : in std_logic;
  59. reset : in std_logic;
  60. cs : in std_logic;
  61. req_read : in std_logic;
  62. req_write : in std_logic;
  63. mem_address : in std_logic_vector(24 downto 0);
  64. data_in : in std_logic_vector(7 downto 0);
  65. data_out : out std_logic_vector(7 downto 0) := (others => '0');
  66. mem_wait : out std_logic;
  67. coldboot : out std_logic; -- this signals 1 until the SDRAM has been initialised
  68. -- interface to hardware SDRAM chip
  69. SDRAM_CLK : out std_logic;
  70. SDRAM_CKE : out std_logic;
  71. SDRAM_CS : out std_logic;
  72. SDRAM_nRAS : out std_logic;
  73. SDRAM_nCAS : out std_logic;
  74. SDRAM_nWE : out std_logic;
  75. SDRAM_DQM : out std_logic_vector( 1 downto 0);
  76. SDRAM_ADDR : out std_logic_vector (12 downto 0);
  77. SDRAM_BA : out std_logic_vector( 1 downto 0);
  78. SDRAM_DQ : inout std_logic_vector (15 downto 0)
  79. );
  80. end DRAM;
  81. architecture behaviour of DRAM is
  82. -- sdram controller interface
  83. signal cmd_address : std_logic_vector(sdram_address_width-2 downto 0) := (others => '0');
  84. signal cmd_wr : std_logic := '1';
  85. signal cmd_enable : std_logic;
  86. signal cmd_byte_enable : std_logic_vector(3 downto 0);
  87. signal cmd_data_in : std_logic_vector(31 downto 0);
  88. signal cmd_ready : std_logic;
  89. signal sdram_data_out : std_logic_vector(31 downto 0);
  90. signal sdram_data_out_ready : std_logic;
  91. signal seen_ready : std_logic := '0';
  92. signal last_address_word : std_logic_vector(20 downto 0);
  93. -- internal signals
  94. signal current_word : std_logic_vector(31 downto 0); -- value of current cache line
  95. signal current_byte_valid : std_logic_vector(3 downto 0); -- validity bits for current cache line
  96. signal word_changed : std_logic; -- did the address bus value change?
  97. signal cache_hit : std_logic;
  98. signal address_hit : std_logic;
  99. signal byte_valid_hit : std_logic;
  100. signal write_back : std_logic;
  101. -- state machine
  102. type controller_state is ( st_idle, -- waiting for command
  103. st_read, -- cache miss: issued read command to controller, waiting for data to arrive
  104. st_read_done, -- cache hit/completed miss: data arrived from controller, waiting for CPU to de-assert
  105. st_write); -- write: issued write command, waiting for CPU to de-assert
  106. signal current_state : controller_state;
  107. signal next_state : controller_state;
  108. -- here's the cache memory signals
  109. signal cache_line_memory_write_enable : std_logic;
  110. signal cache_line_memory_data_in : std_logic_vector(35 downto 0); -- 35 downto 32: validity bits; 31 downto 0: four data bytes
  111. signal cache_line_memory_data_out : std_logic_vector(35 downto 0);
  112. signal cache_tag_memory_write_enable : std_logic;
  113. signal cache_tag_memory_data_in : std_logic_vector(8 downto 0);
  114. signal cache_tag_memory_data_out : std_logic_vector(8 downto 0);
  115. -- break up the incoming physical address
  116. alias address_byte : std_logic_vector(1 downto 0) is mem_address(1 downto 0);
  117. alias address_line : std_logic_vector(11 downto 0) is mem_address(13 downto 2);
  118. alias address_tag : std_logic_vector(8 downto 0) is mem_address(22 downto 14);
  119. alias address_word : std_logic_vector(20 downto 0) is mem_address(22 downto 2);
  120. -- mem_address(23) and mem_address(24) are unused in this design
  121. alias cache_inhibit : std_logic is mem_address(24);
  122. begin
  123. -- this should be based on the generic, really
  124. cmd_address <= mem_address((sdram_address_width) downto 2); -- address_tag & address_line
  125. cmd_data_in <= data_in & data_in & data_in & data_in; -- write the same data four times
  126. cmd_wr <= req_write;
  127. coldboot <= not seen_ready;
  128. compute_next_state: process(req_read, req_write, current_state, cache_hit, cmd_ready, cs, sdram_data_out_ready, word_changed)
  129. begin
  130. cmd_enable <= '0';
  131. mem_wait <= '0';
  132. write_back <= '0';
  133. case current_state is
  134. when st_idle =>
  135. if cs = '1' and cmd_ready = '1' then
  136. if req_read = '1' then
  137. -- we can't process a read immediately if the address input just changed; delay them for one cycle.
  138. if word_changed = '1' then
  139. mem_wait <= '1';
  140. next_state <= st_idle;
  141. -- come back next cycle!
  142. else
  143. if cache_hit = '1' then
  144. mem_wait <= '0';
  145. next_state <= st_read_done;
  146. else
  147. cmd_enable <= '1';
  148. mem_wait <= '1';
  149. next_state <= st_read;
  150. end if;
  151. end if;
  152. elsif req_write = '1' then
  153. if word_changed = '1' then
  154. mem_wait <= '1';
  155. next_state <= st_idle;
  156. -- come back next cycle!
  157. else
  158. next_state <= st_write;
  159. cmd_enable <= '1';
  160. mem_wait <= '0'; -- no need to wait, the SDRAM controller will latch all the inputs
  161. write_back <= '1';
  162. end if;
  163. else
  164. next_state <= st_idle;
  165. mem_wait <= '0'; -- we know cmd_ready='1'
  166. end if;
  167. else
  168. next_state <= st_idle;
  169. mem_wait <= (not cmd_ready);
  170. end if;
  171. when st_read =>
  172. if cs = '1' and req_read = '1' then
  173. if sdram_data_out_ready = '1' then
  174. next_state <= st_read_done;
  175. else
  176. next_state <= st_read;
  177. end if;
  178. else
  179. -- this kind of implies that they gave up on us?
  180. next_state <= st_idle;
  181. end if;
  182. mem_wait <= (not sdram_data_out_ready) and (not cache_hit);
  183. when st_read_done =>
  184. if cs = '1' and req_read = '1' then
  185. next_state <= st_read_done;
  186. else
  187. next_state <= st_idle;
  188. end if;
  189. mem_wait <= (not sdram_data_out_ready) and (not cache_hit);
  190. when st_write =>
  191. if cs = '1' and req_write = '1' then
  192. next_state <= st_write;
  193. else
  194. next_state <= st_idle;
  195. end if;
  196. mem_wait <= (not cmd_ready); -- no need to wait once the write has been committed
  197. end case;
  198. end process;
  199. word_changed_check: process(last_address_word, address_word)
  200. begin
  201. if address_word = last_address_word then
  202. word_changed <= '0';
  203. else
  204. word_changed <= '1';
  205. end if;
  206. end process;
  207. cache_address_check: process(cache_tag_memory_data_out, cache_line_memory_data_out, address_tag)
  208. begin
  209. if cache_tag_memory_data_out = address_tag then
  210. address_hit <= '1';
  211. current_byte_valid <= cache_line_memory_data_out(35 downto 32);
  212. else
  213. address_hit <= '0';
  214. current_byte_valid <= "0000";
  215. end if;
  216. end process;
  217. cache_byte_valid_check: process(address_byte, current_byte_valid)
  218. begin
  219. case address_byte is
  220. when "00" => byte_valid_hit <= current_byte_valid(0);
  221. when "01" => byte_valid_hit <= current_byte_valid(1);
  222. when "10" => byte_valid_hit <= current_byte_valid(2);
  223. when "11" => byte_valid_hit <= current_byte_valid(3);
  224. when others => byte_valid_hit <= '0';
  225. end case;
  226. end process;
  227. cache_hit_check: process(byte_valid_hit, address_hit, cache_inhibit)
  228. begin
  229. if address_hit = '1' and byte_valid_hit = '1' and cache_inhibit = '0' then
  230. cache_hit <= '1';
  231. else
  232. cache_hit <= '0';
  233. end if;
  234. end process;
  235. byte_enable_decode: process(address_byte)
  236. begin
  237. case address_byte is
  238. when "00" => cmd_byte_enable <= "0001";
  239. when "01" => cmd_byte_enable <= "0010";
  240. when "10" => cmd_byte_enable <= "0100";
  241. when "11" => cmd_byte_enable <= "1000";
  242. when others => cmd_byte_enable <= "1000";
  243. end case;
  244. end process;
  245. data_out_demux: process(address_byte, sdram_data_out_ready, sdram_data_out, cache_line_memory_data_out, current_word)
  246. begin
  247. -- when the SDRAM is presenting data, feed it direct to the CPU.
  248. -- otherwise feed data from our cache memory.
  249. if sdram_data_out_ready = '1' then
  250. current_word <= sdram_data_out;
  251. else
  252. current_word <= cache_line_memory_data_out(31 downto 0);
  253. end if;
  254. case address_byte is
  255. when "00" => data_out <= current_word( 7 downto 0);
  256. when "01" => data_out <= current_word(15 downto 8);
  257. when "10" => data_out <= current_word(23 downto 16);
  258. when "11" => data_out <= current_word(31 downto 24);
  259. when others => data_out <= current_word(31 downto 24);
  260. end case;
  261. end process;
  262. cache_write: process(current_state, data_in, next_state, write_back, cache_line_memory_data_out, sdram_data_out, sdram_data_out_ready, address_byte, current_byte_valid)
  263. begin
  264. if (next_state = st_read) or (write_back = '1') then
  265. cache_tag_memory_write_enable <= '1';
  266. else
  267. cache_tag_memory_write_enable <= '0';
  268. end if;
  269. cache_line_memory_write_enable <= '0';
  270. cache_line_memory_data_in <= cache_line_memory_data_out;
  271. if next_state = st_read then
  272. cache_line_memory_data_in <= (others => '0'); -- set word and all valid flags to 1
  273. cache_line_memory_write_enable <= '1';
  274. end if;
  275. -- has our read completed?
  276. if current_state = st_read then
  277. if sdram_data_out_ready = '1' then
  278. cache_line_memory_data_in <= "1111" & sdram_data_out;
  279. cache_line_memory_write_enable <= '1';
  280. end if;
  281. elsif write_back = '1' then
  282. case address_byte is
  283. when "00" =>
  284. cache_line_memory_data_in <= current_byte_valid(3 downto 1) & "1" &
  285. cache_line_memory_data_out(31 downto 8) & data_in;
  286. when "01" =>
  287. cache_line_memory_data_in <=
  288. current_byte_valid(3 downto 2) & "1" & current_byte_valid(0) &
  289. cache_line_memory_data_out(31 downto 16) & data_in & cache_line_memory_data_out(7 downto 0);
  290. when "10" =>
  291. cache_line_memory_data_in <=
  292. current_byte_valid(3) & "1" & current_byte_valid(1 downto 0) &
  293. cache_line_memory_data_out(31 downto 24) & data_in & cache_line_memory_data_out(15 downto 0);
  294. when "11" =>
  295. cache_line_memory_data_in <=
  296. "1" & current_byte_valid(2 downto 0) &
  297. data_in & cache_line_memory_data_out(23 downto 0);
  298. when others => -- shut up, compiler!
  299. end case;
  300. cache_line_memory_write_enable <= '1';
  301. end if;
  302. end process;
  303. sdram_registers: process(clk)
  304. begin
  305. if rising_edge(clk) then
  306. -- state register
  307. current_state <= next_state;
  308. -- coldboot detection
  309. seen_ready <= seen_ready or cmd_ready;
  310. -- track memory address
  311. last_address_word <= address_word;
  312. end if;
  313. end process;
  314. -- underlying SDRAM controller (thanks, Hamsterworks!)
  315. sdram_ctrl: entity work.SDRAM_Controller
  316. GENERIC MAP(
  317. sdram_address_width => sdram_address_width,
  318. sdram_column_bits => sdram_column_bits,
  319. sdram_startup_cycles=> sdram_startup_cycles,
  320. cycles_per_refresh => cycles_per_refresh
  321. )
  322. PORT MAP(
  323. clk => clk,
  324. reset => reset,
  325. cmd_address => cmd_address,
  326. cmd_wr => cmd_wr,
  327. cmd_enable => cmd_enable,
  328. cmd_ready => cmd_ready,
  329. cmd_byte_enable => cmd_byte_enable,
  330. cmd_data_in => cmd_data_in,
  331. data_out => sdram_data_out,
  332. data_out_ready => sdram_data_out_ready,
  333. SDRAM_CLK => SDRAM_CLK,
  334. SDRAM_CKE => SDRAM_CKE,
  335. SDRAM_CS => SDRAM_CS,
  336. SDRAM_RAS => SDRAM_nRAS,
  337. SDRAM_CAS => SDRAM_nCAS,
  338. SDRAM_WE => SDRAM_nWE,
  339. SDRAM_DQM => SDRAM_DQM,
  340. SDRAM_BA => SDRAM_BA,
  341. SDRAM_ADDR => SDRAM_ADDR,
  342. SDRAM_DATA => SDRAM_DQ
  343. );
  344. -- block RAM used to store cache line data and byte validity (packs nicely into 36 bits)
  345. cacheline_memory_sram: entity work.RAM4K36
  346. port map (
  347. clk => clk,
  348. write => cache_line_memory_write_enable,
  349. address => address_line,
  350. data_in => cache_line_memory_data_in,
  351. data_out => cache_line_memory_data_out
  352. );
  353. -- block RAM used to store cache line tag memory (packs nicely into 9 bits)
  354. cachetag_memory_sram: entity work.RAM4K9
  355. port map (
  356. clock => clk,
  357. wren => cache_tag_memory_write_enable,
  358. address => address_line,
  359. data => cache_tag_memory_data_in,
  360. q => cache_tag_memory_data_out
  361. );
  362. end;