DRAM.vhd 13 KB

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  1. --+-----------------------------------+-------------------------------------+--
  2. --| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
  3. --| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
  4. --| / __|/ _ \ / __|_ / _ \| | | | | |--
  5. --| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
  6. --| |___/\___/ \___/___\___/ \___/ | |--
  7. --| | http://sowerbutts.com/ |--
  8. --+-----------------------------------+-------------------------------------+--
  9. --| DRAM interface: Connect the CPU to the SDRAM on the Papilio Pro board. |--
  10. --| The SDRAM takes about 10 cycles to respond with data after making a |--
  11. --| request, so this module includes a direct-mapped cache to store |--
  12. --| recently read or written data in order to hide this latency. |--
  13. --+-------------------------------------------------------------------------+--
  14. --
  15. -- The Papilio Pro board has an 8MB SDRAM chip on the board. The socz80 MMU
  16. -- provides a 64MB (26-bit) phyiscal address space. The low 32MB of address space
  17. -- is allocated to the DRAM (the top 32MB being used for other memory devices).
  18. --
  19. -- The low 32MB is divided into two 16MB blocks. Accesses to the first block
  20. -- (starting at 0MB) go through the cache, while accesses to the second
  21. -- block (starting at 16MB) bypass the cache. There is only 8MB SDRAM on the
  22. -- Papilio Pro so it is aliased twice in each block, ie it appears at 0MB,
  23. -- 8MB, 16MB and 24MB.
  24. --
  25. -- The cache is direct mapped, ie the low bits of the address dictate which cache
  26. -- line to use and which byte within that line. When a cache line is written to
  27. -- the top bits of the address are stored in "cache tag" memory. When a cache line
  28. -- is read the top bits of the address are compared to the stored tag to determine
  29. -- if the cached data relates to the same address.
  30. --
  31. -- Each cache line consists of a 45 bits:
  32. -- 32 bits of cached data
  33. -- 4 validity bits to indicate if the cached data is valid or not
  34. -- 9 bits of address tag to indicate the top address bits of the
  35. --
  36. -- bit number (read these two 22222211111111110000000000
  37. -- lines top to bottom) 54321098765432109876543210
  38. --
  39. -- CPU address is 16 bits wide: PPPPOOOOOOOOOOOO (4 bit page, 12 bit offset)
  40. -- physical address is 26 bits wide: FFFFFFFFFFFFFFOOOOOOOOOOOO (14 bit frame, 12 bit offset)
  41. -- DRAM address is 25 bits wide: CIFFFFFFFFFFFOOOOOOOOOOOO (1 bit cache flag, 1 bit ignored, 11 bit frame, 12 bit offset)
  42. -- cached address is 23 bits wide: TTTTTTTTTLLLLLLLLLLLLBB (9 bit cache line tag, 12 bit cache line, 2 bit byte offset)
  43. --
  44. -- cache lines use 4096 x 36 bit BRAM
  45. -- cache tags use 4096 x 9 bit BRAM
  46. library IEEE;
  47. use IEEE.std_logic_1164.all;
  48. use IEEE.numeric_std.all;
  49. entity DRAM is
  50. generic(
  51. sdram_address_width : natural;
  52. sdram_column_bits : natural;
  53. sdram_startup_cycles: natural;
  54. cycles_per_refresh : natural
  55. );
  56. port(
  57. -- interface to the system
  58. clk : in std_logic;
  59. reset : in std_logic;
  60. cs : in std_logic;
  61. req_read : in std_logic;
  62. req_write : in std_logic;
  63. mem_address : in std_logic_vector(24 downto 0);
  64. data_in : in std_logic_vector(7 downto 0);
  65. data_out : out std_logic_vector(7 downto 0) := (others => '0');
  66. mem_wait : out std_logic;
  67. coldboot : out std_logic; -- this signals 1 until the SDRAM has been initialised
  68. -- interface to hardware SDRAM chip
  69. SDRAM_CLK : out std_logic;
  70. SDRAM_CKE : out std_logic;
  71. SDRAM_CS : out std_logic;
  72. SDRAM_nRAS : out std_logic;
  73. SDRAM_nCAS : out std_logic;
  74. SDRAM_nWE : out std_logic;
  75. SDRAM_DQM : out std_logic_vector( 1 downto 0);
  76. SDRAM_ADDR : out std_logic_vector (12 downto 0);
  77. SDRAM_BA : out std_logic_vector( 1 downto 0);
  78. SDRAM_DQ : inout std_logic_vector (15 downto 0)
  79. );
  80. end DRAM;
  81. architecture behaviour of DRAM is
  82. -- sdram controller interface
  83. signal cmd_address : std_logic_vector(sdram_address_width-2 downto 0) := (others => '0');
  84. signal cmd_wr : std_logic := '1';
  85. signal cmd_enable : std_logic;
  86. signal cmd_byte_enable : std_logic_vector(3 downto 0);
  87. signal cmd_data_in : std_logic_vector(31 downto 0);
  88. signal cmd_ready : std_logic;
  89. signal sdram_data_out : std_logic_vector(31 downto 0);
  90. signal sdram_data_out_ready : std_logic;
  91. signal seen_ready : std_logic := '0';
  92. signal last_address_word : std_logic_vector(20 downto 0);
  93. -- internal signals
  94. signal current_word : std_logic_vector(31 downto 0); -- value of current cache line
  95. signal current_byte_valid : std_logic_vector(3 downto 0); -- validity bits for current cache line
  96. signal word_changed : std_logic; -- did the address bus value change?
  97. signal cache_hit : std_logic;
  98. signal address_hit : std_logic;
  99. signal byte_valid_hit : std_logic;
  100. signal write_back : std_logic;
  101. -- state machine
  102. type controller_state is ( st_idle, -- waiting for command
  103. st_read, -- cache miss: issued read command to controller, waiting for data to arrive
  104. st_read_done, -- cache hit/completed miss: data arrived from controller, waiting for CPU to de-assert
  105. st_write); -- write: issued write command, waiting for CPU to de-assert
  106. signal current_state : controller_state;
  107. signal next_state : controller_state;
  108. -- break up the incoming physical address
  109. alias address_byte : std_logic_vector(1 downto 0) is mem_address(1 downto 0);
  110. alias address_line : std_logic_vector(11 downto 0) is mem_address(13 downto 2);
  111. alias address_tag : std_logic_vector(8 downto 0) is mem_address(22 downto 14);
  112. alias address_word : std_logic_vector(20 downto 0) is mem_address(22 downto 2);
  113. -- mem_address(23) and mem_address(24) are unused in this design
  114. begin
  115. -- this should be based on the generic, really
  116. cmd_address <= '0' & '0' & mem_address(22 downto 2); -- address_tag & address_line
  117. cmd_data_in <= data_in & data_in & data_in & data_in; -- write the same data four times
  118. cmd_wr <= req_write;
  119. coldboot <= not seen_ready;
  120. compute_next_state: process(req_read, req_write, current_state, cache_hit, cmd_ready, cs, sdram_data_out_ready, word_changed)
  121. begin
  122. cmd_enable <= '0';
  123. mem_wait <= '0';
  124. write_back <= '0';
  125. case current_state is
  126. when st_idle =>
  127. if cs = '1' and cmd_ready = '1' then
  128. if req_read = '1' then
  129. -- we can't process a read immediately if the address input just changed; delay them for one cycle.
  130. if word_changed = '1' then
  131. mem_wait <= '1';
  132. next_state <= st_idle;
  133. -- come back next cycle!
  134. else
  135. cmd_enable <= '1';
  136. mem_wait <= '1';
  137. next_state <= st_read;
  138. end if;
  139. elsif req_write = '1' then
  140. if word_changed = '1' then
  141. mem_wait <= '1';
  142. next_state <= st_idle;
  143. -- come back next cycle!
  144. else
  145. next_state <= st_write;
  146. cmd_enable <= '1';
  147. mem_wait <= '0'; -- no need to wait, the SDRAM controller will latch all the inputs
  148. write_back <= '1';
  149. end if;
  150. else
  151. next_state <= st_idle;
  152. mem_wait <= '0'; -- we know cmd_ready='1'
  153. end if;
  154. else
  155. next_state <= st_idle;
  156. mem_wait <= (not cmd_ready);
  157. end if;
  158. when st_read =>
  159. if cs = '1' and req_read = '1' then
  160. if sdram_data_out_ready = '1' then
  161. next_state <= st_read_done;
  162. else
  163. next_state <= st_read;
  164. end if;
  165. else
  166. -- this kind of implies that they gave up on us?
  167. next_state <= st_idle;
  168. end if;
  169. mem_wait <= (not sdram_data_out_ready);
  170. when st_read_done =>
  171. if cs = '1' and req_read = '1' then
  172. next_state <= st_read_done;
  173. else
  174. next_state <= st_idle;
  175. end if;
  176. mem_wait <= (not sdram_data_out_ready);
  177. when st_write =>
  178. if cs = '1' and req_write = '1' then
  179. next_state <= st_write;
  180. else
  181. next_state <= st_idle;
  182. end if;
  183. mem_wait <= (not cmd_ready); -- no need to wait once the write has been committed
  184. end case;
  185. end process;
  186. word_changed_check: process(last_address_word, address_word)
  187. begin
  188. if address_word = last_address_word then
  189. word_changed <= '0';
  190. else
  191. word_changed <= '1';
  192. end if;
  193. end process;
  194. byte_enable_decode: process(address_byte)
  195. begin
  196. case address_byte is
  197. when "00" => cmd_byte_enable <= "0001";
  198. when "01" => cmd_byte_enable <= "0010";
  199. when "10" => cmd_byte_enable <= "0100";
  200. when "11" => cmd_byte_enable <= "1000";
  201. when others => cmd_byte_enable <= "1000";
  202. end case;
  203. end process;
  204. data_out_demux: process(address_byte, sdram_data_out_ready, sdram_data_out, current_word)
  205. begin
  206. -- when the SDRAM is presenting data, feed it direct to the CPU.
  207. -- otherwise feed data from our cache memory.
  208. if sdram_data_out_ready = '1' then
  209. current_word <= sdram_data_out;
  210. else
  211. current_word <= (others => '0');
  212. end if;
  213. case address_byte is
  214. when "00" => data_out <= current_word( 7 downto 0);
  215. when "01" => data_out <= current_word(15 downto 8);
  216. when "10" => data_out <= current_word(23 downto 16);
  217. when "11" => data_out <= current_word(31 downto 24);
  218. when others => data_out <= current_word(31 downto 24);
  219. end case;
  220. end process;
  221. sdram_registers: process(clk)
  222. begin
  223. if rising_edge(clk) then
  224. -- state register
  225. current_state <= next_state;
  226. -- coldboot detection
  227. seen_ready <= seen_ready or cmd_ready;
  228. -- track memory address
  229. last_address_word <= address_word;
  230. end if;
  231. end process;
  232. -- underlying SDRAM controller (thanks, Hamsterworks!)
  233. sdram_ctrl: entity work.SDRAM_Controller
  234. GENERIC MAP(
  235. sdram_address_width => sdram_address_width,
  236. sdram_column_bits => sdram_column_bits,
  237. sdram_startup_cycles=> sdram_startup_cycles,
  238. cycles_per_refresh => cycles_per_refresh
  239. )
  240. PORT MAP(
  241. clk => clk,
  242. reset => reset,
  243. cmd_address => cmd_address,
  244. cmd_wr => cmd_wr,
  245. cmd_enable => cmd_enable,
  246. cmd_ready => cmd_ready,
  247. cmd_byte_enable => cmd_byte_enable,
  248. cmd_data_in => cmd_data_in,
  249. data_out => sdram_data_out,
  250. data_out_ready => sdram_data_out_ready,
  251. SDRAM_CLK => SDRAM_CLK,
  252. SDRAM_CKE => SDRAM_CKE,
  253. SDRAM_CS => SDRAM_CS,
  254. SDRAM_RAS => SDRAM_nRAS,
  255. SDRAM_CAS => SDRAM_nCAS,
  256. SDRAM_WE => SDRAM_nWE,
  257. SDRAM_DQM => SDRAM_DQM,
  258. SDRAM_BA => SDRAM_BA,
  259. SDRAM_ADDR => SDRAM_ADDR,
  260. SDRAM_DATA => SDRAM_DQ
  261. );
  262. end;