T80_Pack.vhd 8.2 KB

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  1. -- ****
  2. -- T80(b) core. In an effort to merge and maintain bug fixes ....
  3. --
  4. --
  5. -- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
  6. -- Ver 300 started tidyup
  7. -- MikeJ March 2005
  8. -- Latest version from www.fpgaarcade.com (original www.opencores.org)
  9. --
  10. -- ****
  11. --
  12. -- Z80 compatible microprocessor core
  13. --
  14. -- Version : 0242
  15. --
  16. -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
  17. --
  18. -- All rights reserved
  19. --
  20. -- Redistribution and use in source and synthezised forms, with or without
  21. -- modification, are permitted provided that the following conditions are met:
  22. --
  23. -- Redistributions of source code must retain the above copyright notice,
  24. -- this list of conditions and the following disclaimer.
  25. --
  26. -- Redistributions in synthesized form must reproduce the above copyright
  27. -- notice, this list of conditions and the following disclaimer in the
  28. -- documentation and/or other materials provided with the distribution.
  29. --
  30. -- Neither the name of the author nor the names of other contributors may
  31. -- be used to endorse or promote products derived from this software without
  32. -- specific prior written permission.
  33. --
  34. -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  35. -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  36. -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  37. -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
  38. -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  39. -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  40. -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  41. -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  42. -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  43. -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  44. -- POSSIBILITY OF SUCH DAMAGE.
  45. --
  46. -- Please report bugs to the author, but before you do so, please
  47. -- make sure that this is not a derivative work and that
  48. -- you have the latest version of this file.
  49. --
  50. -- The latest version of this file can be found at:
  51. -- http://www.opencores.org/cvsweb.shtml/t80/
  52. --
  53. -- Limitations :
  54. --
  55. -- File history :
  56. --
  57. library IEEE;
  58. use IEEE.std_logic_1164.all;
  59. package T80_Pack is
  60. component T80
  61. generic(
  62. Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
  63. IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
  64. Flag_C : integer := 0;
  65. Flag_N : integer := 1;
  66. Flag_P : integer := 2;
  67. Flag_X : integer := 3;
  68. Flag_H : integer := 4;
  69. Flag_Y : integer := 5;
  70. Flag_Z : integer := 6;
  71. Flag_S : integer := 7
  72. );
  73. port(
  74. RESET_n : in std_logic;
  75. CLK_n : in std_logic;
  76. CEN : in std_logic;
  77. WAIT_n : in std_logic;
  78. INT_n : in std_logic;
  79. NMI_n : in std_logic;
  80. BUSRQ_n : in std_logic;
  81. M1_n : out std_logic;
  82. IORQ : out std_logic;
  83. NoRead : out std_logic;
  84. Write : out std_logic;
  85. RFSH_n : out std_logic;
  86. HALT_n : out std_logic;
  87. BUSAK_n : out std_logic;
  88. A : out std_logic_vector(15 downto 0);
  89. DInst : in std_logic_vector(7 downto 0);
  90. DI : in std_logic_vector(7 downto 0);
  91. DO : out std_logic_vector(7 downto 0);
  92. MC : out std_logic_vector(2 downto 0);
  93. TS : out std_logic_vector(2 downto 0);
  94. IntCycle_n : out std_logic;
  95. IntE : out std_logic;
  96. Stop : out std_logic
  97. );
  98. end component;
  99. component T80_Reg
  100. port(
  101. Clk : in std_logic;
  102. CEN : in std_logic;
  103. WEH : in std_logic;
  104. WEL : in std_logic;
  105. AddrA : in std_logic_vector(2 downto 0);
  106. AddrB : in std_logic_vector(2 downto 0);
  107. AddrC : in std_logic_vector(2 downto 0);
  108. DIH : in std_logic_vector(7 downto 0);
  109. DIL : in std_logic_vector(7 downto 0);
  110. DOAH : out std_logic_vector(7 downto 0);
  111. DOAL : out std_logic_vector(7 downto 0);
  112. DOBH : out std_logic_vector(7 downto 0);
  113. DOBL : out std_logic_vector(7 downto 0);
  114. DOCH : out std_logic_vector(7 downto 0);
  115. DOCL : out std_logic_vector(7 downto 0)
  116. );
  117. end component;
  118. component T80_MCode
  119. generic(
  120. Mode : integer := 0;
  121. Flag_C : integer := 0;
  122. Flag_N : integer := 1;
  123. Flag_P : integer := 2;
  124. Flag_X : integer := 3;
  125. Flag_H : integer := 4;
  126. Flag_Y : integer := 5;
  127. Flag_Z : integer := 6;
  128. Flag_S : integer := 7
  129. );
  130. port(
  131. IR : in std_logic_vector(7 downto 0);
  132. ISet : in std_logic_vector(1 downto 0);
  133. MCycle : in std_logic_vector(2 downto 0);
  134. F : in std_logic_vector(7 downto 0);
  135. NMICycle : in std_logic;
  136. IntCycle : in std_logic;
  137. XY_State : in std_logic_vector(1 downto 0);
  138. MCycles : out std_logic_vector(2 downto 0);
  139. TStates : out std_logic_vector(2 downto 0);
  140. Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
  141. Inc_PC : out std_logic;
  142. Inc_WZ : out std_logic;
  143. IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
  144. Read_To_Reg : out std_logic;
  145. Read_To_Acc : out std_logic;
  146. Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
  147. Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
  148. ALU_Op : out std_logic_vector(3 downto 0);
  149. -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
  150. Save_ALU : out std_logic;
  151. PreserveC : out std_logic;
  152. Arith16 : out std_logic;
  153. Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
  154. IORQ : out std_logic;
  155. Jump : out std_logic;
  156. JumpE : out std_logic;
  157. JumpXY : out std_logic;
  158. Call : out std_logic;
  159. RstP : out std_logic;
  160. LDZ : out std_logic;
  161. LDW : out std_logic;
  162. LDSPHL : out std_logic;
  163. Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
  164. ExchangeDH : out std_logic;
  165. ExchangeRp : out std_logic;
  166. ExchangeAF : out std_logic;
  167. ExchangeRS : out std_logic;
  168. I_DJNZ : out std_logic;
  169. I_CPL : out std_logic;
  170. I_CCF : out std_logic;
  171. I_SCF : out std_logic;
  172. I_RETN : out std_logic;
  173. I_BT : out std_logic;
  174. I_BC : out std_logic;
  175. I_BTR : out std_logic;
  176. I_RLD : out std_logic;
  177. I_RRD : out std_logic;
  178. I_INRC : out std_logic;
  179. SetDI : out std_logic;
  180. SetEI : out std_logic;
  181. IMode : out std_logic_vector(1 downto 0);
  182. Halt : out std_logic;
  183. NoRead : out std_logic;
  184. Write : out std_logic;
  185. XYbit_undoc : out std_logic
  186. );
  187. end component;
  188. component T80_ALU
  189. generic(
  190. Mode : integer := 0;
  191. Flag_C : integer := 0;
  192. Flag_N : integer := 1;
  193. Flag_P : integer := 2;
  194. Flag_X : integer := 3;
  195. Flag_H : integer := 4;
  196. Flag_Y : integer := 5;
  197. Flag_Z : integer := 6;
  198. Flag_S : integer := 7
  199. );
  200. port(
  201. Arith16 : in std_logic;
  202. Z16 : in std_logic;
  203. ALU_Op : in std_logic_vector(3 downto 0);
  204. IR : in std_logic_vector(5 downto 0);
  205. ISet : in std_logic_vector(1 downto 0);
  206. BusA : in std_logic_vector(7 downto 0);
  207. BusB : in std_logic_vector(7 downto 0);
  208. F_In : in std_logic_vector(7 downto 0);
  209. Q : out std_logic_vector(7 downto 0);
  210. F_Out : out std_logic_vector(7 downto 0)
  211. );
  212. end component;
  213. end;