SDRAM_Controller.vhd 24 KB

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  1. ----------------------------------------------------------------------------------
  2. -- Engineer: Mike Field <hamster@snap.net.nz>
  3. --
  4. -- Create Date: 14:09:12 09/15/2013
  5. -- Module Name: SDRAM_Controller - Behavioral
  6. -- Description: Simple SDRAM controller for a Micron 48LC16M16A2-7E
  7. -- or Micron 48LC4M16A2-7E @ 100MHz
  8. -- Revision:
  9. -- Revision 0.1 - Initial version
  10. -- Revision 0.2 - Removed second clock signal that isn't needed.
  11. -- Revision 0.3 - Added back-to-back reads and writes.
  12. -- Revision 0.4 - Allow refeshes to be delayed till next PRECHARGE is issued,
  13. -- Unless they get really, really delayed. If a delay occurs multiple
  14. -- refreshes might get pushed out, but it will have avioded about
  15. -- 50% of the refresh overhead
  16. -- Revision 0.5 - Add more paramaters to the design, allowing it to work for both the
  17. -- Papilio Pro and Logi-Pi
  18. --
  19. -- Worst case performance (single accesses to different rows or banks) is:
  20. -- Writes 16 cycles = 6,250,000 writes/sec = 25.0MB/s (excluding refresh overhead)
  21. -- Reads 17 cycles = 5,882,352 reads/sec = 23.5MB/s (excluding refresh overhead)
  22. --
  23. -- For 1:1 mixed reads and writes into the same row it is around 88MB/s
  24. -- For reads or wries to the same it is can be as high as 184MB/s
  25. ----------------------------------------------------------------------------------
  26. library IEEE;
  27. use IEEE.STD_LOGIC_1164.ALL;
  28. library UNISIM;
  29. use UNISIM.VComponents.all;
  30. use IEEE.NUMERIC_STD.ALL;
  31. entity SDRAM_Controller is
  32. generic (
  33. sdram_address_width : natural;
  34. sdram_column_bits : natural;
  35. sdram_startup_cycles: natural;
  36. cycles_per_refresh : natural
  37. );
  38. Port ( clk : in STD_LOGIC;
  39. reset : in STD_LOGIC;
  40. -- Interface to issue reads or write data
  41. cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
  42. cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
  43. cmd_wr : in STD_LOGIC; -- Is this a write?
  44. cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
  45. cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
  46. cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
  47. data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
  48. data_out_ready : out STD_LOGIC; -- is new data ready?
  49. -- SDRAM signals
  50. SDRAM_CLK : out STD_LOGIC;
  51. SDRAM_CKE : out STD_LOGIC;
  52. SDRAM_CS : out STD_LOGIC;
  53. SDRAM_RAS : out STD_LOGIC;
  54. SDRAM_CAS : out STD_LOGIC;
  55. SDRAM_WE : out STD_LOGIC;
  56. SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
  57. SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
  58. SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
  59. SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0));
  60. end SDRAM_Controller;
  61. architecture Behavioral of SDRAM_Controller is
  62. -- From page 37 of MT48LC16M16A2 datasheet
  63. -- Name (Function) CS# RAS# CAS# WE# DQM Addr Data
  64. -- COMMAND INHIBIT (NOP) H X X X X X X
  65. -- NO OPERATION (NOP) L H H H X X X
  66. -- ACTIVE L L H H X Bank/row X
  67. -- READ L H L H L/H Bank/col X
  68. -- WRITE L H L L L/H Bank/col Valid
  69. -- BURST TERMINATE L H H L X X Active
  70. -- PRECHARGE L L H L X Code X
  71. -- AUTO REFRESH L L L H X X X
  72. -- LOAD MODE REGISTER L L L L X Op-code X
  73. -- Write enable X X X X L X Active
  74. -- Write inhibit X X X X H X High-Z
  75. -- Here are the commands mapped to constants
  76. constant CMD_UNSELECTED : std_logic_vector(3 downto 0) := "1000";
  77. constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
  78. constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011";
  79. constant CMD_READ : std_logic_vector(3 downto 0) := "0101";
  80. constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
  81. constant CMD_TERMINATE : std_logic_vector(3 downto 0) := "0110";
  82. constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
  83. constant CMD_REFRESH : std_logic_vector(3 downto 0) := "0001";
  84. constant CMD_LOAD_MODE_REG : std_logic_vector(3 downto 0) := "0000";
  85. constant MODE_REG : std_logic_vector(12 downto 0) :=
  86. -- Reserved, wr bust, OpMode, CAS Latency (2), Burst Type, Burst Length (2)
  87. "000" & "0" & "00" & "010" & "0" & "001";
  88. signal iob_command : std_logic_vector( 3 downto 0) := CMD_NOP;
  89. signal iob_address : std_logic_vector(12 downto 0) := (others => '0');
  90. signal iob_data : std_logic_vector(15 downto 0) := (others => '0');
  91. signal iob_dqm : std_logic_vector( 1 downto 0) := (others => '0');
  92. signal iob_cke : std_logic := '0';
  93. signal iob_bank : std_logic_vector( 1 downto 0) := (others => '0');
  94. attribute IOB: string;
  95. attribute IOB of iob_command: signal is "true";
  96. attribute IOB of iob_address: signal is "true";
  97. attribute IOB of iob_dqm : signal is "true";
  98. attribute IOB of iob_cke : signal is "true";
  99. attribute IOB of iob_bank : signal is "true";
  100. attribute IOB of iob_data : signal is "true";
  101. signal iob_data_next : std_logic_vector(15 downto 0) := (others => '0');
  102. signal captured_data : std_logic_vector(15 downto 0) := (others => '0');
  103. signal captured_data_last : std_logic_vector(15 downto 0) := (others => '0');
  104. signal sdram_din : std_logic_vector(15 downto 0);
  105. attribute IOB of captured_data : signal is "true";
  106. type fsm_state is (s_startup,
  107. s_idle_in_6, s_idle_in_5, s_idle_in_4, s_idle_in_3, s_idle_in_2, s_idle_in_1,
  108. s_idle,
  109. s_open_in_2, s_open_in_1,
  110. s_write_1, s_write_2, s_write_3,
  111. s_read_1, s_read_2, s_read_3, s_read_4,
  112. s_precharge
  113. );
  114. signal state : fsm_state := s_startup;
  115. attribute FSM_ENCODING : string;
  116. attribute FSM_ENCODING of state : signal is "ONE-HOT";
  117. -- dual purpose counter, it counts up during the startup phase, then is used to trigger refreshes.
  118. constant startup_refresh_max : unsigned(13 downto 0) := (others => '1');
  119. signal startup_refresh_count : unsigned(13 downto 0) := startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
  120. -- logic to decide when to refresh
  121. signal pending_refresh : std_logic := '0';
  122. signal forcing_refresh : std_logic := '0';
  123. -- The incoming address is split into these three values
  124. signal addr_row : std_logic_vector(12 downto 0) := (others => '0');
  125. signal addr_col : std_logic_vector(12 downto 0) := (others => '0');
  126. signal addr_bank : std_logic_vector( 1 downto 0) := (others => '0');
  127. signal dqm_sr : std_logic_vector( 3 downto 0) := (others => '1'); -- an extra two bits in case CAS=3
  128. -- signals to hold the requested transaction before it is completed
  129. signal save_wr : std_logic := '0';
  130. signal save_row : std_logic_vector(12 downto 0);
  131. signal save_bank : std_logic_vector( 1 downto 0);
  132. signal save_col : std_logic_vector(12 downto 0);
  133. signal save_data_in : std_logic_vector(31 downto 0);
  134. signal save_byte_enable : std_logic_vector( 3 downto 0);
  135. -- control when new transactions are accepted
  136. signal ready_for_new : std_logic := '0';
  137. signal got_transaction : std_logic := '0';
  138. signal can_back_to_back : std_logic := '0';
  139. -- signal to control the Hi-Z state of the DQ bus
  140. signal iob_dq_hiz : std_logic := '1';
  141. -- signals for when to read the data off of the bus
  142. signal data_ready_delay : std_logic_vector( 4 downto 0);
  143. -- bit indexes used when splitting the address into row/colum/bank.
  144. constant start_of_col : natural := 0;
  145. constant end_of_col : natural := sdram_column_bits-2;
  146. constant start_of_bank : natural := sdram_column_bits-1;
  147. constant end_of_bank : natural := sdram_column_bits;
  148. constant start_of_row : natural := sdram_column_bits+1;
  149. constant end_of_row : natural := sdram_address_width-2;
  150. constant prefresh_cmd : natural := 10;
  151. begin
  152. -- Indicate the need to refresh when the counter is 2048,
  153. -- Force a refresh when the counter is 4096 - (if a refresh is forced,
  154. -- multiple refresshes will be forced until the counter is below 2048
  155. pending_refresh <= startup_refresh_count(11);
  156. forcing_refresh <= startup_refresh_count(12);
  157. -- tell the outside world when we can accept a new transaction;
  158. cmd_ready <= ready_for_new;
  159. ----------------------------------------------------------------------------
  160. -- Seperate the address into row / bank / address
  161. ----------------------------------------------------------------------------
  162. addr_row(end_of_row-start_of_row downto 0) <= cmd_address(end_of_row downto start_of_row); -- 12:0 <= 22:10
  163. addr_bank <= cmd_address(end_of_bank downto start_of_bank); -- 1:0 <= 9:8
  164. addr_col(sdram_column_bits-1 downto 0) <= cmd_address(end_of_col downto start_of_col) & '0'; -- 8:0 <= 7:0 & '0'
  165. --addr_row(12 downto 0) <= cmd_address(22 downto 10); -- 12:0 <= 22:10
  166. --addr_bank <= cmd_address( 9 downto 8); -- 1:0 <= 9:8
  167. --addr_col(8 downto 0) <= cmd_address( 7 downto 0) & '0'; -- 8:0 <= 7:0 & '0'
  168. -----------------------------------------------------------
  169. -- Forward the SDRAM clock to the SDRAM chip - 180 degress
  170. -- out of phase with the control signals (ensuring setup and holdup
  171. -----------------------------------------------------------
  172. sdram_clk_forward : ODDR2
  173. generic map(DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC")
  174. port map (Q => sdram_clk, C0 => clk, C1 => not clk, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1');
  175. -----------------------------------------------
  176. --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  177. --!! Ensure that all outputs are registered. !!
  178. --!! Check the pinout report to be sure !!
  179. --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  180. -----------------------------------------------
  181. sdram_cke <= iob_cke;
  182. sdram_CS <= iob_command(3);
  183. sdram_RAS <= iob_command(2);
  184. sdram_CAS <= iob_command(1);
  185. sdram_WE <= iob_command(0);
  186. sdram_dqm <= iob_dqm;
  187. sdram_ba <= iob_bank;
  188. sdram_addr <= iob_address;
  189. ---------------------------------------------------------------
  190. -- Explicitly set up the tristate I/O buffers on the DQ signals
  191. ---------------------------------------------------------------
  192. iob_dq_g: for i in 0 to 15 generate
  193. begin
  194. iob_dq_iob: IOBUF
  195. generic map (DRIVE => 12, IOSTANDARD => "LVTTL", SLEW => "FAST")
  196. port map ( O => sdram_din(i), IO => sdram_data(i), I => iob_data(i), T => iob_dq_hiz);
  197. end generate;
  198. capture_proc: process(clk)
  199. begin
  200. if rising_edge(clk) then
  201. captured_data <= sdram_din;
  202. end if;
  203. end process;
  204. main_proc: process(clk)
  205. begin
  206. if rising_edge(clk) then
  207. captured_data_last <= captured_data;
  208. ------------------------------------------------
  209. -- Default state is to do nothing
  210. ------------------------------------------------
  211. iob_command <= CMD_NOP;
  212. iob_address <= (others => '0');
  213. iob_bank <= (others => '0');
  214. ------------------------------------------------
  215. -- countdown for initialisation & refresh
  216. ------------------------------------------------
  217. startup_refresh_count <= startup_refresh_count+1;
  218. -------------------------------------------------------------------
  219. -- It we are ready for a new tranasction and one is being presented
  220. -- then accept it. Also remember what we are reading or writing,
  221. -- and if it can be back-to-backed with the last transaction
  222. -------------------------------------------------------------------
  223. if ready_for_new = '1' and cmd_enable = '1' then
  224. if save_bank = addr_bank and save_row = addr_row then
  225. can_back_to_back <= '1';
  226. else
  227. can_back_to_back <= '0';
  228. end if;
  229. save_row <= addr_row;
  230. save_bank <= addr_bank;
  231. save_col <= addr_col;
  232. save_wr <= cmd_wr;
  233. save_data_in <= cmd_data_in;
  234. save_byte_enable <= cmd_byte_enable;
  235. got_transaction <= '1';
  236. ready_for_new <= '0';
  237. end if;
  238. ------------------------------------------------
  239. -- Handle the data coming back from the
  240. -- SDRAM for the Read transaction
  241. ------------------------------------------------
  242. data_out_ready <= '0';
  243. if data_ready_delay(0) = '1' then
  244. data_out <= captured_data & captured_data_last;
  245. data_out_ready <= '1';
  246. end if;
  247. ----------------------------------------------------------------------------
  248. -- update shift registers used to choose when to present data to/from memory
  249. ----------------------------------------------------------------------------
  250. data_ready_delay <= '0' & data_ready_delay(data_ready_delay'high downto 1);
  251. iob_dqm <= dqm_sr(1 downto 0);
  252. dqm_sr <= "11" & dqm_sr(dqm_sr'high downto 2);
  253. case state is
  254. when s_startup =>
  255. ------------------------------------------------------------------------
  256. -- This is the initial startup state, where we wait for at least 100us
  257. -- before starting the start sequence
  258. --
  259. -- The initialisation is sequence is
  260. -- * de-assert SDRAM_CKE
  261. -- * 100us wait,
  262. -- * assert SDRAM_CKE
  263. -- * wait at least one cycle,
  264. -- * PRECHARGE
  265. -- * wait 2 cycles
  266. -- * REFRESH,
  267. -- * tREF wait
  268. -- * REFRESH,
  269. -- * tREF wait
  270. -- * LOAD_MODE_REG
  271. -- * 2 cycles wait
  272. ------------------------------------------------------------------------
  273. iob_CKE <= '1';
  274. -- All the commands during the startup are NOPS, except these
  275. if startup_refresh_count = startup_refresh_max-31 then
  276. -- ensure all rows are closed
  277. iob_command <= CMD_PRECHARGE;
  278. iob_address(prefresh_cmd) <= '1'; -- all banks
  279. iob_bank <= (others => '0');
  280. elsif startup_refresh_count = startup_refresh_max-23 then
  281. -- these refreshes need to be at least tREF (66ns) apart
  282. iob_command <= CMD_REFRESH;
  283. elsif startup_refresh_count = startup_refresh_max-15 then
  284. iob_command <= CMD_REFRESH;
  285. elsif startup_refresh_count = startup_refresh_max-7 then
  286. -- Now load the mode register
  287. iob_command <= CMD_LOAD_MODE_REG;
  288. iob_address <= MODE_REG;
  289. end if;
  290. ------------------------------------------------------
  291. -- if startup is coomplete then go into idle mode,
  292. -- get prepared to accept a new command, and schedule
  293. -- the first refresh cycle
  294. ------------------------------------------------------
  295. if startup_refresh_count = 0 then
  296. state <= s_idle;
  297. ready_for_new <= '1';
  298. got_transaction <= '0';
  299. startup_refresh_count <= to_unsigned(2048 - cycles_per_refresh+1,14);
  300. end if;
  301. when s_idle_in_6 => state <= s_idle_in_5;
  302. when s_idle_in_5 => state <= s_idle_in_4;
  303. when s_idle_in_4 => state <= s_idle_in_3;
  304. when s_idle_in_3 => state <= s_idle_in_2;
  305. when s_idle_in_2 => state <= s_idle_in_1;
  306. when s_idle_in_1 => state <= s_idle;
  307. when s_idle =>
  308. -- Priority is to issue a refresh if one is outstanding
  309. if pending_refresh = '1' or forcing_refresh = '1' then
  310. ------------------------------------------------------------------------
  311. -- Start the refresh cycle.
  312. -- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
  313. ------------------------------------------------------------------------
  314. state <= s_idle_in_6;
  315. iob_command <= CMD_REFRESH;
  316. startup_refresh_count <= startup_refresh_count - cycles_per_refresh+1;
  317. elsif got_transaction = '1' then
  318. --------------------------------
  319. -- Start the read or write cycle.
  320. -- First task is to open the row
  321. --------------------------------
  322. state <= s_open_in_2;
  323. iob_command <= CMD_ACTIVE;
  324. iob_address <= save_row;
  325. iob_bank <= save_bank;
  326. end if;
  327. --------------------------------------------
  328. -- Opening the row ready for reads or writes
  329. --------------------------------------------
  330. when s_open_in_2 => state <= s_open_in_1;
  331. when s_open_in_1 =>
  332. -- still waiting for row to open
  333. if save_wr = '1' then
  334. state <= s_write_1;
  335. iob_dq_hiz <= '0';
  336. iob_data <= save_data_in(15 downto 0); -- get the DQ bus out of HiZ early
  337. else
  338. iob_dq_hiz <= '1';
  339. state <= s_read_1;
  340. end if;
  341. -- we will be ready for a new transaction next cycle!
  342. ready_for_new <= '1';
  343. got_transaction <= '0';
  344. ----------------------------------
  345. -- Processing the read transaction
  346. ----------------------------------
  347. when s_read_1 =>
  348. state <= s_read_2;
  349. iob_command <= CMD_READ;
  350. iob_address <= save_col;
  351. iob_bank <= save_bank;
  352. iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
  353. -- Schedule reading the data values off the bus
  354. data_ready_delay(data_ready_delay'high) <= '1';
  355. -- Set the data masks to read all bytes
  356. iob_dqm <= (others => '0');
  357. dqm_sr(1 downto 0) <= (others => '0');
  358. when s_read_2 =>
  359. state <= s_read_3;
  360. if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
  361. if save_wr = '0' then
  362. state <= s_read_1;
  363. ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
  364. end if;
  365. end if;
  366. when s_read_3 =>
  367. state <= s_read_4;
  368. if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
  369. if save_wr = '0' then
  370. state <= s_read_1;
  371. ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
  372. end if;
  373. end if;
  374. when s_read_4 =>
  375. state <= s_precharge;
  376. -- can we do back-to-back read?
  377. if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
  378. if save_wr = '0' then
  379. state <= s_read_1;
  380. ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
  381. else
  382. state <= s_open_in_2; -- we have to wait for the read data to come back before we swutch the bus into HiZ
  383. end if;
  384. end if;
  385. ------------------------------------------------------------------
  386. -- Processing the write transaction
  387. -------------------------------------------------------------------
  388. when s_write_1 =>
  389. state <= s_write_2;
  390. iob_command <= CMD_WRITE;
  391. iob_address <= save_col;
  392. iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
  393. iob_bank <= save_bank;
  394. iob_dqm <= NOT save_byte_enable(1 downto 0);
  395. dqm_sr(1 downto 0) <= NOT save_byte_enable(3 downto 2);
  396. iob_data <= save_data_in(15 downto 0);
  397. iob_data_next <= save_data_in(31 downto 16);
  398. when s_write_2 =>
  399. state <= s_write_3;
  400. iob_data <= iob_data_next;
  401. -- can we do a back-to-back write?
  402. if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
  403. if save_wr = '1' then
  404. -- back-to-back write?
  405. state <= s_write_1;
  406. ready_for_new <= '1';
  407. got_transaction <= '0';
  408. end if;
  409. -- Although it looks right in simulation you can't go write-to-read
  410. -- here due to bus contention, as iob_dq_hiz takes a few ns.
  411. end if;
  412. when s_write_3 => -- must wait tRDL, hence the extra idle state
  413. -- back to back transaction?
  414. if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
  415. if save_wr = '1' then
  416. -- back-to-back write?
  417. state <= s_write_1;
  418. ready_for_new <= '1';
  419. got_transaction <= '0';
  420. else
  421. -- write-to-read switch?
  422. state <= s_read_1;
  423. iob_dq_hiz <= '1';
  424. ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
  425. got_transaction <= '0';
  426. end if;
  427. else
  428. iob_dq_hiz <= '1';
  429. state <= s_precharge;
  430. end if;
  431. -------------------------------------------------------------------
  432. -- Closing the row off (this closes all banks)
  433. -------------------------------------------------------------------
  434. when s_precharge =>
  435. state <= s_idle_in_3;
  436. iob_command <= CMD_PRECHARGE;
  437. iob_address(prefresh_cmd) <= '1'; -- A10 actually matters - it selects all banks or just one
  438. -------------------------------------------------------------------
  439. -- We should never get here, but if we do then reset the memory
  440. -------------------------------------------------------------------
  441. when others =>
  442. state <= s_startup;
  443. ready_for_new <= '0';
  444. startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
  445. end case;
  446. if reset = '1' then -- Sync reset
  447. state <= s_startup;
  448. ready_for_new <= '0';
  449. startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
  450. end if;
  451. end if;
  452. end process;
  453. end Behavioral;