top_level_de2_70.vhd 18 KB

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  1. --+-----------------------------------+-------------------------------------+--
  2. --| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
  3. --| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
  4. --| / __|/ _ \ / __|_ / _ \| | | | | |--
  5. --| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
  6. --| |___/\___/ \___/___\___/ \___/ | |--
  7. --| | http://sowerbutts.com/ |--
  8. --+-----------------------------------+-------------------------------------+--
  9. --| Top level module: connects modules to each other and the outside world |--
  10. --+-------------------------------------------------------------------------+--
  11. --
  12. -- See README.txt for more details
  13. --
  14. library IEEE;
  15. use IEEE.STD_LOGIC_1164.ALL;
  16. use IEEE.NUMERIC_STD.ALL;
  17. entity top_level is
  18. Port ( sysclk_32m : in std_logic;
  19. sys_clk_pad_i : in std_logic;
  20. rst_n_pad_i : in std_logic;
  21. leds : out std_logic_vector(4 downto 0);
  22. reset_button : in std_logic;
  23. console_select : in std_logic;
  24. -- UART0 (to FTDI USB chip, no flow control)
  25. serial_rx : in std_logic;
  26. serial_tx : out std_logic;
  27. -- UART0 (to MAX3232 level shifter chip, hardware flow control)
  28. uart1_rx : in std_logic;
  29. uart1_cts : in std_logic;
  30. uart1_tx : out std_logic;
  31. uart1_rts : out std_logic;
  32. -- SPI flash chip
  33. flash_spi_cs : out std_logic;
  34. flash_spi_clk : out std_logic;
  35. flash_spi_mosi : out std_logic;
  36. flash_spi_miso : in std_logic;
  37. -- SD card socket
  38. sdcard_spi_cs : out std_logic;
  39. sdcard_spi_clk : out std_logic;
  40. sdcard_spi_mosi : out std_logic;
  41. sdcard_spi_miso : in std_logic;
  42. -- SDRAM chip
  43. SDRAM_CLK : out std_logic;
  44. SDRAM_CKE : out std_logic;
  45. SDRAM_CS : out std_logic;
  46. SDRAM_nRAS : out std_logic;
  47. SDRAM_nCAS : out std_logic;
  48. SDRAM_nWE : out std_logic;
  49. SDRAM_DQM : out std_logic_vector( 1 downto 0);
  50. SDRAM_ADDR : out std_logic_vector (12 downto 0);
  51. SDRAM_BA : out std_logic_vector( 1 downto 0);
  52. SDRAM_DQ : inout std_logic_vector (15 downto 0)
  53. );
  54. end top_level;
  55. architecture Behavioral of top_level is
  56. constant clk_freq_mhz : natural := 50; -- this is the frequency which the PLL outputs, in MHz.
  57. -- SDRAM configuration
  58. constant sdram_address_width : natural := 24;
  59. constant sdram_column_bits : natural := 9;
  60. constant cycles_per_refresh : natural := (64000*clk_freq_mhz)/8192-1;
  61. -- For simulation, we don't need a long init stage. but for real DRAM we need approx 101us.
  62. -- The constant below has a different value when interpreted by the synthesis and simulator
  63. -- tools in order to achieve the desired timing in each.
  64. constant sdram_startup_cycles: natural := 101 * clk_freq_mhz
  65. -- pragma translate_off
  66. - 10000 -- reduce the value the simulator uses
  67. -- pragma translate_on
  68. ;
  69. -- signals for clocking
  70. signal clk_feedback : std_logic; -- PLL clock feedback
  71. signal clk_unbuffered : std_logic; -- unbuffered system clock
  72. signal clk : std_logic; -- buffered system clock (all logic should be clocked by this)
  73. -- console latch
  74. signal console_select_clk1 : std_logic;
  75. signal console_select_sync : std_logic;
  76. signal swap_uart01 : std_logic := '0';
  77. -- system reset signals
  78. signal power_on_reset : std_logic_vector(1 downto 0) := (others => '1');
  79. signal system_reset : std_logic;
  80. signal reset_button_clk1 : std_logic;
  81. signal reset_button_sync : std_logic; -- reset button signal, synchronised to our clock
  82. signal reset_request_uart : std_logic; -- reset request signal from FTDI UART (when you send "!~!~!~" to the UART, this line is asserted)
  83. -- CPU control
  84. signal coldboot : std_logic;
  85. signal cpu_clk_enable : std_logic;
  86. signal cpu_m1_cycle : std_logic;
  87. signal cpu_req_mem : std_logic;
  88. signal cpu_req_io : std_logic;
  89. signal req_mem : std_logic;
  90. signal req_io : std_logic;
  91. signal req_read : std_logic;
  92. signal req_write : std_logic;
  93. signal virtual_address : std_logic_vector(15 downto 0);
  94. signal physical_address : std_logic_vector(25 downto 0);
  95. signal mem_wait : std_logic;
  96. signal cpu_wait : std_logic;
  97. signal dram_wait : std_logic;
  98. signal mmu_wait : std_logic;
  99. signal spimaster0_wait : std_logic;
  100. signal spimaster1_wait : std_logic;
  101. -- chip selects
  102. signal mmu_cs : std_logic;
  103. signal rom_cs : std_logic;
  104. signal sram_cs : std_logic;
  105. signal dram_cs : std_logic;
  106. signal uartA_cs : std_logic;
  107. signal uartB_cs : std_logic;
  108. signal uart0_cs : std_logic;
  109. signal uart1_cs : std_logic;
  110. signal timer_cs : std_logic;
  111. signal spimaster0_cs : std_logic;
  112. signal spimaster1_cs : std_logic;
  113. signal clkscale_cs : std_logic;
  114. signal gpio_cs : std_logic;
  115. -- data bus
  116. signal cpu_data_in : std_logic_vector(7 downto 0);
  117. signal cpu_data_out : std_logic_vector(7 downto 0);
  118. signal rom_data_out : std_logic_vector(7 downto 0);
  119. signal sram_data_out : std_logic_vector(7 downto 0);
  120. signal dram_data_out : std_logic_vector(7 downto 0);
  121. signal uart0_data_out : std_logic_vector(7 downto 0);
  122. signal uart1_data_out : std_logic_vector(7 downto 0);
  123. signal timer_data_out : std_logic_vector(7 downto 0);
  124. signal spimaster0_data_out : std_logic_vector(7 downto 0);
  125. signal spimaster1_data_out : std_logic_vector(7 downto 0);
  126. signal mmu_data_out : std_logic_vector(7 downto 0);
  127. signal clkscale_out : std_logic_vector(7 downto 0);
  128. signal gpio_data_out : std_logic_vector(7 downto 0);
  129. -- GPIO
  130. signal gpio_input : std_logic_vector(7 downto 0);
  131. signal gpio_output : std_logic_vector(7 downto 0);
  132. -- Interrupts
  133. signal cpu_interrupt_in : std_logic;
  134. signal timer_interrupt : std_logic;
  135. signal uart0_interrupt : std_logic;
  136. signal uart1_interrupt : std_logic;
  137. begin
  138. -- Hold CPU reset high for 8 clock cycles on startup,
  139. -- and when the user presses their reset button.
  140. process(clk)
  141. begin
  142. if rising_edge(clk) then
  143. -- Xilinx advises using two flip-flops are used to bring external
  144. -- signals which feed control logic into our clock domain.
  145. reset_button_clk1 <= reset_button;
  146. reset_button_sync <= reset_button_clk1;
  147. console_select_clk1 <= console_select;
  148. console_select_sync <= console_select_clk1;
  149. -- reset the system when requested
  150. if (power_on_reset(0) = '1') then
  151. system_reset <= '1';
  152. else
  153. system_reset <= '0';
  154. end if;
  155. -- shift 0s into the power_on_reset shift register from the MSB
  156. power_on_reset <= '0' & power_on_reset(power_on_reset'length-1 downto 1);
  157. -- During reset, latch the console select jumper. This is used to
  158. -- optionally swap over the UART roles and move the system console to
  159. -- the second serial port on the IO board.
  160. if system_reset = '1' then
  161. swap_uart01 <= console_select_sync;
  162. else
  163. swap_uart01 <= swap_uart01;
  164. end if;
  165. end if;
  166. end process;
  167. -- GPIO input signal routing
  168. gpio_input <= coldboot & swap_uart01 & "000000";
  169. -- GPIO output signal routing
  170. leds(0) <= gpio_output(0);
  171. leds(1) <= gpio_output(1);
  172. leds(2) <= gpio_output(2);
  173. leds(3) <= gpio_output(3);
  174. -- User LED (LED1) on Papilio Pro indicates when the CPU is being asked to wait (eg by the SDRAM cache)
  175. leds(4) <= cpu_wait;
  176. -- Interrupt signal for the CPU
  177. cpu_interrupt_in <= (timer_interrupt or uart0_interrupt or uart1_interrupt);
  178. -- Z80 CPU core
  179. cpu: entity work.Z80cpu
  180. port map (
  181. reset => system_reset,
  182. clk => clk,
  183. clk_enable => cpu_clk_enable,
  184. m1_cycle => cpu_m1_cycle,
  185. interrupt => cpu_interrupt_in,
  186. nmi => '0',
  187. req_mem => cpu_req_mem,
  188. req_io => cpu_req_io,
  189. req_read => req_read,
  190. req_write => req_write,
  191. mem_wait => cpu_wait,
  192. address => virtual_address,
  193. data_in => cpu_data_in,
  194. data_out => cpu_data_out
  195. );
  196. -- Memory management unit
  197. mmu: entity work.MMU
  198. port map (
  199. reset => system_reset,
  200. clk => clk,
  201. address_in => virtual_address,
  202. address_out => physical_address,
  203. cpu_data_in => cpu_data_out,
  204. cpu_data_out => mmu_data_out,
  205. req_mem_in => cpu_req_mem,
  206. req_io_in => cpu_req_io,
  207. req_mem_out => req_mem,
  208. req_io_out => req_io,
  209. req_read => req_read,
  210. req_write => req_write,
  211. io_cs => mmu_cs,
  212. cpu_wait => mmu_wait,
  213. access_violated => open -- for now!!
  214. );
  215. -- This process determines which IO or memory device the CPU is addressing
  216. -- and asserts the appropriate chip select signals.
  217. cs_process: process(req_mem, req_io, physical_address, virtual_address, uartA_cs, uartB_cs, swap_uart01)
  218. begin
  219. -- memory chip selects: default to unselected
  220. rom_cs <= '0';
  221. sram_cs <= '0';
  222. dram_cs <= '0';
  223. -- io chip selects: default to unselected
  224. uartA_cs <= '0';
  225. uartB_cs <= '0';
  226. mmu_cs <= '0';
  227. timer_cs <= '0';
  228. spimaster0_cs <= '0';
  229. spimaster1_cs <= '0';
  230. clkscale_cs <= '0';
  231. gpio_cs <= '0';
  232. -- memory address decoding
  233. -- address space is organised as:
  234. -- 0x0 000 000 - 0x0 FFF FFF 16MB DRAM (cached) (mapped to 8MB DRAM twice)
  235. -- 0x1 000 000 - 0x1 FFF FFF 16MB DRAM (uncached) (mapped to 8MB DRAM twice)
  236. -- 0x2 000 000 - 0x2 000 FFF 4KB monitor ROM (FPGA block RAM)
  237. -- 0x2 001 000 - 0x2 001 FFF 4KB SRAM (FPGA block RAM)
  238. -- 0x2 002 000 - 0x3 FFF FFF unused space for future expansion
  239. if physical_address(25) = '0' then
  240. -- bottom 32MB: DRAM handles this
  241. dram_cs <= req_mem;
  242. else
  243. -- top 32MB: other memory devices
  244. case physical_address(24 downto 12) is
  245. when "0000000000000" => rom_cs <= req_mem;
  246. when "0000000000001" => sram_cs <= req_mem;
  247. when others => -- undecoded memory space
  248. end case;
  249. end if;
  250. -- IO address decoding
  251. case virtual_address(7 downto 3) is
  252. when "00000" => uartA_cs <= req_io; -- 00 ... 07
  253. when "00010" => timer_cs <= req_io; -- 10 ... 17
  254. when "00011" => spimaster0_cs <= req_io; -- 18 ... 1F
  255. when "00100" => gpio_cs <= req_io; -- 20 ... 27
  256. when "00101" => uartB_cs <= req_io; -- 28 ... 2F
  257. when "00110" => spimaster1_cs <= req_io; -- 30 ... 37
  258. -- unused ports
  259. when "11110" => clkscale_cs <= req_io; -- F0 ... F7
  260. when "11111" => mmu_cs <= req_io; -- F8 ... FF
  261. when others =>
  262. end case;
  263. -- send the UART chip select to the appropriate UART depending
  264. -- on whether they have been swapped over or not.
  265. if swap_uart01 = '0' then
  266. uart0_cs <= uartB_cs;
  267. uart1_cs <= uartA_cs;
  268. else
  269. uart0_cs <= uartA_cs;
  270. uart1_cs <= uartB_cs;
  271. end if;
  272. end process;
  273. -- the selected memory device can request the CPU to wait
  274. mem_wait <=
  275. dram_wait when dram_cs='1' else
  276. spimaster0_wait when spimaster0_cs='1' else
  277. spimaster1_wait when spimaster1_cs='1' else
  278. '0';
  279. -- the MMU can, at any time, request the CPU wait (this is used when
  280. -- translating IO to memory requests, to implement a wait state for
  281. -- the "17th page")
  282. cpu_wait <= (mem_wait or mmu_wait);
  283. -- input mux for CPU data bus
  284. cpu_data_in <=
  285. rom_data_out when rom_cs='1' else
  286. dram_data_out when dram_cs='1' else
  287. sram_data_out when sram_cs='1' else
  288. uart0_data_out when uart0_cs='1' else
  289. uart1_data_out when uart1_cs='1' else
  290. timer_data_out when timer_cs='1' else
  291. mmu_data_out when mmu_cs='1' else
  292. spimaster0_data_out when spimaster0_cs='1' else
  293. spimaster1_data_out when spimaster1_cs='1' else
  294. clkscale_out when clkscale_cs='1' else
  295. gpio_data_out when gpio_cs='1' else
  296. rom_data_out; -- default case
  297. dram: entity work.DRAM
  298. generic map(
  299. sdram_address_width => sdram_address_width,
  300. sdram_column_bits => sdram_column_bits,
  301. sdram_startup_cycles=> sdram_startup_cycles,
  302. cycles_per_refresh => cycles_per_refresh
  303. )
  304. port map(
  305. clk => clk,
  306. reset => '0', -- important to note that we DO NOT reset the SDRAM controller on reset (it would stop refreshing, which would be bad)
  307. -- interface to synthetic CPU
  308. cs => dram_cs,
  309. req_read => req_read,
  310. req_write => req_write,
  311. mem_address => physical_address(24 downto 0),
  312. mem_wait => dram_wait,
  313. data_in => cpu_data_out,
  314. data_out => dram_data_out,
  315. coldboot => coldboot,
  316. -- interface to hardware SDRAM chip
  317. SDRAM_CLK => open,
  318. SDRAM_CKE => SDRAM_CKE,
  319. SDRAM_CS => SDRAM_CS,
  320. SDRAM_nRAS => SDRAM_nRAS,
  321. SDRAM_nCAS => SDRAM_nCAS,
  322. SDRAM_nWE => SDRAM_nWE,
  323. SDRAM_DQM => SDRAM_DQM,
  324. SDRAM_BA => SDRAM_BA,
  325. SDRAM_ADDR => SDRAM_ADDR,
  326. SDRAM_DQ => SDRAM_DQ
  327. );
  328. -- 4KB system ROM implemented in block RAM
  329. rom: entity work.MonZ80
  330. port map(
  331. clk => clk,
  332. A => physical_address(11 downto 0),
  333. D => rom_data_out
  334. );
  335. -- 4KB SRAM memory implemented in block RAM
  336. sram: entity work.SSRAM
  337. generic map(
  338. AddrWidth => 12
  339. )
  340. port map(
  341. clk => clk,
  342. ce => sram_cs,
  343. we => req_write,
  344. A => physical_address(11 downto 0),
  345. DIn => cpu_data_out,
  346. DOut => sram_data_out
  347. );
  348. -- UART connected to FTDI USB UART
  349. uart0: entity work.uart_interface
  350. generic map ( watch_for_reset => 1, clk_frequency => (clk_freq_mhz * 1000000) )
  351. port map(
  352. clk => clk,
  353. reset => system_reset,
  354. reset_out => reset_request_uart, -- result of watching for reset sequence on the input
  355. serial_in => serial_rx,
  356. serial_out => serial_tx,
  357. serial_rts => open,
  358. serial_cts => '0',
  359. cpu_address => virtual_address(2 downto 0),
  360. cpu_data_in => cpu_data_out,
  361. cpu_data_out => uart0_data_out,
  362. enable => uart0_cs,
  363. interrupt => uart0_interrupt,
  364. req_read => req_read,
  365. req_write => req_write
  366. );
  367. -- Timer device (internally scales the clock to 1MHz)
  368. timer: entity work.timer
  369. generic map ( clk_frequency => (clk_freq_mhz * 1000000) )
  370. port map(
  371. clk => clk,
  372. reset => system_reset,
  373. cpu_address => virtual_address(2 downto 0),
  374. data_in => cpu_data_out,
  375. data_out => timer_data_out,
  376. enable => timer_cs,
  377. req_read => req_read,
  378. req_write => req_write,
  379. interrupt => timer_interrupt
  380. );
  381. -- GPIO to FPGA pins and/or internal signals
  382. gpio: entity work.gpio
  383. port map(
  384. clk => clk,
  385. reset => system_reset,
  386. cpu_address => virtual_address(2 downto 0),
  387. data_in => cpu_data_out,
  388. data_out => gpio_data_out,
  389. enable => gpio_cs,
  390. read_notwrite => req_read,
  391. input_pins => gpio_input,
  392. output_pins => gpio_output
  393. );
  394. -- An attempt to allow the CPU clock to be scaled back to run
  395. -- at slower speeds without affecting the clock signal sent to
  396. -- IO devices. Basically this was an attempt to make CP/M games
  397. -- playable :) Very limited success. Might be simpler to remove
  398. -- this entirely.
  399. clkscale: entity work.clkscale
  400. port map (
  401. clk => clk,
  402. reset => system_reset,
  403. cpu_address => virtual_address(2 downto 0),
  404. data_in => cpu_data_out,
  405. data_out => clkscale_out,
  406. enable => clkscale_cs,
  407. read_notwrite => req_read,
  408. clk_enable => cpu_clk_enable
  409. );
  410. pll: entity work.pll
  411. port map (
  412. areset => open,
  413. inclk0 => sys_clk_pad_i,
  414. c0 => sdram_clk, -- 100 Mhz - 180 deg
  415. c1 => clk, -- 100 Mhz
  416. locked => open
  417. );
  418. end Behavioral;