SDRAM_Controller.vhd 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473
  1. ----------------------------------------------------------------------------------
  2. -- Engineer: Mike Field <hamster@snap.net.nz>
  3. --
  4. -- Create Date: 14:09:12 09/15/2013
  5. -- Module Name: SDRAM_Controller - Behavioral
  6. -- Description: Simple SDRAM controller for a Micron 48LC16M16A2-7E
  7. -- or Micron 48LC4M16A2-7E @ 100MHz
  8. -- Revision:
  9. -- Revision 0.1 - Initial version
  10. -- Revision 0.2 - Removed second clock signal that isn't needed.
  11. -- Revision 0.3 - Added back-to-back reads and writes.
  12. -- Revision 0.4 - Allow refeshes to be delayed till next PRECHARGE is issued,
  13. -- Unless they get really, really delayed. If a delay occurs multiple
  14. -- refreshes might get pushed out, but it will have avioded about
  15. -- 50% of the refresh overhead
  16. -- Revision 0.5 - Add more paramaters to the design, allowing it to work for both the
  17. -- Papilio Pro and Logi-Pi
  18. --
  19. -- Worst case performance (single accesses to different rows or banks) is:
  20. -- Writes 16 cycles = 6,250,000 writes/sec = 25.0MB/s (excluding refresh overhead)
  21. -- Reads 17 cycles = 5,882,352 reads/sec = 23.5MB/s (excluding refresh overhead)
  22. --
  23. -- For 1:1 mixed reads and writes into the same row it is around 88MB/s
  24. -- For reads or wries to the same it is can be as high as 184MB/s
  25. ----------------------------------------------------------------------------------
  26. library IEEE;
  27. use IEEE.STD_LOGIC_1164.ALL;
  28. library UNISIM;
  29. use IEEE.NUMERIC_STD.ALL;
  30. library altera_mf;
  31. use altera_mf.altera_mf_components.all;
  32. entity SDRAM_Controller is
  33. generic (
  34. sdram_address_width : natural;
  35. sdram_column_bits : natural;
  36. sdram_startup_cycles: natural;
  37. cycles_per_refresh : natural
  38. );
  39. Port ( clk : in STD_LOGIC;
  40. reset : in STD_LOGIC;
  41. -- Interface to issue reads or write data
  42. cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
  43. cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
  44. cmd_wr : in STD_LOGIC; -- Is this a write?
  45. cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
  46. cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
  47. cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
  48. data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
  49. data_out_ready : out STD_LOGIC; -- is new data ready?
  50. -- SDRAM signals
  51. SDRAM_CLK : out STD_LOGIC;
  52. SDRAM_CKE : out STD_LOGIC;
  53. SDRAM_CS : out STD_LOGIC;
  54. SDRAM_RAS : out STD_LOGIC;
  55. SDRAM_CAS : out STD_LOGIC;
  56. SDRAM_WE : out STD_LOGIC;
  57. SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
  58. SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
  59. SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
  60. SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0));
  61. end SDRAM_Controller;
  62. architecture Behavioral of SDRAM_Controller is
  63. -- From page 37 of MT48LC16M16A2 datasheet
  64. -- Name (Function) CS# RAS# CAS# WE# DQM Addr Data
  65. -- COMMAND INHIBIT (NOP) H X X X X X X
  66. -- NO OPERATION (NOP) L H H H X X X
  67. -- ACTIVE L L H H X Bank/row X
  68. -- READ L H L H L/H Bank/col X
  69. -- WRITE L H L L L/H Bank/col Valid
  70. -- BURST TERMINATE L H H L X X Active
  71. -- PRECHARGE L L H L X Code X
  72. -- AUTO REFRESH L L L H X X X
  73. -- LOAD MODE REGISTER L L L L X Op-code X
  74. -- Write enable X X X X L X Active
  75. -- Write inhibit X X X X H X High-Z
  76. -- Here are the commands mapped to constants
  77. constant CMD_UNSELECTED : std_logic_vector(3 downto 0) := "1000";
  78. constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
  79. constant CMD_ACTIVE : std_logic_vector(3 downto 0) := "0011";
  80. constant CMD_READ : std_logic_vector(3 downto 0) := "0101";
  81. constant CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
  82. constant CMD_TERMINATE : std_logic_vector(3 downto 0) := "0110";
  83. constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
  84. constant CMD_REFRESH : std_logic_vector(3 downto 0) := "0001";
  85. constant CMD_LOAD_MODE_REG : std_logic_vector(3 downto 0) := "0000";
  86. constant MODE_REG : std_logic_vector(12 downto 0) :=
  87. -- Reserved, wr bust, OpMode, CAS Latency (2), Burst Type, Burst Length (2)
  88. "000" & "0" & "00" & "010" & "0" & "001";
  89. signal iob_command : std_logic_vector( 3 downto 0) := CMD_NOP;
  90. signal iob_address : std_logic_vector(12 downto 0) := (others => '0');
  91. signal iob_data : std_logic_vector(15 downto 0) := (others => '0');
  92. signal iob_dqm : std_logic_vector( 1 downto 0) := (others => '0');
  93. signal iob_cke : std_logic := '0';
  94. signal iob_bank : std_logic_vector( 1 downto 0) := (others => '0');
  95. attribute IOB: string;
  96. attribute IOB of iob_command: signal is "true";
  97. attribute IOB of iob_address: signal is "true";
  98. attribute IOB of iob_dqm : signal is "true";
  99. attribute IOB of iob_cke : signal is "true";
  100. attribute IOB of iob_bank : signal is "true";
  101. attribute IOB of iob_data : signal is "true";
  102. signal iob_data_next : std_logic_vector(15 downto 0) := (others => '0');
  103. signal captured_data : std_logic_vector(15 downto 0) := (others => '0');
  104. signal captured_data_last : std_logic_vector(15 downto 0) := (others => '0');
  105. signal sdram_din : std_logic_vector(15 downto 0);
  106. attribute IOB of captured_data : signal is "true";
  107. type fsm_state is (s_startup,
  108. s_idle_in_6, s_idle_in_5, s_idle_in_4, s_idle_in_3, s_idle_in_2, s_idle_in_1,
  109. s_idle,
  110. s_open_in_2, s_open_in_1,
  111. s_write_1, s_write_2, s_write_3,
  112. s_read_1, s_read_2, s_read_3, s_read_4,
  113. s_precharge
  114. );
  115. signal state : fsm_state := s_startup;
  116. attribute FSM_ENCODING : string;
  117. attribute FSM_ENCODING of state : signal is "ONE-HOT";
  118. -- dual purpose counter, it counts up during the startup phase, then is used to trigger refreshes.
  119. constant startup_refresh_max : unsigned(13 downto 0) := (others => '1');
  120. signal startup_refresh_count : unsigned(13 downto 0) := startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
  121. -- logic to decide when to refresh
  122. signal pending_refresh : std_logic := '0';
  123. signal forcing_refresh : std_logic := '0';
  124. -- The incoming address is split into these three values
  125. signal addr_row : std_logic_vector(12 downto 0) := (others => '0');
  126. signal addr_col : std_logic_vector(12 downto 0) := (others => '0');
  127. signal addr_bank : std_logic_vector( 1 downto 0) := (others => '0');
  128. signal dqm_sr : std_logic_vector( 3 downto 0) := (others => '1'); -- an extra two bits in case CAS=3
  129. -- signals to hold the requested transaction before it is completed
  130. signal save_wr : std_logic := '0';
  131. signal save_row : std_logic_vector(12 downto 0);
  132. signal save_bank : std_logic_vector( 1 downto 0);
  133. signal save_col : std_logic_vector(12 downto 0);
  134. signal save_data_in : std_logic_vector(31 downto 0);
  135. signal save_byte_enable : std_logic_vector( 3 downto 0);
  136. -- control when new transactions are accepted
  137. signal ready_for_new : std_logic := '0';
  138. signal got_transaction : std_logic := '0';
  139. signal can_back_to_back : std_logic := '0';
  140. -- signal to control the Hi-Z state of the DQ bus
  141. signal iob_dq_hiz : std_logic := '1';
  142. -- signals for when to read the data off of the bus
  143. signal data_ready_delay : std_logic_vector( 4 downto 0);
  144. -- bit indexes used when splitting the address into row/colum/bank.
  145. constant start_of_col : natural := 0;
  146. constant end_of_col : natural := sdram_column_bits-2;
  147. constant start_of_bank : natural := sdram_column_bits-1;
  148. constant end_of_bank : natural := sdram_column_bits;
  149. constant start_of_row : natural := sdram_column_bits+1;
  150. constant end_of_row : natural := sdram_address_width-2;
  151. constant prefresh_cmd : natural := 10;
  152. begin
  153. -- Indicate the need to refresh when the counter is 2048,
  154. -- Force a refresh when the counter is 4096 - (if a refresh is forced,
  155. -- multiple refresshes will be forced until the counter is below 2048
  156. pending_refresh <= startup_refresh_count(11);
  157. forcing_refresh <= startup_refresh_count(12);
  158. -- tell the outside world when we can accept a new transaction;
  159. cmd_ready <= ready_for_new;
  160. ----------------------------------------------------------------------------
  161. -- Seperate the address into row / bank / address
  162. ----------------------------------------------------------------------------
  163. addr_row(end_of_row-start_of_row downto 0) <= cmd_address(end_of_row downto start_of_row); -- 12:0 <= 22:10
  164. addr_bank <= cmd_address(end_of_bank downto start_of_bank); -- 1:0 <= 9:8
  165. addr_col(sdram_column_bits-1 downto 0) <= cmd_address(end_of_col downto start_of_col) & '0'; -- 8:0 <= 7:0 & '0'
  166. --addr_row(12 downto 0) <= cmd_address(22 downto 10); -- 12:0 <= 22:10
  167. --addr_bank <= cmd_address( 9 downto 8); -- 1:0 <= 9:8
  168. --addr_col(8 downto 0) <= cmd_address( 7 downto 0) & '0'; -- 8:0 <= 7:0 & '0'
  169. -----------------------------------------------
  170. --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  171. --!! Ensure that all outputs are registered. !!
  172. --!! Check the pinout report to be sure !!
  173. --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  174. -----------------------------------------------
  175. sdram_cke <= iob_cke;
  176. sdram_CS <= iob_command(3);
  177. sdram_RAS <= iob_command(2);
  178. sdram_CAS <= iob_command(1);
  179. sdram_WE <= iob_command(0);
  180. sdram_dqm <= iob_dqm;
  181. sdram_ba <= iob_bank;
  182. sdram_addr <= iob_address;
  183. sdram_din <= sdram_data;
  184. sdram_data <= iob_data when iob_dq_hiz = '0' else (others => 'Z');
  185. ---------------------------------------------------------------
  186. -- Explicitly set up the tristate I/O buffers on the DQ signals
  187. ---------------------------------------------------------------
  188. --iob_dq_g: for i in 0 to 15 generate
  189. -- begin
  190. --iob_dq_iob: altiobuf_bidir
  191. -- generic map (number_of_channels => 1)
  192. -- port map ( dataout(0) => sdram_din(i), dataio(0) => sdram_data(i), datain(0) => iob_data(i), oe(0) => iob_dq_hiz);
  193. --end generate;
  194. capture_proc: process(clk)
  195. begin
  196. if rising_edge(clk) then
  197. captured_data <= sdram_din;
  198. end if;
  199. end process;
  200. main_proc: process(clk)
  201. begin
  202. if rising_edge(clk) then
  203. captured_data_last <= captured_data;
  204. ------------------------------------------------
  205. -- Default state is to do nothing
  206. ------------------------------------------------
  207. iob_command <= CMD_NOP;
  208. iob_address <= (others => '0');
  209. iob_bank <= (others => '0');
  210. ------------------------------------------------
  211. -- countdown for initialisation & refresh
  212. ------------------------------------------------
  213. startup_refresh_count <= startup_refresh_count+1;
  214. -------------------------------------------------------------------
  215. -- It we are ready for a new tranasction and one is being presented
  216. -- then accept it. Also remember what we are reading or writing,
  217. -- and if it can be back-to-backed with the last transaction
  218. -------------------------------------------------------------------
  219. if ready_for_new = '1' and cmd_enable = '1' then
  220. if save_bank = addr_bank and save_row = addr_row then
  221. can_back_to_back <= '1';
  222. else
  223. can_back_to_back <= '0';
  224. end if;
  225. save_row <= addr_row;
  226. save_bank <= addr_bank;
  227. save_col <= addr_col;
  228. save_wr <= cmd_wr;
  229. save_data_in <= cmd_data_in;
  230. save_byte_enable <= cmd_byte_enable;
  231. got_transaction <= '1';
  232. ready_for_new <= '0';
  233. end if;
  234. ------------------------------------------------
  235. -- Handle the data coming back from the
  236. -- SDRAM for the Read transaction
  237. ------------------------------------------------
  238. data_out_ready <= '0';
  239. if data_ready_delay(0) = '1' then
  240. data_out <= captured_data & captured_data_last;
  241. data_out_ready <= '1';
  242. end if;
  243. ----------------------------------------------------------------------------
  244. -- update shift registers used to choose when to present data to/from memory
  245. ----------------------------------------------------------------------------
  246. data_ready_delay <= '0' & data_ready_delay(data_ready_delay'high downto 1);
  247. iob_dqm <= dqm_sr(1 downto 0);
  248. dqm_sr <= "11" & dqm_sr(dqm_sr'high downto 2);
  249. case state is
  250. when s_startup =>
  251. ------------------------------------------------------------------------
  252. -- This is the initial startup state, where we wait for at least 100us
  253. -- before starting the start sequence
  254. --
  255. -- The initialisation is sequence is
  256. -- * de-assert SDRAM_CKE
  257. -- * 100us wait,
  258. -- * assert SDRAM_CKE
  259. -- * wait at least one cycle,
  260. -- * PRECHARGE
  261. -- * wait 2 cycles
  262. -- * REFRESH,
  263. -- * tREF wait
  264. -- * REFRESH,
  265. -- * tREF wait
  266. -- * LOAD_MODE_REG
  267. -- * 2 cycles wait
  268. ------------------------------------------------------------------------
  269. iob_CKE <= '1';
  270. -- All the commands during the startup are NOPS, except these
  271. if startup_refresh_count = startup_refresh_max-31 then
  272. -- ensure all rows are closed
  273. iob_command <= CMD_PRECHARGE;
  274. iob_address(prefresh_cmd) <= '1'; -- all banks
  275. iob_bank <= (others => '0');
  276. elsif startup_refresh_count = startup_refresh_max-23 then
  277. -- these refreshes need to be at least tREF (66ns) apart
  278. iob_command <= CMD_REFRESH;
  279. elsif startup_refresh_count = startup_refresh_max-15 then
  280. iob_command <= CMD_REFRESH;
  281. elsif startup_refresh_count = startup_refresh_max-7 then
  282. -- Now load the mode register
  283. iob_command <= CMD_LOAD_MODE_REG;
  284. iob_address <= MODE_REG;
  285. end if;
  286. ------------------------------------------------------
  287. -- if startup is coomplete then go into idle mode,
  288. -- get prepared to accept a new command, and schedule
  289. -- the first refresh cycle
  290. ------------------------------------------------------
  291. if startup_refresh_count = 0 then
  292. state <= s_idle;
  293. ready_for_new <= '1';
  294. got_transaction <= '0';
  295. startup_refresh_count <= to_unsigned(2048 - cycles_per_refresh+1,14);
  296. end if;
  297. when s_idle_in_6 => state <= s_idle_in_5;
  298. when s_idle_in_5 => state <= s_idle_in_4;
  299. when s_idle_in_4 => state <= s_idle_in_3;
  300. when s_idle_in_3 => state <= s_idle_in_2;
  301. when s_idle_in_2 => state <= s_idle_in_1;
  302. when s_idle_in_1 => state <= s_idle;
  303. when s_idle =>
  304. -- Priority is to issue a refresh if one is outstanding
  305. if pending_refresh = '1' or forcing_refresh = '1' then
  306. ------------------------------------------------------------------------
  307. -- Start the refresh cycle.
  308. -- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
  309. ------------------------------------------------------------------------
  310. state <= s_idle_in_3;
  311. iob_command <= CMD_REFRESH;
  312. startup_refresh_count <= startup_refresh_count - cycles_per_refresh+1;
  313. elsif got_transaction = '1' then
  314. --------------------------------
  315. -- Start the read or write cycle.
  316. -- First task is to open the row
  317. --------------------------------
  318. state <= s_open_in_1;
  319. iob_command <= CMD_ACTIVE;
  320. iob_address <= save_row;
  321. iob_bank <= save_bank;
  322. end if;
  323. --------------------------------------------
  324. -- Opening the row ready for reads or writes
  325. --------------------------------------------
  326. when s_open_in_2 => state <= s_open_in_1;
  327. when s_open_in_1 =>
  328. -- still waiting for row to open
  329. if save_wr = '1' then
  330. state <= s_write_1;
  331. iob_dq_hiz <= '0';
  332. iob_data <= save_data_in(15 downto 0); -- get the DQ bus out of HiZ early
  333. else
  334. iob_dq_hiz <= '1';
  335. state <= s_read_1;
  336. end if;
  337. -- we will be ready for a new transaction next cycle!
  338. ready_for_new <= '1';
  339. got_transaction <= '0';
  340. ----------------------------------
  341. -- Processing the read transaction
  342. ----------------------------------
  343. when s_read_1 =>
  344. state <= s_read_2;
  345. iob_command <= CMD_READ;
  346. iob_address <= save_col;
  347. iob_bank <= save_bank;
  348. iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
  349. -- Schedule reading the data values off the bus
  350. data_ready_delay(data_ready_delay'high) <= '1';
  351. -- Set the data masks to read all bytes
  352. iob_dqm <= (others => '0');
  353. dqm_sr(1 downto 0) <= (others => '0');
  354. when s_read_2 =>
  355. state <= s_read_3;
  356. if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
  357. if save_wr = '0' then
  358. state <= s_read_1;
  359. ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
  360. end if;
  361. end if;
  362. when s_read_3 =>
  363. state <= s_read_4;
  364. if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
  365. if save_wr = '0' then
  366. state <= s_read_1;
  367. ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
  368. end if;
  369. end if;
  370. when s_read_4 =>
  371. state <= s_precharge;
  372. -- can we do back-to-back read?
  373. if forcing_refresh = '0' and got_transaction = '1' and can_back_to_back = '1' then
  374. if save_wr = '0' then
  375. state <= s_read_1;
  376. ready_for_new <= '1'; -- we will be ready for a new transaction next cycle!
  377. else
  378. state <= s_open_in_2; -- we have to wait for the read data to come back before we swutch the bus into HiZ
  379. end if;
  380. end if;
  381. ------------------------------------------------------------------
  382. -- Processing the write transaction
  383. -------------------------------------------------------------------
  384. when s_write_1 =>
  385. state <= s_write_2;
  386. iob_command <= CMD_WRITE;
  387. iob_address <= save_col;
  388. iob_address(prefresh_cmd) <= '0'; -- A10 actually matters - it selects auto precharge
  389. iob_bank <= save_bank;
  390. iob_dqm <= NOT save_byte_enable(1 downto 0);
  391. dqm_sr(1 downto 0) <= NOT save_byte_enable(3 downto 2);
  392. iob_data <= save_data_in(15 downto 0);
  393. iob_data_next <= save_data_in(31 downto 16);
  394. when s_write_2 =>
  395. state <= s_write_3;
  396. iob_data <= iob_data_next;
  397. when s_write_3 => -- must wait tRDL, hence the extra idle state
  398. iob_dq_hiz <= '1';
  399. state <= s_precharge;
  400. -------------------------------------------------------------------
  401. -- Closing the row off (this closes all banks)
  402. -------------------------------------------------------------------
  403. when s_precharge =>
  404. state <= s_idle_in_3;
  405. iob_command <= CMD_PRECHARGE;
  406. iob_address(prefresh_cmd) <= '1'; -- A10 actually matters - it selects all banks or just one
  407. -------------------------------------------------------------------
  408. -- We should never get here, but if we do then reset the memory
  409. -------------------------------------------------------------------
  410. when others =>
  411. state <= s_startup;
  412. ready_for_new <= '0';
  413. startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
  414. end case;
  415. if reset = '1' then -- Sync reset
  416. state <= s_startup;
  417. ready_for_new <= '0';
  418. startup_refresh_count <= startup_refresh_max-to_unsigned(sdram_startup_cycles,14);
  419. end if;
  420. end if;
  421. end process;
  422. end Behavioral;