MonZ80_template.vhd 1.9 KB

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  1. --+-----------------------------------+-------------------------------------+--
  2. --| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
  3. --| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
  4. --| / __|/ _ \ / __|_ / _ \| | | | | |--
  5. --| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
  6. --| |___/\___/ \___/___\___/ \___/ | |--
  7. --| | http://sowerbutts.com/ |--
  8. --+-----------------------------------+-------------------------------------+--
  9. --| An inferrable 4KB ROM to contain the monitor program |--
  10. --+-------------------------------------------------------------------------+--
  11. --
  12. -- MonZ80_template.vhd contains the template VHDL for the ROM but no actual
  13. -- data. The "ROMHERE" string is replaced by byte data by the "make_vhdl_rom"
  14. -- tool in software/tools which is invoked to generate "MonZ80.vhd" after
  15. -- the monitor program has been assembled.
  16. library ieee;
  17. use ieee.std_logic_1164.all;
  18. use ieee.numeric_std.all;
  19. entity MonZ80 is
  20. port(
  21. clk : in std_logic;
  22. a : in std_logic_vector(11 downto 0);
  23. d : out std_logic_vector(7 downto 0)
  24. );
  25. end MonZ80;
  26. architecture arch of MonZ80 is
  27. constant byte_rom_WIDTH: integer := 8;
  28. type byte_rom_type is array (0 to 4095) of std_logic_vector(byte_rom_WIDTH-1 downto 0);
  29. signal address_latch : std_logic_vector(11 downto 0) := (others => '0');
  30. -- actually memory cells
  31. signal byte_rom : byte_rom_type := (
  32. -- ROM contents follows
  33. %ROMHERE%
  34. );
  35. begin
  36. ram_process: process(clk, byte_rom)
  37. begin
  38. if rising_edge(clk) then
  39. -- latch the address, in order to infer a synchronous memory
  40. address_latch <= a;
  41. end if;
  42. end process;
  43. d <= byte_rom(to_integer(unsigned(address_latch)));
  44. end arch;