top_level_de0.vhd 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532
  1. --+-----------------------------------+-------------------------------------+--
  2. --| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
  3. --| ___ ___ ___ ___( _ ) / _ \ | will@sowerbutts.com |--
  4. --| / __|/ _ \ / __|_ / _ \| | | | | |--
  5. --| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
  6. --| |___/\___/ \___/___\___/ \___/ | |--
  7. --| | http://sowerbutts.com/ |--
  8. --+-----------------------------------+-------------------------------------+--
  9. --| Top level module: connects modules to each other and the outside world |--
  10. --+-------------------------------------------------------------------------+--
  11. --
  12. -- See README.txt for more details
  13. --
  14. library IEEE;
  15. use IEEE.STD_LOGIC_1164.ALL;
  16. use IEEE.NUMERIC_STD.ALL;
  17. use work.T80_Pack.ALL;
  18. entity top_level is
  19. Port (
  20. CLOCK_50 : in std_logic;
  21. LEDG : out std_logic_vector(9 downto 0);
  22. BUTTON : in std_logic_vector(2 downto 0);
  23. SW : in std_logic_vector(9 downto 0);
  24. -- UART0 (to MAX3232 level shifter chip, hardware flow control)
  25. UART_RXD : in std_logic;
  26. UART_TXD : out std_logic;
  27. -- GPIOs
  28. GPIO1_D : inout std_logic_vector(31 downto 0);
  29. GPIO0_D : inout std_logic_vector(31 downto 0);
  30. -- 7-SEG Display
  31. HEX0_D: out std_logic_vector(6 downto 0);
  32. --HEX0_DP: out std_logic;
  33. HEX1_D: out std_logic_vector(6 downto 0);
  34. --HEX1_DP: out std_logic;
  35. HEX2_D: out std_logic_vector(6 downto 0);
  36. --HEX2_DP: out std_logic;
  37. HEX3_D: out std_logic_vector(6 downto 0);
  38. --sHEX3_DP: out std_logic
  39. -- SD card socket
  40. SD_CLK : out std_logic;
  41. SD_CMD : in std_logic;
  42. SD_DAT0 : out std_logic;
  43. SD_DAT3 : out std_logic;
  44. SD_WP_N : in std_logic;
  45. -- SDRAM chip
  46. DRAM_CLK : out std_logic;
  47. DRAM_CKE : out std_logic;
  48. DRAM_CS_N : out std_logic;
  49. DRAM_RAS_N : out std_logic;
  50. DRAM_CAS_N : out std_logic;
  51. DRAM_WE_N : out std_logic;
  52. DRAM_DQM : out std_logic_vector( 1 downto 0);
  53. DRAM_ADDR : out std_logic_vector (12 downto 0);
  54. DRAM_BA : out std_logic_vector( 1 downto 0);
  55. DRAM_DQ : inout std_logic_vector (15 downto 0)
  56. );
  57. end top_level;
  58. architecture Behavioral of top_level is
  59. constant clk_freq_mhz : natural := 50; -- this is the frequency which the PLL outputs, in MHz.
  60. -- SDRAM configuration
  61. constant sdram_line_count : natural := 4096;
  62. constant sdram_address_width : natural := 22;
  63. constant sdram_column_bits : natural := 8;
  64. constant cycles_per_refresh : natural := (64000*clk_freq_mhz)/sdram_line_count-1;
  65. -- For simulation, we don't need a long init stage. but for real DRAM we need approx 101us.
  66. -- The constant below has a different value when interpreted by the synthesis and simulator
  67. -- tools in order to achieve the desired timing in each.
  68. constant sdram_startup_cycles: natural := 101 * clk_freq_mhz
  69. -- pragma translate_off
  70. - 10000 -- reduce the value the simulator uses
  71. -- pragma translate_on
  72. ;
  73. -- signals for clocking
  74. signal clk_feedback : std_logic; -- PLL clock feedback
  75. signal clk_unbuffered : std_logic; -- unbuffered system clock
  76. signal clk : std_logic; -- buffered system clock (all logic should be clocked by this)
  77. -- console latch
  78. signal console_select_clk1 : std_logic;
  79. signal console_select_sync : std_logic;
  80. signal swap_uart01 : std_logic := '0';
  81. -- system reset signals
  82. signal power_on_reset : std_logic_vector(1 downto 0) := (others => '1');
  83. signal system_reset : std_logic;
  84. signal reset_button_clk1 : std_logic;
  85. signal reset_button_sync : std_logic; -- reset button signal, synchronised to our clock
  86. signal reset_request_uart : std_logic; -- reset request signal from FTDI UART (when you send "!~!~!~" to the UART, this line is asserted)
  87. -- CPU control
  88. signal coldboot : std_logic;
  89. signal cpu_clk_enable : std_logic;
  90. signal cpu_m1_cycle : std_logic;
  91. signal cpu_req_mem : std_logic;
  92. signal cpu_req_io : std_logic;
  93. signal req_mem : std_logic;
  94. signal req_io : std_logic;
  95. signal req_read : std_logic;
  96. signal req_write : std_logic;
  97. signal virtual_address : std_logic_vector(15 downto 0);
  98. signal physical_address : std_logic_vector(25 downto 0);
  99. signal mem_wait : std_logic;
  100. signal cpu_wait : std_logic;
  101. signal dram_wait : std_logic;
  102. signal mmu_wait : std_logic;
  103. signal spimaster0_wait : std_logic;
  104. signal spimaster1_wait : std_logic;
  105. -- chip selects
  106. signal mmu_cs : std_logic;
  107. signal rom_cs : std_logic;
  108. signal sram_cs : std_logic;
  109. signal dram_cs : std_logic;
  110. signal uartA_cs : std_logic;
  111. signal uartB_cs : std_logic;
  112. signal uart0_cs : std_logic;
  113. signal uart1_cs : std_logic;
  114. signal timer_cs : std_logic;
  115. signal spimaster0_cs : std_logic;
  116. signal spimaster1_cs : std_logic;
  117. signal clkscale_cs : std_logic;
  118. signal gpio_cs : std_logic;
  119. -- data bus
  120. signal cpu_data_in : std_logic_vector(7 downto 0);
  121. signal cpu_data_out : std_logic_vector(7 downto 0);
  122. signal rom_data_out : std_logic_vector(7 downto 0);
  123. signal sram_data_out : std_logic_vector(7 downto 0);
  124. signal dram_data_out : std_logic_vector(7 downto 0);
  125. signal uart0_data_out : std_logic_vector(7 downto 0);
  126. signal uart1_data_out : std_logic_vector(7 downto 0);
  127. signal timer_data_out : std_logic_vector(7 downto 0);
  128. signal spimaster0_data_out : std_logic_vector(7 downto 0);
  129. signal spimaster1_data_out : std_logic_vector(7 downto 0);
  130. signal mmu_data_out : std_logic_vector(7 downto 0);
  131. signal clkscale_out : std_logic_vector(7 downto 0);
  132. signal gpio_data_out : std_logic_vector(7 downto 0);
  133. -- GPIO
  134. signal gpio_input : std_logic_vector(7 downto 0);
  135. signal gpio_output : std_logic_vector(7 downto 0);
  136. signal gpio_bank0_input : std_logic_vector(31 downto 0);
  137. signal gpio_bank0_output : std_logic_vector(31 downto 0);
  138. signal gpio_bank1_input : std_logic_vector(31 downto 0);
  139. signal gpio_bank1_output : std_logic_vector(31 downto 0);
  140. -- Interrupts
  141. signal cpu_interrupt_in : std_logic;
  142. signal timer_interrupt : std_logic;
  143. signal uart0_interrupt : std_logic;
  144. signal uart1_interrupt : std_logic;
  145. begin
  146. -- Hold CPU reset high for 8 clock cycles on startup,
  147. -- and when the user presses their reset button.
  148. process(clk)
  149. begin
  150. if rising_edge(clk) then
  151. -- Xilinx advises using two flip-flops are used to bring external
  152. -- signals which feed control logic into our clock domain.
  153. reset_button_clk1 <= not BUTTON(0);
  154. reset_button_sync <= reset_button_clk1;
  155. console_select_clk1 <= SW(9);
  156. console_select_sync <= console_select_clk1;
  157. -- reset the system when requested
  158. if (power_on_reset(0) = '1' or reset_button_sync = '1' or reset_request_uart = '1') then
  159. system_reset <= '1';
  160. else
  161. system_reset <= '0';
  162. end if;
  163. -- shift 0s into the power_on_reset shift register from the MSB
  164. power_on_reset <= '0' & power_on_reset(power_on_reset'length-1 downto 1);
  165. -- During reset, latch the console select jumper. This is used to
  166. -- optionally swap over the UART roles and move the system console to
  167. -- the second serial port on the IO board.
  168. if system_reset = '1' then
  169. swap_uart01 <= console_select_sync;
  170. else
  171. swap_uart01 <= swap_uart01;
  172. end if;
  173. end if;
  174. end process;
  175. -- GPIO input signal routing
  176. gpio_input(0) <= SW(0);
  177. gpio_input(1) <= SW(1);
  178. gpio_input(2) <= SW(2);
  179. gpio_input(3) <= SW(3);
  180. gpio_input(4) <= SW(4);
  181. gpio_input(5) <= SW(5);
  182. gpio_input(6) <= swap_uart01;
  183. gpio_input(7) <= coldboot;
  184. -- GPIO output signal routing
  185. LEDG(0) <= gpio_output(0);
  186. LEDG(1) <= gpio_output(1);
  187. LEDG(2) <= gpio_output(2);
  188. LEDG(3) <= gpio_output(3);
  189. LEDG(4) <= gpio_output(4);
  190. LEDG(5) <= gpio_output(5);
  191. LEDG(6) <= gpio_output(6);
  192. LEDG(7) <= gpio_output(7);
  193. -- User LED (LED1) on Papilio Pro indicates when the CPU is being asked to wait (eg by the SDRAM cache)
  194. LEDG(9) <= cpu_wait;
  195. --
  196. LEDG(8) <= clk or not(BUTTON(2));
  197. -- Interrupt signal for the CPU
  198. cpu_interrupt_in <= (timer_interrupt or uart0_interrupt or uart1_interrupt);
  199. -- 7 Seg
  200. seg0: entity work.DE0_SEG7 port map(virtual_address(3 downto 0), HEX0_D);
  201. seg1: entity work.DE0_SEG7 port map(virtual_address(7 downto 4), HEX1_D);
  202. seg2: entity work.DE0_SEG7 port map(virtual_address(11 downto 8), HEX2_D);
  203. seg3: entity work.DE0_SEG7 port map(virtual_address(15 downto 12), HEX3_D);
  204. -- Z80 CPU core
  205. cpu: entity work.Z80cpu
  206. port map (
  207. reset => system_reset,
  208. clk => clk,
  209. clk_enable => cpu_clk_enable,
  210. m1_cycle => cpu_m1_cycle,
  211. interrupt => cpu_interrupt_in,
  212. nmi => '0',
  213. req_mem => cpu_req_mem,
  214. req_io => cpu_req_io,
  215. req_read => req_read,
  216. req_write => req_write,
  217. mem_wait => cpu_wait,
  218. address => virtual_address,
  219. data_in => cpu_data_in,
  220. data_out => cpu_data_out
  221. );
  222. -- Memory management unit
  223. mmu: entity work.MMU
  224. port map (
  225. reset => system_reset,
  226. clk => clk,
  227. address_in => virtual_address,
  228. address_out => physical_address,
  229. cpu_data_in => cpu_data_out,
  230. cpu_data_out => mmu_data_out,
  231. req_mem_in => cpu_req_mem,
  232. req_io_in => cpu_req_io,
  233. req_mem_out => req_mem,
  234. req_io_out => req_io,
  235. req_read => req_read,
  236. req_write => req_write,
  237. io_cs => mmu_cs,
  238. cpu_wait => mmu_wait,
  239. access_violated => open -- for now!!
  240. );
  241. -- This process determines which IO or memory device the CPU is addressing
  242. -- and asserts the appropriate chip select signals.
  243. cs_process: process(req_mem, req_io, physical_address, virtual_address, uartA_cs, uartB_cs, swap_uart01)
  244. begin
  245. -- memory chip selects: default to unselected
  246. rom_cs <= '0';
  247. sram_cs <= '0';
  248. dram_cs <= '0';
  249. -- io chip selects: default to unselected
  250. uartA_cs <= '0';
  251. uartB_cs <= '0';
  252. mmu_cs <= '0';
  253. timer_cs <= '0';
  254. spimaster0_cs <= '0';
  255. spimaster1_cs <= '0';
  256. clkscale_cs <= '0';
  257. gpio_cs <= '0';
  258. -- memory address decoding
  259. -- address space is organised as:
  260. -- 0x0 000 000 - 0x0 FFF FFF 16MB DRAM (cached) (mapped to 8MB DRAM twice)
  261. -- 0x1 000 000 - 0x1 FFF FFF 16MB DRAM (uncached) (mapped to 8MB DRAM twice)
  262. -- 0x2 000 000 - 0x2 000 FFF 4KB monitor ROM (FPGA block RAM)
  263. -- 0x2 001 000 - 0x2 001 FFF 4KB SRAM (FPGA block RAM)
  264. -- 0x2 002 000 - 0x3 FFF FFF unused space for future expansion
  265. if physical_address(25) = '0' then
  266. -- bottom 32MB: DRAM handles this
  267. dram_cs <= req_mem;
  268. else
  269. -- top 32MB: other memory devices
  270. case physical_address(24 downto 12) is
  271. when "0000000000000" => rom_cs <= req_mem;
  272. when "0000000000001" => sram_cs <= req_mem;
  273. when others => -- undecoded memory space
  274. end case;
  275. end if;
  276. -- IO address decoding
  277. case virtual_address(7 downto 3) is
  278. when "00000" => uartA_cs <= req_io; -- 00 ... 07
  279. when "00010" => timer_cs <= req_io; -- 10 ... 17
  280. when "00011" => spimaster0_cs <= req_io; -- 18 ... 1F
  281. when "00100" => gpio_cs <= req_io; -- 20 ... 27
  282. when "00101" => uartB_cs <= req_io; -- 28 ... 2F
  283. when "00110" => spimaster1_cs <= req_io; -- 30 ... 37
  284. -- unused ports
  285. when "11110" => clkscale_cs <= req_io; -- F0 ... F7
  286. when "11111" => mmu_cs <= req_io; -- F8 ... FF
  287. when others =>
  288. end case;
  289. -- send the UART chip select to the appropriate UART depending
  290. -- on whether they have been swapped over or not.
  291. if swap_uart01 = '0' then
  292. uart0_cs <= uartB_cs;
  293. uart1_cs <= uartA_cs;
  294. else
  295. uart0_cs <= uartA_cs;
  296. uart1_cs <= uartB_cs;
  297. end if;
  298. end process;
  299. -- the selected memory device can request the CPU to wait
  300. mem_wait <=
  301. dram_wait when dram_cs='1' else
  302. spimaster0_wait when spimaster0_cs='1' else
  303. spimaster1_wait when spimaster1_cs='1' else
  304. '0';
  305. -- the MMU can, at any time, request the CPU wait (this is used when
  306. -- translating IO to memory requests, to implement a wait state for
  307. -- the "17th page")
  308. cpu_wait <= (mem_wait or mmu_wait);
  309. -- input mux for CPU data bus
  310. cpu_data_in <=
  311. rom_data_out when rom_cs='1' else
  312. dram_data_out when dram_cs='1' else
  313. sram_data_out when sram_cs='1' else
  314. uart0_data_out when uart0_cs='1' else
  315. uart1_data_out when uart1_cs='1' else
  316. timer_data_out when timer_cs='1' else
  317. mmu_data_out when mmu_cs='1' else
  318. spimaster0_data_out when spimaster0_cs='1' else
  319. spimaster1_data_out when spimaster1_cs='1' else
  320. clkscale_out when clkscale_cs='1' else
  321. gpio_data_out when gpio_cs='1' else
  322. rom_data_out; -- default case
  323. dram: entity work.DRAM
  324. generic map(
  325. sdram_address_width => sdram_address_width,
  326. sdram_column_bits => sdram_column_bits,
  327. sdram_startup_cycles=> sdram_startup_cycles,
  328. cycles_per_refresh => cycles_per_refresh
  329. )
  330. port map(
  331. clk => clk,
  332. reset => '0', -- important to note that we DO NOT reset the SDRAM controller on reset (it would stop refreshing, which would be bad)
  333. -- interface to synthetic CPU
  334. cs => dram_cs,
  335. req_read => req_read,
  336. req_write => req_write,
  337. mem_address => physical_address(24 downto 0),
  338. mem_wait => dram_wait,
  339. data_in => cpu_data_out,
  340. data_out => dram_data_out,
  341. coldboot => coldboot,
  342. -- interface to hardware SDRAM chip
  343. SDRAM_CLK => open,
  344. SDRAM_CKE => DRAM_CKE,
  345. SDRAM_CS => DRAM_CS_N,
  346. SDRAM_nCAS => DRAM_CAS_N,
  347. SDRAM_nRAS => DRAM_RAS_N,
  348. SDRAM_nWE => DRAM_WE_N,
  349. SDRAM_DQM => DRAM_DQM,
  350. SDRAM_BA => DRAM_BA,
  351. SDRAM_ADDR => DRAM_ADDR,
  352. SDRAM_DQ => DRAM_DQ
  353. );
  354. -- 4KB system ROM implemented in block RAM
  355. rom: entity work.MonZ80
  356. port map(
  357. clk => clk,
  358. A => physical_address(11 downto 0),
  359. D => rom_data_out
  360. );
  361. -- 4KB SRAM memory implemented in block RAM
  362. sram: entity work.SSRAM
  363. generic map(
  364. AddrWidth => 12
  365. )
  366. port map(
  367. clk => clk,
  368. ce => sram_cs,
  369. we => req_write,
  370. A => physical_address(11 downto 0),
  371. DIn => cpu_data_out,
  372. DOut => sram_data_out
  373. );
  374. -- UART connected to FTDI USB UART
  375. uart0: entity work.uart_interface
  376. generic map ( watch_for_reset => 1, clk_frequency => (clk_freq_mhz * 1000000) )
  377. port map(
  378. clk => clk,
  379. reset => system_reset,
  380. reset_out => reset_request_uart, -- result of watching for reset sequence on the input
  381. serial_in => UART_RXD,
  382. serial_out => UART_TXD,
  383. serial_rts => open,
  384. serial_cts => '0',
  385. cpu_address => virtual_address(2 downto 0),
  386. cpu_data_in => cpu_data_out,
  387. cpu_data_out => uart0_data_out,
  388. enable => uart0_cs,
  389. interrupt => uart0_interrupt,
  390. req_read => req_read,
  391. req_write => req_write
  392. );
  393. -- UART connected to two GPIOs (1(30), 1(31))
  394. uart1: entity work.uart_interface
  395. generic map ( watch_for_reset => 1, clk_frequency => (clk_freq_mhz * 1000000) )
  396. port map(
  397. clk => clk,
  398. reset => system_reset,
  399. reset_out => open,
  400. serial_in => GPIO1_D(30),
  401. serial_out => GPIO1_D(31),
  402. serial_rts => open,
  403. serial_cts => '0',
  404. cpu_address => virtual_address(2 downto 0),
  405. cpu_data_in => cpu_data_out,
  406. cpu_data_out => uart1_data_out,
  407. enable => uart1_cs,
  408. interrupt => uart1_interrupt,
  409. req_read => req_read,
  410. req_write => req_write
  411. );
  412. -- Timer device (internally scales the clock to 1MHz)
  413. timer: entity work.timer
  414. generic map ( clk_frequency => (clk_freq_mhz * 1000000) )
  415. port map(
  416. clk => clk,
  417. reset => system_reset,
  418. cpu_address => virtual_address(2 downto 0),
  419. data_in => cpu_data_out,
  420. data_out => timer_data_out,
  421. enable => timer_cs,
  422. req_read => req_read,
  423. req_write => req_write,
  424. interrupt => timer_interrupt
  425. );
  426. -- GPIO to FPGA pins and/or internal signals
  427. gpio: entity work.gpio
  428. port map(
  429. clk => clk,
  430. reset => system_reset,
  431. cpu_address => virtual_address(2 downto 0),
  432. data_in => cpu_data_out,
  433. data_out => gpio_data_out,
  434. enable => gpio_cs,
  435. read_notwrite => req_read,
  436. input_pins => gpio_input,
  437. output_pins => gpio_output
  438. );
  439. -- SPI master device connected to SD card socket on the IO board
  440. spimaster1: entity work.spimaster
  441. port map(
  442. clk => clk,
  443. reset => system_reset,
  444. cpu_address => virtual_address(2 downto 0),
  445. cpu_wait => spimaster1_wait,
  446. data_in => cpu_data_out,
  447. data_out => spimaster1_data_out,
  448. enable => spimaster1_cs,
  449. req_read => req_read,
  450. req_write => req_write,
  451. slave_cs => SD_DAT3,
  452. slave_clk => SD_CLK,
  453. slave_mosi => SD_DAT0,
  454. slave_miso => SD_CMD
  455. );
  456. -- An attempt to allow the CPU clock to be scaled back to run
  457. -- at slower speeds without affecting the clock signal sent to
  458. -- IO devices. Basically this was an attempt to make CP/M games
  459. -- playable :) Very limited success. Might be simpler to remove
  460. -- this entirely.
  461. clkscale: entity work.clkscale
  462. port map (
  463. clk => clk,
  464. reset => system_reset,
  465. cpu_address => virtual_address(2 downto 0),
  466. data_in => cpu_data_out,
  467. data_out => clkscale_out,
  468. enable => clkscale_cs,
  469. read_notwrite => req_read,
  470. clk_enable => cpu_clk_enable
  471. );
  472. pll: entity work.pll
  473. port map (
  474. areset => open,
  475. inclk0 => CLOCK_50,
  476. c0 => DRAM_CLK, -- 100 Mhz - 180 deg
  477. c1 => clk, -- 100 Mhz
  478. locked => open
  479. );
  480. end Behavioral;