spi.c 5.0 KB

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  1. /* Sd2iec - SD/MMC to Commodore serial bus interface/controller
  2. Copyright (C) 2007-2010 Ingo Korb <ingo@akana.de>
  3. Inspiration and low-level SD/MMC access based on code from MMC2IEC
  4. by Lars Pontoppidan et al., see sdcard.c|h and config.h.
  5. FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; version 2 of the License only.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. spi.c: Low-level SPI routines
  17. */
  18. #include <arm/NXP/LPC17xx/LPC17xx.h>
  19. #include "bits.h"
  20. #include "config.h"
  21. #include "spi.h"
  22. #include "uart.h"
  23. void spi_preinit() {
  24. /* Set clock prescaler to 1:1 */
  25. BITBAND(LPC_SC->SSP_PCLKREG, SSP_PCLKBIT) = 1;
  26. }
  27. void spi_init() {
  28. /* configure data format - 8 bits, SPI, CPOL=0, CPHA=0, 1 clock per bit */
  29. SSP_REGS->CR0 = (8-1);
  30. /* set clock prescaler */
  31. SSP_REGS->CPSR = SSP_CLK_DIVISOR;
  32. /* Enable SSP */
  33. SSP_REGS->CR1 = BV(1);
  34. /* Enable DMA controller, little-endian mode */
  35. BITBAND(LPC_SC->PCONP, 29) = 1;
  36. LPC_GPDMA->DMACConfig = 1;
  37. }
  38. void spi_tx_sync() {
  39. /* Wait until TX fifo is flushed */
  40. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  41. }
  42. void spi_tx_byte(uint8_t data) {
  43. /* Wait until TX fifo can accept data */
  44. while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ;
  45. /* Send byte */
  46. SSP_REGS->DR = data;
  47. }
  48. uint8_t spi_txrx_byte(uint8_t data) {
  49. /* Wait until SSP is not busy */
  50. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  51. /* Clear RX fifo */
  52. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  53. (void) SSP_REGS->DR;
  54. /* Transmit a single byte */
  55. SSP_REGS->DR = data;
  56. /* Wait until answer has been received */
  57. while (!BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  58. return SSP_REGS->DR;
  59. }
  60. uint8_t spi_rx_byte() {
  61. /* Wait until SSP is not busy */
  62. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  63. /* Clear RX fifo */
  64. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  65. (void) SSP_REGS->DR;
  66. /* Transmit a single dummy byte */
  67. SSP_REGS->DR = 0xff;
  68. /* Wait until answer has been received */
  69. while (!BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  70. return SSP_REGS->DR;
  71. }
  72. void spi_tx_block(const void *ptr, unsigned int length) {
  73. const uint8_t *data = (const uint8_t *)ptr;
  74. while (length--) {
  75. /* Wait until TX fifo can accept data */
  76. while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ;
  77. SSP_REGS->DR = *data++;
  78. }
  79. }
  80. void spi_rx_block(void *ptr, unsigned int length) {
  81. uint8_t *data = (uint8_t *)ptr;
  82. unsigned int txlen = length;
  83. /* Wait until SSP is not busy */
  84. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  85. /* Clear RX fifo */
  86. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  87. (void) SSP_REGS->DR;
  88. if ((length & 3) != 0 || ((uint32_t)ptr & 3) != 0) {
  89. /* Odd length or unaligned buffer */
  90. while (length > 0) {
  91. /* Wait until TX or RX FIFO are ready */
  92. while (txlen > 0 && !BITBAND(SSP_REGS->SR, SSP_TNF) &&
  93. !BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  94. /* Try to receive data */
  95. while (length > 0 && BITBAND(SSP_REGS->SR, SSP_RNE)) {
  96. *data++ = SSP_REGS->DR;
  97. length--;
  98. }
  99. /* Send dummy data until TX full or RX ready */
  100. while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF) && !BITBAND(SSP_REGS->SR, SSP_RNE)) {
  101. txlen--;
  102. SSP_REGS->DR = 0xff;
  103. }
  104. }
  105. } else {
  106. /* Clear interrupt flags of DMA channels 0 */
  107. LPC_GPDMA->DMACIntTCClear = BV(0);
  108. LPC_GPDMA->DMACIntErrClr = BV(0);
  109. /* Set up RX DMA channel */
  110. SSP_DMACH->DMACCSrcAddr = (uint32_t)&SSP_REGS->DR;
  111. SSP_DMACH->DMACCDestAddr = (uint32_t)ptr;
  112. SSP_DMACH->DMACCLLI = 0; // no linked list
  113. SSP_DMACH->DMACCControl = length
  114. | (0 << 12) // source burst size 1 (FIXME: Check if larger possible/useful)
  115. | (0 << 15) // destination burst size 1
  116. | (0 << 18) // source transfer width 1 byte
  117. | (2 << 21) // destination transfer width 4 bytes
  118. | (0 << 26) // source address not incremented
  119. | (1 << 27) // destination address incremented
  120. ;
  121. SSP_DMACH->DMACCConfig = 1 // enable channel
  122. | (SSP_DMAID_RX << 1) // data source SSP RX
  123. | (2 << 11) // transfer from peripheral to memory
  124. ;
  125. /* Enable RX FIFO DMA */
  126. SSP_REGS->DMACR = 1;
  127. /* Write <length> bytes into TX FIFO */
  128. // FIXME: Any value in doing this using DMA too?
  129. while (txlen > 0) {
  130. while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF)) {
  131. txlen--;
  132. SSP_REGS->DR = 0xff;
  133. }
  134. }
  135. /* Wait until DMA channel disables itself */
  136. while (SSP_DMACH->DMACCConfig & 1) ;
  137. /* Disable RX FIFO DMA */
  138. SSP_REGS->DMACR = 0;
  139. }
  140. }