mcu_cmd.v 14 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 21:57:50 08/25/2009
  7. // Design Name:
  8. // Module Name: mcu_cmd
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module mcu_cmd(
  22. input clk,
  23. input cmd_ready,
  24. input param_ready,
  25. input [7:0] cmd_data,
  26. input [7:0] param_data,
  27. output [3:0] mcu_mapper,
  28. output [3:0] mcu_sram_size,
  29. output mcu_rrq,
  30. output mcu_write,
  31. output mcu_wrq,
  32. input mcu_rq_rdy,
  33. output [7:0] mcu_data_out,
  34. input [7:0] mcu_data_in,
  35. output [7:0] spi_data_out,
  36. input [31:0] spi_byte_cnt,
  37. input [2:0] spi_bit_cnt,
  38. output [23:0] addr_out,
  39. output [3:0] mapper,
  40. input endmessage,
  41. input startmessage,
  42. output [23:0] saveram_mask_out,
  43. output [23:0] rom_mask_out,
  44. // SD "DMA" extension
  45. output SD_DMA_EN,
  46. input SD_DMA_STATUS,
  47. input SD_DMA_NEXTADDR,
  48. input [7:0] SD_DMA_SRAM_DATA,
  49. input SD_DMA_SRAM_WE,
  50. output [1:0] SD_DMA_TGT,
  51. output SD_DMA_PARTIAL,
  52. output [11:0] SD_DMA_PARTIAL_START,
  53. output [11:0] SD_DMA_PARTIAL_END,
  54. // DAC
  55. output [10:0] dac_addr_out,
  56. // output [7:0] dac_volume_out,
  57. // output dac_volume_latch_out,
  58. input DAC_STATUS,
  59. output dac_play_out,
  60. output dac_reset_out,
  61. // MSU data
  62. output [13:0] msu_addr_out,
  63. input [6:0] MSU_STATUS,
  64. output [5:0] msu_status_reset_out,
  65. output [5:0] msu_status_set_out,
  66. output msu_status_reset_we,
  67. input [31:0] msu_addressrq,
  68. input [15:0] msu_trackrq,
  69. input [7:0] msu_volumerq,
  70. output [13:0] msu_ptr_out,
  71. output msu_reset_out,
  72. // BS-X
  73. output [7:0] bsx_regs_reset_out,
  74. output [7:0] bsx_regs_set_out,
  75. output bsx_regs_reset_we,
  76. // generic RTC
  77. output [55:0] rtc_data_out,
  78. output rtc_pgm_we,
  79. // S-RTC
  80. output srtc_reset,
  81. // uPD77C25
  82. output reg [23:0] dspx_pgm_data_out,
  83. output reg [10:0] dspx_pgm_addr_out,
  84. output reg dspx_pgm_we_out,
  85. output reg [15:0] dspx_dat_data_out,
  86. output reg [10:0] dspx_dat_addr_out,
  87. output reg dspx_dat_we_out,
  88. output reg dspx_reset_out,
  89. // feature enable
  90. output reg [7:0] featurebits_out,
  91. // SNES sync/clk
  92. input snes_sysclk
  93. );
  94. initial begin
  95. dspx_pgm_addr_out = 11'b00000000000;
  96. dspx_dat_addr_out = 10'b0000000000;
  97. dspx_reset_out = 1'b1;
  98. end
  99. wire [31:0] snes_sysclk_freq;
  100. clk_test snes_clk_test (
  101. .clk(clk),
  102. .sysclk(snes_sysclk),
  103. .snes_sysclk_freq(snes_sysclk_freq)
  104. );
  105. reg [3:0] MAPPER_BUF;
  106. reg [3:0] SRAM_SIZE_BUF;
  107. reg MCU_READ_BUF;
  108. reg MCU_WRITE_BUF;
  109. reg [23:0] ADDR_OUT_BUF;
  110. reg [10:0] DAC_ADDR_OUT_BUF;
  111. reg [7:0] DAC_VOL_OUT_BUF;
  112. reg DAC_VOL_LATCH_BUF;
  113. reg DAC_PLAY_OUT_BUF;
  114. reg DAC_RESET_OUT_BUF;
  115. reg [13:0] MSU_ADDR_OUT_BUF;
  116. reg [13:0] MSU_PTR_OUT_BUF;
  117. reg [5:0] msu_status_set_out_buf;
  118. reg [5:0] msu_status_reset_out_buf;
  119. reg msu_status_reset_we_buf;
  120. reg MSU_RESET_OUT_BUF;
  121. reg [7:0] bsx_regs_set_out_buf;
  122. reg [7:0] bsx_regs_reset_out_buf;
  123. reg bsx_regs_reset_we_buf;
  124. reg [55:0] rtc_data_out_buf;
  125. reg rtc_pgm_we_buf;
  126. reg srtc_reset_buf;
  127. reg [31:0] SNES_SYSCLK_FREQ_BUF;
  128. reg [7:0] MCU_DATA_OUT_BUF;
  129. reg [7:0] MCU_DATA_IN_BUF;
  130. reg [1:0] mcu_nextaddr_buf;
  131. reg mcu_nextaddr_r;
  132. reg SD_DMA_NEXTADDRr;
  133. always @(posedge clk) SD_DMA_NEXTADDRr <= SD_DMA_NEXTADDR;
  134. wire mcu_nextaddr;
  135. reg DAC_STATUSr;
  136. reg SD_DMA_STATUSr;
  137. reg [6:0] MSU_STATUSr;
  138. always @(posedge clk) begin
  139. DAC_STATUSr <= DAC_STATUS;
  140. SD_DMA_STATUSr <= SD_DMA_STATUS;
  141. MSU_STATUSr <= MSU_STATUS;
  142. end
  143. reg SD_DMA_PARTIALr;
  144. assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
  145. reg SD_DMA_ENr;
  146. assign SD_DMA_EN = SD_DMA_ENr;
  147. reg [1:0] SD_DMA_TGTr;
  148. assign SD_DMA_TGT = SD_DMA_TGTr;
  149. reg [11:0] SD_DMA_PARTIAL_STARTr;
  150. reg [11:0] SD_DMA_PARTIAL_ENDr;
  151. assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
  152. assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
  153. reg [2:0] spi_dma_nextaddr_r;
  154. reg [1:0] SRAM_MASK_IDX;
  155. reg [23:0] SAVERAM_MASK;
  156. reg [23:0] ROM_MASK;
  157. assign spi_data_out = MCU_DATA_IN_BUF;
  158. initial begin
  159. ADDR_OUT_BUF = 0;
  160. DAC_ADDR_OUT_BUF = 0;
  161. MSU_ADDR_OUT_BUF = 0;
  162. DAC_VOL_OUT_BUF = 0;
  163. DAC_VOL_LATCH_BUF = 0;
  164. spi_dma_nextaddr_r = 0;
  165. SD_DMA_ENr = 0;
  166. MAPPER_BUF = 1;
  167. end
  168. // command interpretation
  169. always @(posedge clk) begin
  170. if (cmd_ready) begin
  171. case (cmd_data[7:4])
  172. 4'h3: // select mapper
  173. MAPPER_BUF <= cmd_data[3:0];
  174. 4'h4: begin// SD DMA
  175. SD_DMA_ENr <= 1;
  176. SD_DMA_TGTr <= cmd_data[1:0];
  177. SD_DMA_PARTIALr <= cmd_data[2];
  178. end
  179. 4'h8: SD_DMA_TGTr <= 2'b00;
  180. 4'h9: SD_DMA_TGTr <= cmd_data[1:0]; // not implemented
  181. // 4'hE:
  182. // select memory unit
  183. endcase
  184. end else if (param_ready) begin
  185. casex (cmd_data[7:0])
  186. 8'h1x:
  187. case (spi_byte_cnt)
  188. 32'h2:
  189. ROM_MASK[23:16] <= param_data;
  190. 32'h3:
  191. ROM_MASK[15:8] <= param_data;
  192. 32'h4:
  193. ROM_MASK[7:0] <= param_data;
  194. endcase
  195. 8'h2x:
  196. case (spi_byte_cnt)
  197. 32'h2:
  198. SAVERAM_MASK[23:16] <= param_data;
  199. 32'h3:
  200. SAVERAM_MASK[15:8] <= param_data;
  201. 32'h4:
  202. SAVERAM_MASK[7:0] <= param_data;
  203. endcase
  204. 8'h4x:
  205. SD_DMA_ENr <= 1'b0;
  206. // 8'h5x:
  207. // case (spi_byte_cnt)
  208. // 32'h2:
  209. // DAC_VOL_OUT_BUF <= param_data;
  210. // 32'h3:
  211. // DAC_VOL_LATCH_BUF <= 1'b1;
  212. // 32'h4:
  213. // DAC_VOL_LATCH_BUF <= 1'b0;
  214. // endcase
  215. 8'h6x:
  216. case (spi_byte_cnt)
  217. 32'h2:
  218. SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
  219. 32'h3:
  220. SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
  221. 32'h4:
  222. SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
  223. 32'h5:
  224. SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
  225. endcase
  226. 8'h9x:
  227. MCU_DATA_OUT_BUF <= param_data;
  228. 8'he0:
  229. case (spi_byte_cnt)
  230. 32'h2: begin
  231. msu_status_set_out_buf <= param_data[5:0];
  232. end
  233. 32'h3: begin
  234. msu_status_reset_out_buf <= param_data[5:0];
  235. msu_status_reset_we_buf <= 1'b1;
  236. end
  237. 32'h4:
  238. msu_status_reset_we_buf <= 1'b0;
  239. endcase
  240. 8'he1: // pause DAC
  241. DAC_PLAY_OUT_BUF <= 1'b0;
  242. 8'he2: // resume DAC
  243. DAC_PLAY_OUT_BUF <= 1'b1;
  244. 8'he3: // reset DAC (set DAC playback address = 0)
  245. case (spi_byte_cnt)
  246. 32'h2:
  247. DAC_RESET_OUT_BUF <= 1'b1;
  248. 32'h3:
  249. DAC_RESET_OUT_BUF <= 1'b0;
  250. endcase
  251. 8'he4: // reset MSU read buffer pointer
  252. case (spi_byte_cnt)
  253. 32'h2: begin
  254. MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
  255. MSU_PTR_OUT_BUF[7:0] <= 8'h0;
  256. end
  257. 32'h3: begin
  258. MSU_PTR_OUT_BUF[7:0] <= param_data;
  259. MSU_RESET_OUT_BUF <= 1'b1;
  260. end
  261. 32'h4:
  262. MSU_RESET_OUT_BUF <= 1'b0;
  263. endcase
  264. 8'he5:
  265. case (spi_byte_cnt)
  266. 32'h2:
  267. rtc_data_out_buf[55:48] <= param_data;
  268. 32'h3:
  269. rtc_data_out_buf[47:40] <= param_data;
  270. 32'h4:
  271. rtc_data_out_buf[39:32] <= param_data;
  272. 32'h5:
  273. rtc_data_out_buf[31:24] <= param_data;
  274. 32'h6:
  275. rtc_data_out_buf[23:16] <= param_data;
  276. 32'h7:
  277. rtc_data_out_buf[15:8] <= param_data;
  278. 32'h8: begin
  279. rtc_data_out_buf[7:0] <= param_data;
  280. rtc_pgm_we_buf <= 1'b1;
  281. end
  282. 32'h9:
  283. rtc_pgm_we_buf <= 1'b0;
  284. endcase
  285. 8'he6:
  286. case (spi_byte_cnt)
  287. 32'h2: begin
  288. bsx_regs_set_out_buf <= param_data[7:0];
  289. end
  290. 32'h3: begin
  291. bsx_regs_reset_out_buf <= param_data[7:0];
  292. bsx_regs_reset_we_buf <= 1'b1;
  293. end
  294. 32'h4:
  295. bsx_regs_reset_we_buf <= 1'b0;
  296. endcase
  297. 8'he7:
  298. case (spi_byte_cnt)
  299. 32'h2: begin
  300. srtc_reset_buf <= 1'b1;
  301. end
  302. 32'h3: begin
  303. srtc_reset_buf <= 1'b0;
  304. end
  305. endcase
  306. 8'he8: begin// reset DSPx PGM+DAT address
  307. case (spi_byte_cnt)
  308. 32'h2: begin
  309. dspx_pgm_addr_out <= 11'b00000000000;
  310. dspx_dat_addr_out <= 10'b0000000000;
  311. end
  312. endcase
  313. end
  314. 8'he9:// write DSPx PGM w/ increment
  315. case (spi_byte_cnt)
  316. 32'h2: dspx_pgm_data_out[23:16] <= param_data[7:0];
  317. 32'h3: dspx_pgm_data_out[15:8] <= param_data[7:0];
  318. 32'h4: dspx_pgm_data_out[7:0] <= param_data[7:0];
  319. 32'h5: dspx_pgm_we_out <= 1'b1;
  320. 32'h6: begin
  321. dspx_pgm_we_out <= 1'b0;
  322. dspx_pgm_addr_out <= dspx_pgm_addr_out + 1;
  323. end
  324. endcase
  325. 8'hea:// write DSPx DAT w/ increment
  326. case (spi_byte_cnt)
  327. 32'h2: dspx_dat_data_out[15:8] <= param_data[7:0];
  328. 32'h3: dspx_dat_data_out[7:0] <= param_data[7:0];
  329. 32'h4: dspx_dat_we_out <= 1'b1;
  330. 32'h5: begin
  331. dspx_dat_we_out <= 1'b0;
  332. dspx_dat_addr_out <= dspx_dat_addr_out + 1;
  333. end
  334. endcase
  335. 8'heb: // put DSPx into reset
  336. dspx_reset_out <= 1'b1;
  337. 8'hec: // release DSPx reset
  338. dspx_reset_out <= 1'b0;
  339. 8'hed:
  340. featurebits_out <= param_data[7:0];
  341. endcase
  342. end
  343. end
  344. always @(posedge clk) begin
  345. if(param_ready && cmd_data[7:4] == 4'h0) begin
  346. case (cmd_data[1:0])
  347. 2'b01: begin
  348. case (spi_byte_cnt)
  349. 32'h2: begin
  350. DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
  351. DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
  352. end
  353. 32'h3:
  354. DAC_ADDR_OUT_BUF[7:0] <= param_data;
  355. endcase
  356. end
  357. 2'b10: begin
  358. case (spi_byte_cnt)
  359. 32'h2: begin
  360. MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
  361. MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
  362. end
  363. 32'h3:
  364. MSU_ADDR_OUT_BUF[7:0] <= param_data;
  365. endcase
  366. end
  367. default:
  368. case (spi_byte_cnt)
  369. 32'h2: begin
  370. ADDR_OUT_BUF[23:16] <= param_data;
  371. ADDR_OUT_BUF[15:0] <= 16'b0;
  372. end
  373. 32'h3:
  374. ADDR_OUT_BUF[15:8] <= param_data;
  375. 32'h4:
  376. ADDR_OUT_BUF[7:0] <= param_data;
  377. endcase
  378. endcase
  379. end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
  380. && (cmd_data[3])
  381. && (spi_byte_cnt >= (32'h1+cmd_data[4])))
  382. )
  383. begin
  384. case (SD_DMA_TGTr)
  385. 2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
  386. 2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
  387. 2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
  388. endcase
  389. end
  390. end
  391. // value fetch during last SPI bit
  392. always @(posedge clk) begin
  393. if (cmd_data[7:4] == 4'h8 && mcu_nextaddr_buf == 2'b01)
  394. MCU_DATA_IN_BUF <= mcu_data_in;
  395. else if (spi_bit_cnt == 3'h7) begin
  396. if (cmd_data[7:0] == 8'hF0)
  397. MCU_DATA_IN_BUF <= 8'hA5;
  398. else if (cmd_data[7:0] == 8'hF1)
  399. case (spi_byte_cnt[0])
  400. 1'b1: // buffer status (1st byte)
  401. MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[6], 5'b0};
  402. 1'b0: // control status (2nd byte)
  403. MCU_DATA_IN_BUF <= {2'b0, MSU_STATUSr[5:0]};
  404. endcase
  405. else if (cmd_data[7:0] == 8'hF2)
  406. case (spi_byte_cnt)
  407. 32'h1:
  408. MCU_DATA_IN_BUF <= msu_addressrq[31:24];
  409. 32'h2:
  410. MCU_DATA_IN_BUF <= msu_addressrq[23:16];
  411. 32'h3:
  412. MCU_DATA_IN_BUF <= msu_addressrq[15:8];
  413. 32'h4:
  414. MCU_DATA_IN_BUF <= msu_addressrq[7:0];
  415. endcase
  416. else if (cmd_data[7:0] == 8'hF3)
  417. case (spi_byte_cnt)
  418. 32'h1:
  419. MCU_DATA_IN_BUF <= msu_trackrq[15:8];
  420. 32'h2:
  421. MCU_DATA_IN_BUF <= msu_trackrq[7:0];
  422. endcase
  423. else if (cmd_data[7:0] == 8'hF4)
  424. MCU_DATA_IN_BUF <= msu_volumerq;
  425. else if (cmd_data[7:0] == 8'hFE)
  426. case (spi_byte_cnt)
  427. 32'h1:
  428. SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
  429. 32'h2:
  430. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  431. 32'h3:
  432. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  433. 32'h4:
  434. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  435. 32'h5:
  436. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  437. endcase
  438. else if (cmd_data[7:0] == 8'hFF)
  439. MCU_DATA_IN_BUF <= param_data;
  440. end
  441. end
  442. // nextaddr pulse generation
  443. always @(posedge clk) begin
  444. mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], mcu_rq_rdy};
  445. end
  446. parameter ST_RRQ = 4'b0001;
  447. parameter ST_WAIT = 4'b0010;
  448. parameter ST_NEXT = 4'b0100;
  449. parameter ST_IDLE = 4'b1000;
  450. reg [3:0] rrq_state;
  451. initial rrq_state = ST_IDLE;
  452. reg [2:0] rrq_wait;
  453. reg mcu_rrq_r;
  454. reg [3:0] wrq_state;
  455. initial wrq_state = ST_IDLE;
  456. reg [2:0] wrq_wait;
  457. reg mcu_wrq_r;
  458. always @(posedge clk) begin
  459. case(rrq_state)
  460. ST_IDLE: begin
  461. mcu_nextaddr_r <= 1'b0;
  462. if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
  463. mcu_rrq_r <= 1'b1;
  464. rrq_state <= ST_RRQ;
  465. end else
  466. rrq_state <= ST_IDLE;
  467. end
  468. ST_RRQ: begin
  469. mcu_rrq_r <= 1'b0;
  470. rrq_state <= ST_IDLE;
  471. end
  472. endcase
  473. end
  474. always @(posedge clk) begin
  475. case(wrq_state)
  476. ST_IDLE: begin
  477. mcu_nextaddr_r <= 1'b0;
  478. if(param_ready && cmd_data[7:4] == 4'h9) begin
  479. mcu_wrq_r <= 1'b1;
  480. wrq_state <= ST_RRQ;
  481. end else
  482. wrq_state <= ST_IDLE;
  483. end
  484. ST_RRQ: begin
  485. mcu_wrq_r <= 1'b0;
  486. wrq_state <= ST_IDLE;
  487. end
  488. endcase
  489. end
  490. // trigger for nextaddr
  491. assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
  492. assign mcu_rrq = mcu_rrq_r;
  493. assign mcu_wrq = mcu_wrq_r;
  494. assign mcu_write = SD_DMA_STATUS
  495. ?(SD_DMA_TGTr == 2'b00
  496. ?SD_DMA_SRAM_WE
  497. :1'b1
  498. )
  499. : 1'b1;
  500. assign addr_out = ADDR_OUT_BUF;
  501. assign dac_addr_out = DAC_ADDR_OUT_BUF;
  502. assign msu_addr_out = MSU_ADDR_OUT_BUF;
  503. assign dac_volume_out = DAC_VOL_OUT_BUF;
  504. assign dac_volume_latch_out = DAC_VOL_LATCH_BUF;
  505. assign dac_play_out = DAC_PLAY_OUT_BUF;
  506. assign dac_reset_out = DAC_RESET_OUT_BUF;
  507. assign msu_status_reset_we = msu_status_reset_we_buf;
  508. assign msu_status_reset_out = msu_status_reset_out_buf;
  509. assign msu_status_set_out = msu_status_set_out_buf;
  510. assign msu_reset_out = MSU_RESET_OUT_BUF;
  511. assign msu_ptr_out = MSU_PTR_OUT_BUF;
  512. assign bsx_regs_reset_we = bsx_regs_reset_we_buf;
  513. assign bsx_regs_reset_out = bsx_regs_reset_out_buf;
  514. assign bsx_regs_set_out = bsx_regs_set_out_buf;
  515. assign rtc_data_out = rtc_data_out_buf;
  516. assign rtc_pgm_we = rtc_pgm_we_buf;
  517. assign srtc_reset = srtc_reset_buf;
  518. assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
  519. assign mcu_mapper = MAPPER_BUF;
  520. assign mcu_sram_size = SRAM_SIZE_BUF;
  521. assign rom_mask_out = ROM_MASK;
  522. assign saveram_mask_out = SAVERAM_MASK;
  523. endmodule