main.v 18 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. inout SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. output IRQ_DIR,
  36. input SNES_SYSCLK,
  37. /* SRAM signals */
  38. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  39. inout [15:0] ROM_DATA,
  40. output [22:0] ROM_ADDR,
  41. output ROM_CE,
  42. output ROM_OE,
  43. output ROM_WE,
  44. output ROM_BHE,
  45. output ROM_BLE,
  46. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  47. inout [7:0] RAM_DATA,
  48. output [18:0] RAM_ADDR,
  49. output RAM_CE,
  50. output RAM_OE,
  51. output RAM_WE,
  52. /* MCU signals */
  53. input SPI_MOSI,
  54. inout SPI_MISO,
  55. input SPI_SS,
  56. inout SPI_SCK,
  57. input MCU_OVR,
  58. output MCU_RDY,
  59. output DAC_MCLK,
  60. output DAC_LRCK,
  61. output DAC_SDOUT,
  62. /* SD signals */
  63. input [3:0] SD_DAT,
  64. inout SD_CMD,
  65. inout SD_CLK,
  66. /* debug */
  67. output p113_out
  68. );
  69. wire dspx_dp_enable;
  70. wire [7:0] spi_cmd_data;
  71. wire [7:0] spi_param_data;
  72. wire [7:0] spi_input_data;
  73. wire [31:0] spi_byte_cnt;
  74. wire [2:0] spi_bit_cnt;
  75. wire [23:0] MCU_ADDR;
  76. wire [7:0] mcu_data_in;
  77. wire [7:0] mcu_data_out;
  78. wire [3:0] MAPPER;
  79. wire [23:0] SAVERAM_MASK;
  80. wire [23:0] ROM_MASK;
  81. wire [7:0] SD_DMA_SRAM_DATA;
  82. wire [1:0] SD_DMA_TGT;
  83. wire [10:0] SD_DMA_PARTIAL_START;
  84. wire [10:0] SD_DMA_PARTIAL_END;
  85. wire [10:0] dac_addr;
  86. //wire [7:0] dac_volume;
  87. wire [7:0] msu_volumerq_out;
  88. wire [6:0] msu_status_out;
  89. wire [31:0] msu_addressrq_out;
  90. wire [15:0] msu_trackrq_out;
  91. wire [13:0] msu_write_addr;
  92. wire [13:0] msu_ptr_addr;
  93. wire [7:0] MSU_SNES_DATA_IN;
  94. wire [7:0] MSU_SNES_DATA_OUT;
  95. wire [5:0] msu_status_reset_bits;
  96. wire [5:0] msu_status_set_bits;
  97. wire [14:0] bsx_regs;
  98. wire [14:0] bsx_regs_in;
  99. wire [7:0] BSX_SNES_DATA_IN;
  100. wire [7:0] BSX_SNES_DATA_OUT;
  101. wire [7:0] bsx_regs_reset_bits;
  102. wire [7:0] bsx_regs_set_bits;
  103. wire [59:0] rtc_data;
  104. wire [59:0] rtc_data_in;
  105. wire [59:0] srtc_rtc_data_out;
  106. wire [7:0] SRTC_SNES_DATA_IN;
  107. wire [7:0] SRTC_SNES_DATA_OUT;
  108. wire [7:0] DSPX_SNES_DATA_IN;
  109. wire [7:0] DSPX_SNES_DATA_OUT;
  110. wire [23:0] dspx_pgm_data;
  111. wire [10:0] dspx_pgm_addr;
  112. wire dspx_pgm_we;
  113. wire [15:0] dspx_dat_data;
  114. wire [10:0] dspx_dat_addr;
  115. wire dspx_dat_we;
  116. wire [7:0] featurebits;
  117. wire [23:0] MAPPED_SNES_ADDR;
  118. wire ROM_ADDR0;
  119. wire [22:0] MAPPED_SNES_ADDR2 = MAPPED_SNES_ADDR[23:1];
  120. //wire SD_DMA_EN; //SPI_DMA_CTRL;
  121. sd_dma snes_sd_dma(
  122. .CLK(CLK2),
  123. .SD_DAT(SD_DAT),
  124. .SD_CLK(SD_CLK),
  125. .SD_DMA_EN(SD_DMA_EN),
  126. .SD_DMA_STATUS(SD_DMA_STATUS),
  127. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  128. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  129. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  130. .SD_DMA_TGT(SD_DMA_TGT),
  131. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  132. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  133. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
  134. );
  135. dac snes_dac(
  136. .clkin(CLK2),
  137. .sysclk(SNES_SYSCLK),
  138. .mclk(DAC_MCLK),
  139. .lrck(DAC_LRCK),
  140. .sdout(DAC_SDOUT),
  141. .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
  142. .pgm_address(dac_addr),
  143. .pgm_data(SD_DMA_SRAM_DATA),
  144. .DAC_STATUS(DAC_STATUS),
  145. .volume(msu_volumerq_out),
  146. .vol_latch(msu_volume_latch_out),
  147. .play(dac_play),
  148. .reset(dac_reset)
  149. );
  150. srtc snes_srtc (
  151. .clkin(CLK2),
  152. /*XXX*/.reg_addr(srtc_reg_addr),
  153. .addr_in(SNES_ADDR[0]),
  154. .data_in(SRTC_SNES_DATA_IN),
  155. .data_out(SRTC_SNES_DATA_OUT),
  156. .rtc_data_in(rtc_data),
  157. .reg_we(SNES_WRITE),
  158. .reg_oe(SNES_READ),
  159. .enable(srtc_enable),
  160. .rtc_data_out(srtc_rtc_data_out),
  161. .rtc_we(srtc_rtc_we),
  162. .reset(srtc_reset)
  163. );
  164. rtc snes_rtc (
  165. .clkin(CLKIN),
  166. .rtc_data(rtc_data),
  167. .rtc_data_in(rtc_data_in),
  168. .pgm_we(rtc_pgm_we),
  169. .rtc_data_in1(srtc_rtc_data_out),
  170. .we1(srtc_rtc_we)
  171. );
  172. msu snes_msu (
  173. .clkin(CLK2),
  174. .enable(msu_enable),
  175. .pgm_address(msu_write_addr),
  176. .pgm_data(SD_DMA_SRAM_DATA),
  177. .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
  178. .reg_addr(SNES_ADDR),
  179. .reg_data_in(MSU_SNES_DATA_IN),
  180. .reg_data_out(MSU_SNES_DATA_OUT),
  181. .reg_oe(SNES_READ),
  182. .reg_we(SNES_WRITE),
  183. .status_out(msu_status_out),
  184. .volume_out(msu_volumerq_out),
  185. .volume_latch_out(msu_volume_latch_out),
  186. .addr_out(msu_addressrq_out),
  187. .track_out(msu_trackrq_out),
  188. .status_reset_bits(msu_status_reset_bits),
  189. .status_set_bits(msu_status_set_bits),
  190. .status_reset_we(msu_status_reset_we),
  191. .msu_address_ext(msu_ptr_addr),
  192. .msu_address_ext_write(msu_addr_reset)
  193. );
  194. bsx snes_bsx(
  195. .clkin(CLK2),
  196. .use_bsx(use_bsx),
  197. .pgm_we(bsx_regs_reset_we),
  198. .snes_addr(SNES_ADDR),
  199. .reg_data_in(BSX_SNES_DATA_IN),
  200. .reg_data_out(BSX_SNES_DATA_OUT),
  201. .reg_oe(SNES_READ),
  202. .reg_we(SNES_WRITE),
  203. .regs_out(bsx_regs),
  204. .reg_reset_bits(bsx_regs_reset_bits),
  205. .reg_set_bits(bsx_regs_set_bits),
  206. .data_ovr(bsx_data_ovr),
  207. .flash_writable(IS_FLASHWR),
  208. .rtc_data(rtc_data)
  209. );
  210. spi snes_spi(
  211. .clk(CLK2),
  212. .MOSI(SPI_MOSI),
  213. .MISO(SPI_MISO),
  214. .SSEL(SPI_SS),
  215. .SCK(SPI_SCK),
  216. .cmd_ready(spi_cmd_ready),
  217. .param_ready(spi_param_ready),
  218. .cmd_data(spi_cmd_data),
  219. .param_data(spi_param_data),
  220. .endmessage(spi_endmessage),
  221. .startmessage(spi_startmessage),
  222. .input_data(spi_input_data),
  223. .byte_cnt(spi_byte_cnt),
  224. .bit_cnt(spi_bit_cnt)
  225. );
  226. upd77c25 snes_dspx (
  227. .DI(DSPX_SNES_DATA_IN),
  228. .DO(DSPX_SNES_DATA_OUT),
  229. .A0(DSPX_A0),
  230. .nCS(~dspx_enable),
  231. .nRD(SNES_READ),
  232. .nWR(SNES_WRITE),
  233. .RST(~dspx_reset),
  234. .CLK(CLK2),
  235. .PGM_WR(dspx_pgm_we),
  236. .PGM_DI(dspx_pgm_data),
  237. .PGM_WR_ADDR(dspx_pgm_addr),
  238. .DAT_WR(dspx_dat_we),
  239. .DAT_DI(dspx_dat_data),
  240. .DAT_WR_ADDR(dspx_dat_addr),
  241. .DP_nCS(~dspx_dp_enable),
  242. .DP_ADDR(SNES_ADDR[10:0])
  243. );
  244. reg [7:0] MCU_DINr;
  245. wire [7:0] MCU_DOUT;
  246. mcu_cmd snes_mcu_cmd(
  247. .clk(CLK2),
  248. .snes_sysclk(SNES_SYSCLK),
  249. .cmd_ready(spi_cmd_ready),
  250. .param_ready(spi_param_ready),
  251. .cmd_data(spi_cmd_data),
  252. .param_data(spi_param_data),
  253. .mcu_mapper(MAPPER),
  254. .mcu_sram_size(SRAM_SIZE),
  255. // .mcu_read(MCU_READ),
  256. .mcu_write(MCU_WRITE),
  257. .mcu_data_in(MCU_DINr),
  258. .mcu_data_out(MCU_DOUT),
  259. .spi_byte_cnt(spi_byte_cnt),
  260. .spi_bit_cnt(spi_bit_cnt),
  261. .spi_data_out(spi_input_data),
  262. .addr_out(MCU_ADDR),
  263. .endmessage(spi_endmessage),
  264. .startmessage(spi_startmessage),
  265. .saveram_mask_out(SAVERAM_MASK),
  266. .rom_mask_out(ROM_MASK),
  267. .SD_DMA_EN(SD_DMA_EN),
  268. .SD_DMA_STATUS(SD_DMA_STATUS),
  269. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  270. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  271. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  272. .SD_DMA_TGT(SD_DMA_TGT),
  273. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  274. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  275. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  276. .dac_addr_out(dac_addr),
  277. .DAC_STATUS(DAC_STATUS),
  278. // .dac_volume_out(dac_volume),
  279. // .dac_volume_latch_out(dac_vol_latch),
  280. .dac_play_out(dac_play),
  281. .dac_reset_out(dac_reset),
  282. .msu_addr_out(msu_write_addr),
  283. .MSU_STATUS(msu_status_out),
  284. .msu_status_reset_out(msu_status_reset_bits),
  285. .msu_status_set_out(msu_status_set_bits),
  286. .msu_status_reset_we(msu_status_reset_we),
  287. .msu_volumerq(msu_volumerq_out),
  288. .msu_addressrq(msu_addressrq_out),
  289. .msu_trackrq(msu_trackrq_out),
  290. .msu_ptr_out(msu_ptr_addr),
  291. .msu_reset_out(msu_addr_reset),
  292. .bsx_regs_set_out(bsx_regs_set_bits),
  293. .bsx_regs_reset_out(bsx_regs_reset_bits),
  294. .bsx_regs_reset_we(bsx_regs_reset_we),
  295. .rtc_data_out(rtc_data_in),
  296. .rtc_pgm_we(rtc_pgm_we),
  297. .srtc_reset(srtc_reset),
  298. .dspx_pgm_data_out(dspx_pgm_data),
  299. .dspx_pgm_addr_out(dspx_pgm_addr),
  300. .dspx_pgm_we_out(dspx_pgm_we),
  301. .dspx_dat_data_out(dspx_dat_data),
  302. .dspx_dat_addr_out(dspx_dat_addr),
  303. .dspx_dat_we_out(dspx_dat_we),
  304. .dspx_reset_out(dspx_reset),
  305. .featurebits_out(featurebits),
  306. .mcu_rrq(MCU_RRQ),
  307. .mcu_wrq(MCU_WRQ),
  308. .mcu_rq_rdy(MCU_RDY)
  309. );
  310. // dcm1: dfs 4x
  311. my_dcm snes_dcm(
  312. .CLKIN(CLKIN),
  313. .CLKFX(CLK2),
  314. .LOCKED(DCM_LOCKED),
  315. .RST(DCM_RST),
  316. .STATUS(DCM_STATUS)
  317. );
  318. assign DCM_RST=0;
  319. reg [5:0] SNES_READr;
  320. reg [5:0] SNES_WRITEr;
  321. reg [12:0] SNES_CPU_CLKr;
  322. reg [5:0] SNES_RWr;
  323. reg [23:0] SNES_ADDRr;
  324. wire SNES_RW = (SNES_READ & SNES_WRITE);
  325. wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
  326. wire SNES_RD_start = (SNES_READr == 6'b111110);
  327. wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
  328. wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
  329. wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
  330. always @(posedge CLK2) begin
  331. SNES_READr <= {SNES_READr[4:0], SNES_READ};
  332. SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
  333. SNES_CPU_CLKr <= {SNES_CPU_CLKr[11:0], SNES_CPU_CLK};
  334. SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
  335. end
  336. wire ROM_SEL;
  337. address snes_addr(
  338. .CLK(CLK2),
  339. .MAPPER(MAPPER),
  340. .featurebits(featurebits),
  341. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  342. .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
  343. .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
  344. .ROM_SEL(ROM_SEL), // which SRAM unit to access
  345. .MCU_OVR(MCU_OVR), // enable MCU mode (active low)
  346. .IS_SAVERAM(IS_SAVERAM),
  347. .IS_ROM(IS_ROM),
  348. .IS_WRITABLE(IS_WRITABLE),
  349. .MCU_ADDR(MCU_ADDR),
  350. .SAVERAM_MASK(SAVERAM_MASK),
  351. .ROM_MASK(ROM_MASK),
  352. //MSU-1
  353. .use_msu(use_msu),
  354. .msu_enable(msu_enable),
  355. //BS-X
  356. .use_bsx(use_bsx),
  357. .bsx_regs(bsx_regs),
  358. //SRTC
  359. .srtc_enable(srtc_enable),
  360. //uPD77C25
  361. .dspx_enable(dspx_enable),
  362. .dspx_dp_enable(dspx_dp_enable),
  363. .dspx_a0(DSPX_A0)
  364. );
  365. wire SNES_READ_CYCLEw;
  366. wire SNES_WRITE_CYCLEw;
  367. wire MCU_READ_CYCLEw;
  368. wire MCU_WRITE_CYCLEw;
  369. parameter MODE_SNES = 1'b0;
  370. parameter MODE_MCU = 1'b1;
  371. parameter ST_IDLE = 18'b000000000000000001;
  372. parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
  373. parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
  374. parameter ST_SNES_RD_END = 18'b000000000000001000;
  375. parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
  376. parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
  377. parameter ST_SNES_WR_DATA = 18'b000000000001000000;
  378. parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
  379. parameter ST_SNES_WR_END = 18'b000000000100000000;
  380. parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
  381. parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
  382. parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
  383. parameter ST_MCU_RD_END = 18'b000001000000000000;
  384. parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
  385. parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
  386. parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
  387. parameter ST_MCU_WR_END = 18'b010000000000000000;
  388. parameter ROM_RD_WAIT = 4'h4;
  389. parameter ROM_RD_WAIT_MCU = 4'h5;
  390. parameter ROM_WR_WAIT1 = 4'h2;
  391. parameter ROM_WR_WAIT2 = 4'h3;
  392. parameter ROM_WR_WAIT_MCU = 4'h6;
  393. reg [17:0] STATE;
  394. reg [3:0] STATEIDX;
  395. reg [1:0] CYCLE_RESET;
  396. reg ROM_WE_MASK;
  397. reg ROM_OE_MASK;
  398. reg SNES_READ_CYCLE;
  399. reg SNES_WRITE_CYCLE;
  400. reg MCU_READ_CYCLE;
  401. reg MCU_WRITE_CYCLE;
  402. reg MCU_SPI_WRITEONCE;
  403. reg MCU_SPI_READONCE;
  404. reg MCU_SPI_WRITE;
  405. reg MCU_SPI_READ;
  406. reg MCU_SPI_ADDR_INCREMENT;
  407. reg [7:0] MCU_DATA_IN;
  408. reg [3:0] MAPPER_BUF;
  409. reg SNES_DATABUS_OE_BUF;
  410. reg SNES_DATABUS_DIR_BUF;
  411. initial begin
  412. CYCLE_RESET = 2'b0;
  413. STATE = ST_IDLE;
  414. STATEIDX = 13;
  415. ROM_WE_MASK = 1'b1;
  416. ROM_OE_MASK = 1'b1;
  417. SNES_READ_CYCLE = 1'b1;
  418. SNES_WRITE_CYCLE = 1'b1;
  419. MCU_READ_CYCLE = 1'b1;
  420. MCU_WRITE_CYCLE = 1'b1;
  421. end
  422. // falling edge of SNES /RD or /WR marks the beginning of a new cycle
  423. // SNES READ or WRITE always starts @posedge CLK !!
  424. // CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy
  425. // the minimum of 6 SNES cycles to get everything done.
  426. // we have 24 internal cycles to work with. (CLKIN * 4)
  427. assign DSPX_SNES_DATA_IN = SNES_DATA;
  428. assign SRTC_SNES_DATA_IN = SNES_DATA;
  429. assign MSU_SNES_DATA_IN = SNES_DATA;
  430. assign BSX_SNES_DATA_IN = SNES_DATA;
  431. reg [7:0] SNES_DINr;
  432. reg [7:0] ROM_DOUTr;
  433. assign SNES_DATA = (!SNES_READ) ? (srtc_enable ? SRTC_SNES_DATA_OUT
  434. :dspx_enable ? DSPX_SNES_DATA_OUT
  435. :dspx_dp_enable ? DSPX_SNES_DATA_OUT
  436. :msu_enable ? MSU_SNES_DATA_OUT
  437. :bsx_data_ovr ? BSX_SNES_DATA_OUT
  438. :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
  439. reg [3:0] ST_MEM_DELAYr;
  440. reg MCU_RD_PENDr;
  441. reg MCU_WR_PENDr;
  442. reg [23:0] ROM_ADDRr;
  443. reg NEED_SNES_ADDRr;
  444. always @(posedge CLK2) begin
  445. if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
  446. else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
  447. end
  448. wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
  449. assign ROM_ADDR = (!MCU_OVR) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
  450. assign ROM_ADDR0 = (!MCU_OVR) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
  451. reg ROM_WEr;
  452. initial ROM_WEr = 1'b1;
  453. reg RQ_MCU_RDYr;
  454. initial RQ_MCU_RDYr = 1'b1;
  455. assign MCU_RDY = RQ_MCU_RDYr;
  456. always @(posedge CLK2) begin
  457. if(MCU_RRQ) begin
  458. MCU_RD_PENDr <= 1'b1;
  459. RQ_MCU_RDYr <= 1'b0;
  460. end else if(MCU_WRQ) begin
  461. MCU_WR_PENDr <= 1'b1;
  462. RQ_MCU_RDYr <= 1'b0;
  463. end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
  464. MCU_RD_PENDr <= 1'b0;
  465. MCU_WR_PENDr <= 1'b0;
  466. RQ_MCU_RDYr <= 1'b1;
  467. end
  468. end
  469. reg [23:0] SNES_ADDRsr[1:0];
  470. always @(posedge CLK2) begin
  471. SNES_ADDRsr[0] <= SNES_ADDR;
  472. SNES_ADDRsr[1] <= SNES_ADDRsr[0];
  473. end
  474. wire SNES_ADDRchg = (SNES_ADDRsr[0] != SNES_ADDRsr[1]);
  475. reg snes_wr_cycle;
  476. always @(posedge CLK2) begin
  477. if(SNES_cycle_start) begin
  478. STATE <= ST_SNES_RD_ADDR;
  479. end else if(SNES_WR_start) begin
  480. STATE <= ST_SNES_WR_ADDR;
  481. end else begin
  482. case(STATE)
  483. ST_IDLE: begin
  484. ROM_ADDRr <= MAPPED_SNES_ADDR;
  485. if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
  486. else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
  487. else STATE <= ST_IDLE;
  488. end
  489. ST_SNES_RD_ADDR: begin
  490. STATE <= ST_SNES_RD_WAIT;
  491. ST_MEM_DELAYr <= ROM_RD_WAIT;
  492. end
  493. ST_SNES_RD_WAIT: begin
  494. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  495. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
  496. else STATE <= ST_SNES_RD_WAIT;
  497. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
  498. else SNES_DINr <= ROM_DATA[15:8];
  499. end
  500. ST_SNES_RD_END: begin
  501. STATE <= ST_IDLE;
  502. if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
  503. else SNES_DINr <= ROM_DATA[15:8];
  504. end
  505. ST_SNES_WR_ADDR: begin
  506. ROM_WEr <= (!IS_FLASHWR & !IS_WRITABLE);
  507. snes_wr_cycle <= 1'b1;
  508. STATE <= ST_SNES_WR_WAIT1;
  509. ST_MEM_DELAYr <= ROM_WR_WAIT1;
  510. end
  511. ST_SNES_WR_WAIT1: begin
  512. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  513. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
  514. else STATE <= ST_SNES_WR_WAIT1;
  515. end
  516. ST_SNES_WR_DATA: begin
  517. ROM_DOUTr <= SNES_DATA;
  518. ST_MEM_DELAYr <= ROM_WR_WAIT2;
  519. STATE <= ST_SNES_WR_WAIT2;
  520. end
  521. ST_SNES_WR_WAIT2: begin
  522. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  523. if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
  524. else STATE <= ST_SNES_WR_WAIT2;
  525. end
  526. ST_SNES_WR_END: begin
  527. STATE <= ST_IDLE;
  528. ROM_WEr <= 1'b1;
  529. snes_wr_cycle <= 1'b0;
  530. end
  531. ST_MCU_RD_ADDR: begin
  532. ROM_ADDRr <= MCU_ADDR;
  533. STATE <= ST_MCU_RD_WAIT;
  534. ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
  535. end
  536. ST_MCU_RD_WAIT: begin
  537. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  538. if(ST_MEM_DELAYr == 4'h0) begin
  539. STATE <= ST_MCU_RD_WAIT2;
  540. ST_MEM_DELAYr <= 4'h2;
  541. end
  542. else STATE <= ST_MCU_RD_WAIT;
  543. if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
  544. else MCU_DINr <= ROM_DATA[15:8];
  545. end
  546. ST_MCU_RD_WAIT2: begin
  547. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  548. if(ST_MEM_DELAYr == 4'h0) begin
  549. STATE <= ST_MCU_RD_END;
  550. end else STATE <= ST_MCU_RD_WAIT2;
  551. end
  552. ST_MCU_RD_END: begin
  553. STATE <= ST_IDLE;
  554. end
  555. ST_MCU_WR_ADDR: begin
  556. ROM_ADDRr <= MCU_ADDR;
  557. STATE <= ST_MCU_WR_WAIT;
  558. ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
  559. ROM_DOUTr <= MCU_DOUT;
  560. ROM_WEr <= 1'b0;
  561. end
  562. ST_MCU_WR_WAIT: begin
  563. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  564. if(ST_MEM_DELAYr == 4'h0) begin
  565. ROM_WEr <= 1'b1;
  566. STATE <= ST_MCU_WR_WAIT2;
  567. ST_MEM_DELAYr <= 4'h2;
  568. end
  569. else STATE <= ST_MCU_WR_WAIT;
  570. end
  571. ST_MCU_WR_WAIT2: begin
  572. ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
  573. if(ST_MEM_DELAYr == 4'h0) begin
  574. STATE <= ST_MCU_WR_END;
  575. end else STATE <= ST_MCU_WR_WAIT2;
  576. end
  577. ST_MCU_WR_END: begin
  578. STATE <= ST_IDLE;
  579. end
  580. endcase
  581. end
  582. end
  583. // wire MCU_RRQ;
  584. // wire MCU_WRQ;
  585. // reg ROM_OEr;
  586. assign ROM_DATA[7:0] = ROM_ADDR0
  587. ?(!MCU_OVR ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
  588. : (!ROM_WE ? ROM_DOUTr : 8'bZ)
  589. )
  590. :8'bZ;
  591. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  592. :(!MCU_OVR ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
  593. : (!ROM_WE ? ROM_DOUTr : 8'bZ)
  594. );
  595. // When in MCU mode, enable SRAM_WE according to MCU programming
  596. // else enable SRAM_WE according to state&cycle
  597. assign ROM_WE = !MCU_OVR
  598. ?MCU_WRITE
  599. :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle); /* & !MODE)
  600. | ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX])*/
  601. // When in MCU mode, enable SRAM_OE whenever not writing
  602. // else enable SRAM_OE according to state&cycle
  603. assign ROM_OE = 1'b0; //!MCU_OVR
  604. //?MCU_READ
  605. //:ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX];
  606. assign ROM_CE = 1'b0; // !MCU_OVR ? (MCU_READ & MCU_WRITE) : ROM_SEL;
  607. assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
  608. assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
  609. //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
  610. assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
  611. msu_enable ? 1'b0 :
  612. bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
  613. srtc_enable ? (SNES_READ & SNES_WRITE) :
  614. ((IS_ROM & SNES_CS)
  615. |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
  616. |(SNES_READ & SNES_WRITE)
  617. );
  618. assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
  619. assign IRQ_DIR = 1'b0;
  620. assign SNES_IRQ = 1'bZ;
  621. assign p113_out = ROM_WE;
  622. endmodule