data.v 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107
  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 23:03:06 05/13/2009
  7. // Design Name:
  8. // Module Name: data
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module data(
  22. input CLK,
  23. input SNES_READ,
  24. input SNES_WRITE,
  25. input ROM_WE,
  26. input MCU_READ,
  27. input MCU_WRITE,
  28. inout [7:0] SNES_DATA,
  29. inout [15:0] ROM_DATA,
  30. input [7:0] MCU_IN_DATA,
  31. output [7:0] MCU_OUT_DATA,
  32. input MODE,
  33. input SNES_DATA_TO_MEM,
  34. input MCU_DATA_TO_MEM,
  35. input ROM_DATA_TO_SNES_MEM,
  36. input ROM_DATA_TO_MCU_MEM,
  37. input MCU_OVR,
  38. input ROM_ADDR0,
  39. output [7:0] MSU_DATA_IN,
  40. input [7:0] MSU_DATA_OUT,
  41. output [7:0] BSX_DATA_IN,
  42. input [7:0] BSX_DATA_OUT,
  43. output [7:0] SRTC_DATA_IN,
  44. input [7:0] SRTC_DATA_OUT,
  45. output [7:0] DSPX_DATA_IN,
  46. input [7:0] DSPX_DATA_OUT,
  47. input msu_enable,
  48. input bsx_data_ovr,
  49. input srtc_enable,
  50. input dspx_enable,
  51. input dspx_dp_enable
  52. );
  53. reg [7:0] SNES_IN_MEM;
  54. reg [7:0] SNES_OUT_MEM;
  55. reg [7:0] MCU_IN_MEM;
  56. reg [7:0] MCU_OUT_MEM;
  57. wire [7:0] FROM_ROM_BYTE;
  58. assign MSU_DATA_IN = SNES_DATA;
  59. assign BSX_DATA_IN = SNES_DATA;
  60. assign SRTC_DATA_IN = SNES_DATA;
  61. assign DSPX_DATA_IN = SNES_DATA;
  62. assign SNES_DATA = SNES_READ ? 8'bZ
  63. :(!MCU_OVR ? 8'h00
  64. :(msu_enable ? MSU_DATA_OUT
  65. : bsx_data_ovr ? BSX_DATA_OUT
  66. : srtc_enable ? SRTC_DATA_OUT
  67. : dspx_enable ? DSPX_DATA_OUT
  68. : dspx_dp_enable ? DSPX_DATA_OUT
  69. : SNES_OUT_MEM)
  70. );
  71. assign FROM_ROM_BYTE = (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
  72. assign MCU_OUT_DATA = !MCU_OVR ? (FROM_ROM_BYTE)
  73. :(MCU_OUT_MEM);
  74. assign ROM_DATA[7:0] = ROM_ADDR0
  75. ?(!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
  76. : (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
  77. : (!ROM_WE ? SNES_IN_MEM : 8'bZ)
  78. )
  79. )
  80. :8'bZ;
  81. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  82. :(!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
  83. : (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
  84. : (!ROM_WE ? SNES_IN_MEM : 8'bZ)
  85. )
  86. );
  87. always @(posedge CLK) begin
  88. if(SNES_DATA_TO_MEM)
  89. SNES_IN_MEM <= SNES_DATA;
  90. if(MCU_DATA_TO_MEM)
  91. MCU_IN_MEM <= MCU_IN_DATA;
  92. if(ROM_DATA_TO_SNES_MEM)
  93. SNES_OUT_MEM <= FROM_ROM_BYTE;
  94. if(ROM_DATA_TO_MCU_MEM)
  95. MCU_OUT_MEM <= FROM_ROM_BYTE;
  96. end
  97. endmodule