address.v 9.3 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: address
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Address logic w/ SaveRAM masking
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Additional Comments:
  18. //
  19. //////////////////////////////////////////////////////////////////////////////////
  20. module address(
  21. input CLK,
  22. input [7:0] featurebits, // peripheral enable/disable
  23. input [2:0] MAPPER, // MCU detected mapper
  24. input [23:0] SNES_ADDR, // requested address from SNES
  25. input SNES_CS, // "CART" pin from SNES (active low)
  26. output [23:0] ROM_ADDR, // Address to request from SRAM0
  27. output ROM_SEL, // enable SRAM0 (active low)
  28. input MCU_OVR, // enable MCU master mode (active low)
  29. output IS_SAVERAM, // address/CS mapped as SRAM?
  30. output IS_ROM, // address mapped as ROM?
  31. output IS_WRITABLE, // address somehow mapped as writable area?
  32. input [23:0] MCU_ADDR, // allow address to be set externally
  33. input ADDR_WRITE,
  34. input [23:0] SAVERAM_MASK,
  35. input [23:0] ROM_MASK,
  36. input use_msu,
  37. output msu_enable,
  38. output srtc_enable,
  39. output use_bsx,
  40. input [14:0] bsx_regs,
  41. output dspx_enable,
  42. output dspx_dp_enable,
  43. output dspx_a0
  44. );
  45. parameter [2:0]
  46. FEAT_DSPX = 0,
  47. FEAT_ST0010 = 1,
  48. FEAT_SRTC = 2,
  49. FEAT_MSU1 = 3
  50. ;
  51. wire [1:0] SRAM_BANK;
  52. wire [23:0] SRAM_SNES_ADDR;
  53. /* currently supported mappers:
  54. Index Mapper
  55. 000 HiROM
  56. 001 LoROM
  57. 010 ExHiROM (48-64Mbit)
  58. 011 BS-X
  59. 110 brainfuck interleaved 96MBit Star Ocean =)
  60. 111 menu (ROM in upper SRAM)
  61. */
  62. /* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
  63. Offset 6000-7fff */
  64. assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
  65. |(SNES_ADDR[22]));
  66. assign IS_SAVERAM = SAVERAM_MASK[0]
  67. &(featurebits[FEAT_ST0010]
  68. ?((SNES_ADDR[22:19] == 4'b1101)
  69. & &(~SNES_ADDR[15:12])
  70. & SNES_ADDR[11])
  71. :((MAPPER == 3'b000
  72. || MAPPER == 3'b010
  73. || MAPPER == 3'b110
  74. || MAPPER == 3'b111)
  75. ? (!SNES_ADDR[22]
  76. & &SNES_ADDR[21:20]
  77. & &SNES_ADDR[14:13]
  78. & !SNES_ADDR[15]
  79. )
  80. /* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd Offset 0000-7fff
  81. TODO: 0000-ffff for small ROMs? */
  82. :(MAPPER == 3'b001)
  83. ? (&SNES_ADDR[22:20]
  84. & (SNES_ADDR[19:16] < 4'b1110)
  85. & !SNES_ADDR[15]
  86. )
  87. /* BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
  88. :(MAPPER == 3'b011)
  89. ? ((SNES_ADDR[23:19] == 5'b00010)
  90. & (SNES_ADDR[15:12] == 4'b0101)
  91. )
  92. : 1'b0));
  93. /* BS-X has 4 MBits of extra RAM that can be mapped to various places */
  94. assign IS_WRITABLE = IS_SAVERAM
  95. |((MAPPER == 3'b011)
  96. ?((bsx_regs[3] && SNES_ADDR[23:20]==4'b0110)
  97. |(!bsx_regs[5] && SNES_ADDR[23:20]==4'b0100)
  98. |(!bsx_regs[6] && SNES_ADDR[23:20]==4'b0101)
  99. |(SNES_ADDR[23:19] == 5'b01110)
  100. |(SNES_ADDR[23:21] == 3'b001
  101. && SNES_ADDR[15:13] == 3'b011)
  102. )
  103. : 1'b0);
  104. /* BSX regs:
  105. Index Function
  106. 1 0=map flash to ROM area; 1=map PRAM to ROM area
  107. 2 1=HiROM; 0=LoROM
  108. 3 1=Mirror PRAM @60-6f:0000-ffff
  109. 5 1=DO NOT mirror PRAM @40-4f:0000-ffff
  110. 6 1=DO NOT mirror PRAM @50-5f:0000-ffff
  111. 7 1=map BSX cartridge ROM @00-1f:8000-ffff
  112. 8 1=map BSX cartridge ROM @80-9f:8000-ffff
  113. */
  114. assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
  115. ?(IS_SAVERAM
  116. ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
  117. & SAVERAM_MASK)
  118. : ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
  119. :(MAPPER == 3'b001)
  120. ?(IS_SAVERAM
  121. ? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
  122. : ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
  123. & ROM_MASK))
  124. :(MAPPER == 3'b010)
  125. ?(IS_SAVERAM
  126. ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
  127. & SAVERAM_MASK)
  128. : ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
  129. & ROM_MASK))
  130. :(MAPPER == 3'b011)
  131. ?(IS_SAVERAM
  132. ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
  133. : IS_WRITABLE
  134. ? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
  135. : ((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
  136. |(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
  137. ?(24'h800000
  138. + ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
  139. & 24'h0FFFFF)
  140. )
  141. :((bsx_regs[1]
  142. ? 24'h400000
  143. : 24'h000000
  144. )
  145. + bsx_regs[2]
  146. ?({2'b00, SNES_ADDR[21:0]}
  147. & (ROM_MASK /* >> bsx_regs[1] */)
  148. )
  149. :({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
  150. & (ROM_MASK /* >> bsx_regs[1] */)
  151. )
  152. )
  153. )
  154. :(MAPPER == 3'b110)
  155. ?(IS_SAVERAM
  156. ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
  157. & SAVERAM_MASK)
  158. :(SNES_ADDR[15]
  159. ?({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
  160. :({2'b10,
  161. SNES_ADDR[23],
  162. SNES_ADDR[21:16],
  163. SNES_ADDR[14:0]}
  164. )
  165. )
  166. )
  167. :(MAPPER == 3'b111)
  168. ?(IS_SAVERAM
  169. ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
  170. & SAVERAM_MASK)
  171. : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
  172. + 24'hE00000)
  173. )
  174. : 24'b0);
  175. assign ROM_ADDR = SRAM_SNES_ADDR;
  176. assign ROM_SEL = 1'b0; // (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK];
  177. assign msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
  178. reg [7:0] msu_enable_r;
  179. initial msu_enable_r = 8'b00000000;
  180. always @(posedge CLK) msu_enable_r <= {msu_enable_r[6:0], msu_enable_w};
  181. assign msu_enable = &msu_enable_r[5:2];
  182. assign use_bsx = (MAPPER == 3'b011);
  183. assign srtc_enable = featurebits[FEAT_SRTC] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
  184. // DSP1 LoROM: DR=30-3f:8000-bfff; SR=30-3f:c000-ffff
  185. // or DR=60-6f:0000-3fff; SR=60-6f:4000-7fff
  186. // DSP1 HiROM: DR=00-0f:6000-6fff; SR=00-0f:7000-7fff
  187. wire dspx_enable_w =
  188. featurebits[FEAT_DSPX]
  189. ?((MAPPER == 3'b001)
  190. ?(ROM_MASK[20]
  191. ?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
  192. :(~SNES_ADDR[22] & SNES_ADDR[21] & SNES_ADDR[20] & SNES_ADDR[15])
  193. )
  194. :(MAPPER == 3'b000)
  195. ?(~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15]
  196. & &SNES_ADDR[14:13])
  197. :1'b0)
  198. :featurebits[FEAT_ST0010]
  199. ?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & &(~SNES_ADDR[19:16]) & ~SNES_ADDR[15])
  200. :1'b0;
  201. wire dspx_dp_enable_w = featurebits[FEAT_ST0010]
  202. &(SNES_ADDR[22:19] == 4'b1101
  203. && SNES_ADDR[15:11] == 5'b00000);
  204. assign dspx_a0 = featurebits[FEAT_DSPX]
  205. ?((MAPPER == 3'b001) ? SNES_ADDR[14]
  206. :(MAPPER == 3'b000) ? SNES_ADDR[12]
  207. :1'b1)
  208. :featurebits[FEAT_ST0010]
  209. ?SNES_ADDR[0]
  210. :1'b1;
  211. //reg [7:0] dspx_dp_enable_r;
  212. //initial dspx_dp_enable_r = 8'b00000000;
  213. //always @(posedge CLK) dspx_dp_enable_r <= {dspx_dp_enable_r[6:0], dspx_dp_enable_w};
  214. //assign dspx_dp_enable = &dspx_dp_enable_r[5:2];
  215. assign dspx_dp_enable = dspx_dp_enable_w;
  216. reg [7:0] dspx_enable_r;
  217. initial dspx_enable_r = 8'b00000000;
  218. always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[6:0], dspx_enable_w};
  219. assign dspx_enable = &dspx_enable_r[5:2];
  220. endmodule