upd77c25_datrom.xco 2.9 KB

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  1. ##############################################################
  2. #
  3. # Xilinx Core Generator version 13.1
  4. # Date: Wed Jun 22 21:30:01 2011
  5. #
  6. ##############################################################
  7. #
  8. # This file contains the customisation parameters for a
  9. # Xilinx CORE Generator IP GUI. It is strongly recommended
  10. # that you do not manually alter this file as it may cause
  11. # unexpected and unsupported behavior.
  12. #
  13. ##############################################################
  14. #
  15. # BEGIN Project Options
  16. SET addpads = false
  17. SET asysymbol = true
  18. SET busformat = BusFormatAngleBracketNotRipped
  19. SET createndf = false
  20. SET designentry = Advanced
  21. SET device = xc3s400
  22. SET devicefamily = spartan3
  23. SET flowvendor = Other
  24. SET formalverification = false
  25. SET foundationsym = false
  26. SET implementationfiletype = Ngc
  27. SET package = pq208
  28. SET removerpms = false
  29. SET simulationfiles = Behavioral
  30. SET speedgrade = -4
  31. SET verilogsim = true
  32. SET vhdlsim = true
  33. # END Project Options
  34. # BEGIN Select
  35. SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
  36. # END Select
  37. # BEGIN Parameters
  38. CSET additional_inputs_for_power_estimation=false
  39. CSET algorithm=Minimum_Area
  40. CSET assume_synchronous_clk=true
  41. CSET axi_id_width=4
  42. CSET axi_slave_type=Memory_Slave
  43. CSET axi_type=AXI4_Full
  44. CSET byte_size=9
  45. CSET coe_file=no_coe_file_loaded
  46. CSET collision_warnings=ALL
  47. CSET component_name=upd77c25_datrom
  48. CSET disable_collision_warnings=false
  49. CSET disable_out_of_range_warnings=false
  50. CSET ecc=false
  51. CSET ecctype=No_ECC
  52. CSET enable_a=Always_Enabled
  53. CSET enable_b=Always_Enabled
  54. CSET error_injection_type=Single_Bit_Error_Injection
  55. CSET fill_remaining_memory_locations=false
  56. CSET interface_type=Native
  57. CSET load_init_file=false
  58. CSET memory_type=Simple_Dual_Port_RAM
  59. CSET operating_mode_a=WRITE_FIRST
  60. CSET operating_mode_b=WRITE_FIRST
  61. CSET output_reset_value_a=0
  62. CSET output_reset_value_b=0
  63. CSET pipeline_stages=0
  64. CSET port_a_clock=100
  65. CSET port_a_enable_rate=100
  66. CSET port_a_write_rate=50
  67. CSET port_b_clock=100
  68. CSET port_b_enable_rate=100
  69. CSET port_b_write_rate=0
  70. CSET primitive=8kx2
  71. CSET read_width_a=16
  72. CSET read_width_b=16
  73. CSET register_porta_input_of_softecc=false
  74. CSET register_porta_output_of_memory_core=false
  75. CSET register_porta_output_of_memory_primitives=false
  76. CSET register_portb_output_of_memory_core=false
  77. CSET register_portb_output_of_memory_primitives=false
  78. CSET register_portb_output_of_softecc=false
  79. CSET remaining_memory_locations=0
  80. CSET reset_memory_latch_a=false
  81. CSET reset_memory_latch_b=false
  82. CSET reset_priority_a=CE
  83. CSET reset_priority_b=CE
  84. CSET reset_type=SYNC
  85. CSET softecc=false
  86. CSET use_axi_id=false
  87. CSET use_byte_write_enable=false
  88. CSET use_error_injection_pins=false
  89. CSET use_regcea_pin=false
  90. CSET use_regceb_pin=false
  91. CSET use_rsta_pin=false
  92. CSET use_rstb_pin=false
  93. CSET write_depth_a=1536
  94. CSET write_width_a=16
  95. CSET write_width_b=16
  96. # END Parameters
  97. # BEGIN Extra information
  98. MISC pkg_timestamp=2011-02-03T22:20:43.000Z
  99. # END Extra information
  100. GENERATE
  101. # CRC: 7b2b203b