address.v 9.3 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: address
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Address logic w/ SaveRAM masking
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Additional Comments:
  18. //
  19. //////////////////////////////////////////////////////////////////////////////////
  20. module address(
  21. input CLK,
  22. input [7:0] featurebits, // peripheral enable/disable
  23. input [2:0] MAPPER, // MCU detected mapper
  24. input [23:0] SNES_ADDR, // requested address from SNES
  25. input SNES_CS, // "CART" pin from SNES (active low)
  26. output [22:0] ROM_ADDR, // Address to request from SRAM0
  27. output ROM_SEL, // enable SRAM0 (active low)
  28. input MCU_OVR, // enable MCU master mode (active low)
  29. input MODE, // MCU(1) or SNES(0) ("bus phase")
  30. output IS_SAVERAM, // address/CS mapped as SRAM?
  31. output IS_ROM, // address mapped as ROM?
  32. output IS_WRITABLE, // address somehow mapped as writable area?
  33. input [23:0] MCU_ADDR, // allow address to be set externally
  34. input ADDR_WRITE,
  35. output ROM_ADDR0,
  36. input [23:0] SAVERAM_MASK,
  37. input [23:0] ROM_MASK,
  38. input use_msu,
  39. output msu_enable,
  40. output srtc_enable,
  41. output use_bsx,
  42. input [14:0] bsx_regs,
  43. output dspx_enable,
  44. output dspx_dp_enable,
  45. output dspx_a0
  46. );
  47. parameter [2:0]
  48. FEAT_DSPX = 0,
  49. FEAT_ST0010 = 1,
  50. FEAT_SRTC = 2,
  51. FEAT_MSU1 = 3
  52. ;
  53. wire [1:0] SRAM_BANK;
  54. wire [23:0] SRAM_ADDR_FULL;
  55. /* currently supported mappers:
  56. Index Mapper
  57. 000 HiROM
  58. 001 LoROM
  59. 010 ExHiROM (48-64Mbit)
  60. 011 BS-X
  61. 110 brainfuck interleaved 96MBit Star Ocean =)
  62. 111 menu (ROM in upper SRAM)
  63. */
  64. /* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
  65. Offset 6000-7fff */
  66. assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
  67. |(SNES_ADDR[22]));
  68. assign IS_SAVERAM = SAVERAM_MASK[0]
  69. &(featurebits[FEAT_ST0010]
  70. ?((SNES_ADDR[22:19] == 4'b1101)
  71. & &(~SNES_ADDR[15:12])
  72. & SNES_ADDR[11])
  73. :((MAPPER == 3'b000
  74. || MAPPER == 3'b010
  75. || MAPPER == 3'b110
  76. || MAPPER == 3'b111)
  77. ? (!SNES_ADDR[22]
  78. & &SNES_ADDR[21:20]
  79. & &SNES_ADDR[14:13]
  80. & !SNES_ADDR[15]
  81. )
  82. /* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd Offset 0000-7fff
  83. TODO: 0000-ffff for small ROMs? */
  84. :(MAPPER == 3'b001)
  85. ? (&SNES_ADDR[22:20]
  86. & (SNES_ADDR[19:16] < 4'b1110)
  87. & !SNES_ADDR[15]
  88. )
  89. /* BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
  90. :(MAPPER == 3'b011)
  91. ? ((SNES_ADDR[23:19] == 5'b00010)
  92. & (SNES_ADDR[15:12] == 4'b0101)
  93. )
  94. : 1'b0));
  95. assign IS_WRITABLE = IS_SAVERAM
  96. |((MAPPER == 3'b011)
  97. ?((bsx_regs[3] && SNES_ADDR[23:20]==4'b0110)
  98. |(!bsx_regs[5] && SNES_ADDR[23:20]==4'b0100)
  99. |(!bsx_regs[6] && SNES_ADDR[23:20]==4'b0101)
  100. |(SNES_ADDR[23:19] == 5'b01110)
  101. |(SNES_ADDR[23:21] == 3'b001
  102. && SNES_ADDR[15:13] == 3'b011)
  103. )
  104. : 1'b0);
  105. /* BSX regs:
  106. Index Function
  107. 1 0=map flash to ROM area; 1=map PRAM to ROM area
  108. 2 1=HiROM; 0=LoROM
  109. 3 1=Mirror PRAM @60-6f:0000-ffff
  110. 5 1=DO NOT mirror PRAM @40-4f:0000-ffff
  111. 6 1=DO NOT mirror PRAM @50-5f:0000-ffff
  112. 7 1=map BSX cartridge ROM @00-1f:8000-ffff
  113. 8 1=map BSX cartridge ROM @80-9f:8000-ffff
  114. */
  115. assign SRAM_ADDR_FULL = (MODE) ? MCU_ADDR
  116. :((MAPPER == 3'b000)
  117. ?(IS_SAVERAM
  118. ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
  119. & SAVERAM_MASK)
  120. : ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
  121. :(MAPPER == 3'b001)
  122. ?(IS_SAVERAM
  123. ? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
  124. : ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
  125. & ROM_MASK))
  126. :(MAPPER == 3'b010)
  127. ?(IS_SAVERAM
  128. ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
  129. & SAVERAM_MASK)
  130. : ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
  131. & ROM_MASK))
  132. :(MAPPER == 3'b011)
  133. ?(IS_SAVERAM
  134. ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
  135. : IS_WRITABLE
  136. ? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
  137. : ((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
  138. |(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
  139. ?(24'h800000
  140. + ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
  141. & 24'h0FFFFF)
  142. )
  143. :((bsx_regs[1]
  144. ? 24'h400000
  145. : 24'h000000
  146. )
  147. + bsx_regs[2]
  148. ?({2'b00, SNES_ADDR[21:0]}
  149. & (ROM_MASK /* >> bsx_regs[1] */)
  150. )
  151. :({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
  152. & (ROM_MASK /* >> bsx_regs[1] */)
  153. )
  154. )
  155. )
  156. :(MAPPER == 3'b110)
  157. ?(IS_SAVERAM
  158. ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
  159. & SAVERAM_MASK)
  160. :(SNES_ADDR[15]
  161. ?({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
  162. :({2'b10,
  163. SNES_ADDR[23],
  164. SNES_ADDR[21:16],
  165. SNES_ADDR[14:0]}
  166. )
  167. )
  168. )
  169. :(MAPPER == 3'b111)
  170. ?(IS_SAVERAM
  171. ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
  172. & SAVERAM_MASK)
  173. : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
  174. + 24'hE00000)
  175. )
  176. : 24'b0);
  177. assign ROM_ADDR = SRAM_ADDR_FULL[23:1];
  178. assign ROM_SEL = 1'b0; // (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK];
  179. assign ROM_ADDR0 = SRAM_ADDR_FULL[0];
  180. assign msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
  181. reg [7:0] msu_enable_r;
  182. initial msu_enable_r = 8'b00000000;
  183. always @(posedge CLK) msu_enable_r <= {msu_enable_r[6:0], msu_enable_w};
  184. assign msu_enable = &msu_enable_r[5:2];
  185. assign use_bsx = (MAPPER == 3'b011);
  186. assign srtc_enable = featurebits[FEAT_SRTC] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
  187. // DSP1 LoROM: DR=30-3f:8000-bfff; SR=30-3f:c000-ffff
  188. // or DR=60-6f:0000-3fff; SR=60-6f:4000-7fff
  189. // DSP1 HiROM: DR=00-0f:6000-6fff; SR=00-0f:7000-7fff
  190. wire dspx_enable_w =
  191. featurebits[FEAT_DSPX]
  192. ?((MAPPER == 3'b001)
  193. ?(ROM_MASK[20]
  194. ?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
  195. :(~SNES_ADDR[22] & SNES_ADDR[21] & SNES_ADDR[20] & SNES_ADDR[15])
  196. )
  197. :(MAPPER == 3'b000)
  198. ?(~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15]
  199. & &SNES_ADDR[14:13])
  200. :1'b0)
  201. :featurebits[FEAT_ST0010]
  202. ?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & &(~SNES_ADDR[19:16]) & ~SNES_ADDR[15])
  203. :1'b0;
  204. wire dspx_dp_enable_w = featurebits[FEAT_ST0010]
  205. &(SNES_ADDR[22:19] == 4'b1101
  206. && SNES_ADDR[15:11] == 5'b00000);
  207. assign dspx_a0 = featurebits[FEAT_DSPX]
  208. ?((MAPPER == 3'b001) ? SNES_ADDR[14]
  209. :(MAPPER == 3'b000) ? SNES_ADDR[12]
  210. :1'b1)
  211. :featurebits[FEAT_ST0010]
  212. ?SNES_ADDR[0]
  213. :1'b1;
  214. //reg [7:0] dspx_dp_enable_r;
  215. //initial dspx_dp_enable_r = 8'b00000000;
  216. //always @(posedge CLK) dspx_dp_enable_r <= {dspx_dp_enable_r[6:0], dspx_dp_enable_w};
  217. //assign dspx_dp_enable = &dspx_dp_enable_r[5:2];
  218. assign dspx_dp_enable = dspx_dp_enable_w;
  219. reg [7:0] dspx_enable_r;
  220. initial dspx_enable_r = 8'b00000000;
  221. always @(posedge CLK) dspx_enable_r <= {dspx_enable_r[6:0], dspx_enable_w};
  222. assign dspx_enable = &dspx_enable_r[5:2];
  223. endmodule