sd2snes.xise 4.0 KB

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  1. <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
  2. <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
  3. <header>
  4. <!-- ISE source project file created by Project Navigator. -->
  5. <!-- -->
  6. <!-- This file contains project source information including a list of -->
  7. <!-- project source files, project and process properties. This file, -->
  8. <!-- along with the project source files, is sufficient to open and -->
  9. <!-- implement in ISE Project Navigator. -->
  10. <!-- -->
  11. <!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
  12. </header>
  13. <version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
  14. <files>
  15. <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
  16. <association xil_pn:name="BehavioralSimulation"/>
  17. <association xil_pn:name="Implementation"/>
  18. </file>
  19. <file xil_pn:name="data.v" xil_pn:type="FILE_VERILOG">
  20. <association xil_pn:name="BehavioralSimulation"/>
  21. <association xil_pn:name="Implementation"/>
  22. </file>
  23. <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
  24. <association xil_pn:name="Implementation"/>
  25. </file>
  26. <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
  27. <association xil_pn:name="BehavioralSimulation"/>
  28. <association xil_pn:name="Implementation"/>
  29. </file>
  30. <file xil_pn:name="tf_main.v" xil_pn:type="FILE_VERILOG">
  31. <association xil_pn:name="BehavioralSimulation"/>
  32. <association xil_pn:name="PostRouteSimulation"/>
  33. <association xil_pn:name="PostMapSimulation"/>
  34. <association xil_pn:name="PostTranslateSimulation"/>
  35. </file>
  36. <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
  37. <association xil_pn:name="BehavioralSimulation"/>
  38. <association xil_pn:name="Implementation"/>
  39. </file>
  40. </files>
  41. <properties>
  42. <property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
  43. <property xil_pn:name="Device" xil_pn:value="xc3s200"/>
  44. <property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
  45. <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal"/>
  46. <property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
  47. <property xil_pn:name="Implementation Top" xil_pn:value="Module|main"/>
  48. <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main"/>
  49. <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tf_main"/>
  50. <property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes"/>
  51. <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|tf_main"/>
  52. <property xil_pn:name="Package" xil_pn:value="tq144"/>
  53. <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High"/>
  54. <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
  55. <property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
  56. <property xil_pn:name="Project Description" xil_pn:value="sd2snes"/>
  57. <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
  58. <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|tf_main"/>
  59. <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Module|tf_main"/>
  60. <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut"/>
  61. <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
  62. <property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
  63. <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
  64. <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
  65. <property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
  66. </properties>
  67. <bindings/>
  68. <libraries/>
  69. <partitions>
  70. <partition xil_pn:name="/main"/>
  71. </partitions>
  72. </project>