address.v 4.0 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: address
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Address logic w/ SaveRAM masking
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.02 - All new combinatorial glory. fucking slow.
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module address(
  22. input CLK,
  23. input [2:0] MAPPER, // AVR detected mapper
  24. input [23:0] SNES_ADDR, // requested address from SNES
  25. input SNES_CS, // "CART" pin from SNES (active low)
  26. output [20:0] SRAM_ADDR, // Address to request from SRAM
  27. output [3:0] ROM_SEL, // which SRAM unit to access (active low)
  28. input AVR_ADDR_RESET, // reset AVR sequence (active low)
  29. input AVR_NEXTADDR, // next byte request from AVR
  30. input AVR_ENA, // enable AVR master mode (active low)
  31. input AVR_ADDR_EN, // enable address counter (active low)
  32. input [1:0] AVR_BANK, // which bank does the AVR want
  33. input MODE, // AVR(1) or SNES(0) ("bus phase")
  34. output IS_SAVERAM, // address/CS mapped as SRAM?
  35. output IS_ROM, // address mapped as ROM?
  36. input AVR_NEXTADDR_CURR,
  37. input AVR_NEXTADDR_PREV
  38. );
  39. reg [22:0] SRAM_ADDR_BUF;
  40. reg [3:0] ROM_SEL_BUF;
  41. reg [3:0] AVR_ROM_SEL_BUF;
  42. reg [20:0] AVR_ADDR;
  43. reg [3:0] CS_ARRAY[3:0];
  44. wire [3:0] CURRENT_ROM_SEL;
  45. wire [22:0] SRAM_ADDR_FULL;
  46. initial begin
  47. AVR_ADDR = 21'b0;
  48. CS_ARRAY[0] = 4'b1110;
  49. CS_ARRAY[1] = 4'b1101;
  50. CS_ARRAY[2] = 4'b1011;
  51. CS_ARRAY[3] = 4'b0111;
  52. end
  53. /* currently supported mappers:
  54. Index Mapper
  55. 000 HiROM
  56. 001 LoROM
  57. */
  58. /* HiROM: SRAM @ Bank 0x20-0x3f, 0xa0-0xbf
  59. Offset 6000-7fff */
  60. assign IS_SAVERAM = ((MAPPER == 3'b000) ? (!SNES_ADDR[22]
  61. & SNES_ADDR[21]
  62. & &SNES_ADDR[14:13]
  63. & !SNES_ADDR[15]
  64. )
  65. /* LoROM: SRAM @ Bank 0x70-0x7f, 0xf0-0xff
  66. Offset 0000-7fff */
  67. :(MAPPER == 3'b001) ? (&SNES_ADDR[22:20]
  68. & !SNES_ADDR[15]
  69. & !SNES_CS)
  70. : 1'b0);
  71. assign IS_ROM = ((MAPPER == 3'b000) ? ( (!SNES_ADDR[22]
  72. & SNES_ADDR[15])
  73. |(SNES_ADDR[22]))
  74. :(MAPPER == 3'b001) ? ( (SNES_ADDR[15]) )
  75. : 1'b0);
  76. assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR
  77. : ((MAPPER == 3'b000) ?
  78. (IS_SAVERAM ? SNES_ADDR[14:0] - 15'h6000
  79. : SNES_ADDR[22:0])
  80. :(MAPPER == 3'b001) ?
  81. (IS_SAVERAM ? SNES_ADDR[14:0]
  82. : {1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]})
  83. : 21'b0);
  84. assign SRAM_BANK = SRAM_ADDR_FULL[22:21];
  85. assign SRAM_ADDR = SRAM_ADDR_FULL[20:0];
  86. assign ROM_SEL = (MODE) ? CS_ARRAY[AVR_BANK] : IS_SAVERAM ? 4'b0111 : 4'b1110; // CS_ARRAY[SRAM_BANK];
  87. //assign ROM_SEL = 4'b1110;
  88. always @(posedge CLK) begin
  89. if(AVR_NEXTADDR_CURR) begin
  90. if(!AVR_NEXTADDR_PREV) begin
  91. if(!AVR_ADDR_RESET)
  92. AVR_ADDR <= 21'b0;
  93. else if (!AVR_ADDR_EN)
  94. AVR_ADDR <= AVR_ADDR + 1;
  95. end
  96. end
  97. end
  98. /*
  99. always @(posedge AVR_NEXTADDR) begin
  100. if (!AVR_ADDR_RESET)
  101. AVR_ADDR <= 21'b0;
  102. else if (!AVR_ADDR_EN)
  103. AVR_ADDR <= AVR_ADDR + 1;
  104. end
  105. */
  106. endmodule