spi.v 2.8 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 21:16:09 07/10/2009
  7. // Design Name:
  8. // Module Name: spi
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module spi(
  22. input clk,
  23. input SCK,
  24. input MOSI,
  25. inout MISO,
  26. input SSEL,
  27. output cmd_ready,
  28. output param_ready,
  29. output [7:0] cmd_data,
  30. output [7:0] param_data,
  31. output endmessage,
  32. output startmessage,
  33. input [7:0] input_data,
  34. output [31:0] byte_cnt,
  35. output [2:0] bit_cnt
  36. );
  37. reg [7:0] cmd_data_r;
  38. reg [7:0] param_data_r;
  39. reg [1:0] SSELr; always @(posedge clk) SSELr <= {SSELr[0], SSEL};
  40. wire SSEL_active = ~SSELr[1]; // SSEL is active low
  41. wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge
  42. wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge
  43. assign endmessage = SSEL_endmessage;
  44. assign startmessage = SSEL_startmessage;
  45. // bit count for one SPI byte + byte count for the message
  46. reg [2:0] bitcnt;
  47. reg [31:0] byte_cnt_r;
  48. reg byte_received; // high when a byte has been received
  49. reg [7:0] byte_data_received;
  50. assign bit_cnt = bitcnt;
  51. always @(posedge SCK) begin
  52. if(SSEL) bitcnt <= 3'b000;
  53. else begin
  54. bitcnt <= bitcnt + 3'b001;
  55. byte_data_received <= {byte_data_received[6:0], MOSI};
  56. end
  57. if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1;
  58. else byte_received <= 1'b0;
  59. end
  60. reg [1:0] byte_received_r;
  61. always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received};
  62. wire byte_received_sync = (byte_received_r == 2'b01);
  63. always @(posedge clk) begin
  64. if(~SSEL_active)
  65. byte_cnt_r <= 16'h0000;
  66. else if(byte_received_sync) begin
  67. byte_cnt_r <= byte_cnt_r + 16'h0001;
  68. end
  69. end
  70. reg [7:0] byte_data_sent;
  71. assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
  72. reg cmd_ready_r;
  73. reg param_ready_r;
  74. reg cmd_ready_r2;
  75. reg param_ready_r2;
  76. assign cmd_ready = cmd_ready_r;
  77. assign param_ready = param_ready_r;
  78. assign cmd_data = cmd_data_r;
  79. assign param_data = param_data_r;
  80. assign byte_cnt = byte_cnt_r;
  81. always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
  82. always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
  83. // fill registers
  84. always @(posedge clk) begin
  85. if (SSEL_startmessage)
  86. cmd_data_r <= 8'h00;
  87. else if(cmd_ready_r2)
  88. cmd_data_r <= byte_data_received;
  89. else if(param_ready_r2)
  90. param_data_r <= byte_data_received;
  91. end
  92. // delay ready signals by one clock
  93. always @(posedge clk) begin
  94. cmd_ready_r <= cmd_ready_r2;
  95. param_ready_r <= param_ready_r2;
  96. end
  97. endmodule