mcu_cmd.v 16 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 21:57:50 08/25/2009
  7. // Design Name:
  8. // Module Name: mcu_cmd
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module mcu_cmd(
  22. input clk,
  23. input cmd_ready,
  24. input param_ready,
  25. input [7:0] cmd_data,
  26. input [7:0] param_data,
  27. output [2:0] mcu_mapper,
  28. output mcu_rrq,
  29. output mcu_write,
  30. output mcu_wrq,
  31. input mcu_rq_rdy,
  32. output [7:0] mcu_data_out,
  33. input [7:0] mcu_data_in,
  34. output [7:0] spi_data_out,
  35. input [31:0] spi_byte_cnt,
  36. input [2:0] spi_bit_cnt,
  37. output [23:0] addr_out,
  38. output [23:0] saveram_mask_out,
  39. output [23:0] rom_mask_out,
  40. output reg ramsel_out,
  41. // SD "DMA" extension
  42. output SD_DMA_EN,
  43. input SD_DMA_STATUS,
  44. input SD_DMA_NEXTADDR,
  45. input [7:0] SD_DMA_SRAM_DATA,
  46. input SD_DMA_SRAM_WE,
  47. output [1:0] SD_DMA_TGT,
  48. output SD_DMA_PARTIAL,
  49. output [10:0] SD_DMA_PARTIAL_START,
  50. output [10:0] SD_DMA_PARTIAL_END,
  51. // DAC
  52. output [10:0] dac_addr_out,
  53. input DAC_STATUS,
  54. output dac_play_out,
  55. output dac_reset_out,
  56. // MSU data
  57. output [13:0] msu_addr_out,
  58. input [6:0] MSU_STATUS,
  59. output [5:0] msu_status_reset_out,
  60. output [5:0] msu_status_set_out,
  61. output msu_status_reset_we,
  62. input [31:0] msu_addressrq,
  63. input [15:0] msu_trackrq,
  64. input [7:0] msu_volumerq,
  65. output [13:0] msu_ptr_out,
  66. output msu_reset_out,
  67. // BS-X
  68. output [7:0] bsx_regs_reset_out,
  69. output [7:0] bsx_regs_set_out,
  70. output bsx_regs_reset_we,
  71. // generic RTC
  72. output [55:0] rtc_data_out,
  73. output rtc_pgm_we,
  74. // S-RTC
  75. output srtc_reset,
  76. // uPD77C25
  77. output reg [23:0] dspx_pgm_data_out,
  78. output reg [10:0] dspx_pgm_addr_out,
  79. output reg dspx_pgm_we_out,
  80. output reg [15:0] dspx_dat_data_out,
  81. output reg [10:0] dspx_dat_addr_out,
  82. output reg dspx_dat_we_out,
  83. output reg dspx_reset_out,
  84. // feature enable
  85. output reg [3:0] featurebits_out,
  86. // SNES control signal/clock freqs
  87. input [31:0] snes_cpuclk_freq,
  88. input [31:0] snes_sysclk_freq,
  89. input [31:0] snes_read_freq,
  90. input [31:0] snes_write_freq,
  91. input [31:0] snes_pard_freq,
  92. input [31:0] snes_pawr_freq,
  93. input [31:0] snes_refresh_freq,
  94. input [31:0] snes_romsel_freq,
  95. output reg [12:0] mcu_bram_addr,
  96. input [7:0] mcu_bram_data_in,
  97. output reg [7:0] mcu_bram_data_out,
  98. output reg mcu_bram_we
  99. );
  100. initial begin
  101. dspx_pgm_addr_out = 11'b00000000000;
  102. dspx_dat_addr_out = 10'b0000000000;
  103. dspx_reset_out = 1'b1;
  104. ramsel_out = 1'b0;
  105. end
  106. reg [2:0] MAPPER_BUF;
  107. reg [23:0] ADDR_OUT_BUF;
  108. reg [10:0] DAC_ADDR_OUT_BUF;
  109. reg [7:0] DAC_VOL_OUT_BUF;
  110. reg DAC_VOL_LATCH_BUF;
  111. reg DAC_PLAY_OUT_BUF;
  112. reg DAC_RESET_OUT_BUF;
  113. reg [13:0] MSU_ADDR_OUT_BUF;
  114. reg [13:0] MSU_PTR_OUT_BUF;
  115. reg [5:0] msu_status_set_out_buf;
  116. reg [5:0] msu_status_reset_out_buf;
  117. reg msu_status_reset_we_buf;
  118. reg MSU_RESET_OUT_BUF;
  119. reg [7:0] bsx_regs_set_out_buf;
  120. reg [7:0] bsx_regs_reset_out_buf;
  121. reg bsx_regs_reset_we_buf;
  122. reg [55:0] rtc_data_out_buf;
  123. reg rtc_pgm_we_buf;
  124. reg srtc_reset_buf;
  125. reg [31:0] SNES_SYSCLK_FREQ_BUF;
  126. reg [7:0] MCU_DATA_OUT_BUF;
  127. reg [7:0] MCU_DATA_IN_BUF;
  128. reg [1:0] mcu_nextaddr_buf;
  129. wire mcu_nextaddr;
  130. reg DAC_STATUSr;
  131. reg SD_DMA_STATUSr;
  132. reg [6:0] MSU_STATUSr;
  133. always @(posedge clk) begin
  134. DAC_STATUSr <= DAC_STATUS;
  135. SD_DMA_STATUSr <= SD_DMA_STATUS;
  136. MSU_STATUSr <= MSU_STATUS;
  137. end
  138. reg SD_DMA_PARTIALr;
  139. assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
  140. reg SD_DMA_ENr;
  141. assign SD_DMA_EN = SD_DMA_ENr;
  142. reg [1:0] SD_DMA_TGTr;
  143. assign SD_DMA_TGT = SD_DMA_TGTr;
  144. reg [10:0] SD_DMA_PARTIAL_STARTr;
  145. reg [10:0] SD_DMA_PARTIAL_ENDr;
  146. assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
  147. assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
  148. reg [23:0] SAVERAM_MASK;
  149. reg [23:0] ROM_MASK;
  150. assign spi_data_out = MCU_DATA_IN_BUF;
  151. initial begin
  152. ADDR_OUT_BUF = 0;
  153. DAC_ADDR_OUT_BUF = 0;
  154. MSU_ADDR_OUT_BUF = 0;
  155. SD_DMA_ENr = 0;
  156. MAPPER_BUF = 1;
  157. end
  158. // command interpretation
  159. always @(posedge clk) begin
  160. if (cmd_ready) begin
  161. case (cmd_data[7:4])
  162. 4'h3: // select mapper
  163. MAPPER_BUF <= cmd_data[2:0];
  164. 4'h4: begin// SD DMA
  165. SD_DMA_ENr <= 1;
  166. SD_DMA_TGTr <= cmd_data[1:0];
  167. SD_DMA_PARTIALr <= cmd_data[2];
  168. end
  169. 4'h8: SD_DMA_TGTr <= 2'b00;
  170. 4'h9: SD_DMA_TGTr <= cmd_data[1:0]; // not implemented
  171. endcase
  172. end else if (param_ready) begin
  173. casex (cmd_data[7:0])
  174. 8'h1x:
  175. case (spi_byte_cnt)
  176. 32'h2:
  177. ROM_MASK[23:16] <= param_data;
  178. 32'h3:
  179. ROM_MASK[15:8] <= param_data;
  180. 32'h4:
  181. ROM_MASK[7:0] <= param_data;
  182. endcase
  183. 8'h2x:
  184. case (spi_byte_cnt)
  185. 32'h2:
  186. SAVERAM_MASK[23:16] <= param_data;
  187. 32'h3:
  188. SAVERAM_MASK[15:8] <= param_data;
  189. 32'h4:
  190. SAVERAM_MASK[7:0] <= param_data;
  191. endcase
  192. 8'h4x:
  193. SD_DMA_ENr <= 1'b0;
  194. 8'h6x:
  195. case (spi_byte_cnt)
  196. 32'h2:
  197. SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
  198. 32'h3:
  199. SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
  200. 32'h4:
  201. SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
  202. 32'h5:
  203. SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
  204. endcase
  205. 8'h9x:
  206. MCU_DATA_OUT_BUF <= param_data;
  207. 8'he0:
  208. case (spi_byte_cnt)
  209. 32'h2: begin
  210. msu_status_set_out_buf <= param_data[5:0];
  211. end
  212. 32'h3: begin
  213. msu_status_reset_out_buf <= param_data[5:0];
  214. msu_status_reset_we_buf <= 1'b1;
  215. end
  216. 32'h4:
  217. msu_status_reset_we_buf <= 1'b0;
  218. endcase
  219. 8'he1: // pause DAC
  220. DAC_PLAY_OUT_BUF <= 1'b0;
  221. 8'he2: // resume DAC
  222. DAC_PLAY_OUT_BUF <= 1'b1;
  223. 8'he3: // reset DAC (set DAC playback address = 0)
  224. case (spi_byte_cnt)
  225. 32'h2:
  226. DAC_RESET_OUT_BUF <= 1'b1;
  227. 32'h3:
  228. DAC_RESET_OUT_BUF <= 1'b0;
  229. endcase
  230. 8'he4: // reset MSU read buffer pointer
  231. case (spi_byte_cnt)
  232. 32'h2: begin
  233. MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
  234. MSU_PTR_OUT_BUF[7:0] <= 8'h0;
  235. end
  236. 32'h3: begin
  237. MSU_PTR_OUT_BUF[7:0] <= param_data;
  238. MSU_RESET_OUT_BUF <= 1'b1;
  239. end
  240. 32'h4:
  241. MSU_RESET_OUT_BUF <= 1'b0;
  242. endcase
  243. 8'he5:
  244. case (spi_byte_cnt)
  245. 32'h2:
  246. rtc_data_out_buf[55:48] <= param_data;
  247. 32'h3:
  248. rtc_data_out_buf[47:40] <= param_data;
  249. 32'h4:
  250. rtc_data_out_buf[39:32] <= param_data;
  251. 32'h5:
  252. rtc_data_out_buf[31:24] <= param_data;
  253. 32'h6:
  254. rtc_data_out_buf[23:16] <= param_data;
  255. 32'h7:
  256. rtc_data_out_buf[15:8] <= param_data;
  257. 32'h8: begin
  258. rtc_data_out_buf[7:0] <= param_data;
  259. rtc_pgm_we_buf <= 1'b1;
  260. end
  261. 32'h9:
  262. rtc_pgm_we_buf <= 1'b0;
  263. endcase
  264. 8'he6:
  265. case (spi_byte_cnt)
  266. 32'h2: begin
  267. bsx_regs_set_out_buf <= param_data[7:0];
  268. end
  269. 32'h3: begin
  270. bsx_regs_reset_out_buf <= param_data[7:0];
  271. bsx_regs_reset_we_buf <= 1'b1;
  272. end
  273. 32'h4:
  274. bsx_regs_reset_we_buf <= 1'b0;
  275. endcase
  276. 8'he7:
  277. case (spi_byte_cnt)
  278. 32'h2: begin
  279. srtc_reset_buf <= 1'b1;
  280. end
  281. 32'h3: begin
  282. srtc_reset_buf <= 1'b0;
  283. end
  284. endcase
  285. 8'he8: begin // set BRAM address
  286. case (spi_byte_cnt)
  287. 32'h2: mcu_bram_addr[12:8] <= param_data[4:0];
  288. 32'h3: mcu_bram_addr[7:0] <= param_data[7:0];
  289. endcase
  290. end
  291. 8'he9: begin // write BRAM
  292. case (spi_byte_cnt)
  293. 32'h2: begin
  294. mcu_bram_data_out <= param_data;
  295. mcu_bram_we <= 1'b1;
  296. end
  297. 32'h3: mcu_bram_we <= 1'b0;
  298. 32'h4: mcu_bram_addr <= mcu_bram_addr + 1;
  299. endcase
  300. end
  301. 8'hee:
  302. ramsel_out <= param_data[0];
  303. 8'hf5:
  304. if (spi_byte_cnt == 32'h3) mcu_bram_addr <= mcu_bram_addr + 1;
  305. endcase
  306. end
  307. end
  308. always @(posedge clk) begin
  309. if(param_ready && cmd_data[7:4] == 4'h0) begin
  310. case (cmd_data[1:0])
  311. 2'b01: begin
  312. case (spi_byte_cnt)
  313. 32'h2: begin
  314. DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
  315. DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
  316. end
  317. 32'h3:
  318. DAC_ADDR_OUT_BUF[7:0] <= param_data;
  319. endcase
  320. end
  321. 2'b10: begin
  322. case (spi_byte_cnt)
  323. 32'h2: begin
  324. MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
  325. MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
  326. end
  327. 32'h3:
  328. MSU_ADDR_OUT_BUF[7:0] <= param_data;
  329. endcase
  330. end
  331. default:
  332. case (spi_byte_cnt)
  333. 32'h2: begin
  334. ADDR_OUT_BUF[23:16] <= param_data;
  335. ADDR_OUT_BUF[15:0] <= 16'b0;
  336. end
  337. 32'h3:
  338. ADDR_OUT_BUF[15:8] <= param_data;
  339. 32'h4:
  340. ADDR_OUT_BUF[7:0] <= param_data;
  341. endcase
  342. endcase
  343. end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
  344. && (cmd_data[3])
  345. && (spi_byte_cnt >= (32'h1+cmd_data[4])))
  346. )
  347. begin
  348. case (SD_DMA_TGTr)
  349. 2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
  350. 2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
  351. 2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
  352. endcase
  353. end
  354. end
  355. // value fetch during last SPI bit
  356. always @(posedge clk) begin
  357. if (cmd_data[7:4] == 4'h8 && mcu_nextaddr_buf == 2'b01)
  358. MCU_DATA_IN_BUF <= mcu_data_in;
  359. else if (spi_bit_cnt == 3'h7) begin
  360. if (cmd_data[7:0] == 8'hF0)
  361. MCU_DATA_IN_BUF <= 8'hA5;
  362. else if (cmd_data[7:0] == 8'hF1)
  363. case (spi_byte_cnt[0])
  364. 1'b1: // buffer status (1st byte)
  365. MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[6], 5'b0};
  366. 1'b0: // control status (2nd byte)
  367. MCU_DATA_IN_BUF <= {2'b0, MSU_STATUSr[5:0]};
  368. endcase
  369. else if (cmd_data[7:0] == 8'hF2)
  370. case (spi_byte_cnt)
  371. 32'h1:
  372. MCU_DATA_IN_BUF <= msu_addressrq[31:24];
  373. 32'h2:
  374. MCU_DATA_IN_BUF <= msu_addressrq[23:16];
  375. 32'h3:
  376. MCU_DATA_IN_BUF <= msu_addressrq[15:8];
  377. 32'h4:
  378. MCU_DATA_IN_BUF <= msu_addressrq[7:0];
  379. endcase
  380. else if (cmd_data[7:0] == 8'hF3)
  381. case (spi_byte_cnt)
  382. 32'h1:
  383. MCU_DATA_IN_BUF <= msu_trackrq[15:8];
  384. 32'h2:
  385. MCU_DATA_IN_BUF <= msu_trackrq[7:0];
  386. endcase
  387. else if (cmd_data[7:0] == 8'hF4)
  388. MCU_DATA_IN_BUF <= msu_volumerq;
  389. else if (cmd_data[7:0] == 8'hF5)
  390. MCU_DATA_IN_BUF <= mcu_bram_data_in;
  391. else if (cmd_data[7:0] == 8'hF7)
  392. case (spi_byte_cnt)
  393. 32'h1:
  394. SNES_SYSCLK_FREQ_BUF <= snes_romsel_freq;
  395. 32'h2:
  396. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  397. 32'h3:
  398. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  399. 32'h4:
  400. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  401. 32'h5:
  402. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  403. endcase
  404. else if (cmd_data[7:0] == 8'hF8)
  405. case (spi_byte_cnt)
  406. 32'h1:
  407. SNES_SYSCLK_FREQ_BUF <= snes_cpuclk_freq;
  408. 32'h2:
  409. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  410. 32'h3:
  411. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  412. 32'h4:
  413. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  414. 32'h5:
  415. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  416. endcase
  417. else if (cmd_data[7:0] == 8'hF9)
  418. case (spi_byte_cnt)
  419. 32'h1:
  420. SNES_SYSCLK_FREQ_BUF <= snes_read_freq;
  421. 32'h2:
  422. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  423. 32'h3:
  424. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  425. 32'h4:
  426. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  427. 32'h5:
  428. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  429. endcase
  430. else if (cmd_data[7:0] == 8'hFA)
  431. case (spi_byte_cnt)
  432. 32'h1:
  433. SNES_SYSCLK_FREQ_BUF <= snes_write_freq;
  434. 32'h2:
  435. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  436. 32'h3:
  437. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  438. 32'h4:
  439. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  440. 32'h5:
  441. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  442. endcase
  443. else if (cmd_data[7:0] == 8'hFB)
  444. case (spi_byte_cnt)
  445. 32'h1:
  446. SNES_SYSCLK_FREQ_BUF <= snes_pard_freq;
  447. 32'h2:
  448. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  449. 32'h3:
  450. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  451. 32'h4:
  452. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  453. 32'h5:
  454. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  455. endcase
  456. else if (cmd_data[7:0] == 8'hFC)
  457. case (spi_byte_cnt)
  458. 32'h1:
  459. SNES_SYSCLK_FREQ_BUF <= snes_pawr_freq;
  460. 32'h2:
  461. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  462. 32'h3:
  463. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  464. 32'h4:
  465. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  466. 32'h5:
  467. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  468. endcase
  469. else if (cmd_data[7:0] == 8'hFD)
  470. case (spi_byte_cnt)
  471. 32'h1:
  472. SNES_SYSCLK_FREQ_BUF <= snes_refresh_freq;
  473. 32'h2:
  474. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  475. 32'h3:
  476. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  477. 32'h4:
  478. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  479. 32'h5:
  480. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  481. endcase
  482. else if (cmd_data[7:0] == 8'hFE)
  483. case (spi_byte_cnt)
  484. 32'h1:
  485. SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
  486. 32'h2:
  487. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
  488. 32'h3:
  489. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
  490. 32'h4:
  491. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
  492. 32'h5:
  493. MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
  494. endcase
  495. else if (cmd_data[7:0] == 8'hFF)
  496. MCU_DATA_IN_BUF <= param_data;
  497. end
  498. end
  499. // nextaddr pulse generation
  500. always @(posedge clk) begin
  501. mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], mcu_rq_rdy};
  502. end
  503. parameter ST_RQ = 2'b01;
  504. parameter ST_IDLE = 2'b10;
  505. reg [1:0] rrq_state;
  506. initial rrq_state = ST_IDLE;
  507. reg mcu_rrq_r;
  508. reg [1:0] wrq_state;
  509. initial wrq_state = ST_IDLE;
  510. reg mcu_wrq_r;
  511. always @(posedge clk) begin
  512. case(rrq_state)
  513. ST_IDLE: begin
  514. if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
  515. mcu_rrq_r <= 1'b1;
  516. rrq_state <= ST_RQ;
  517. end else
  518. rrq_state <= ST_IDLE;
  519. end
  520. ST_RQ: begin
  521. mcu_rrq_r <= 1'b0;
  522. rrq_state <= ST_IDLE;
  523. end
  524. endcase
  525. end
  526. always @(posedge clk) begin
  527. case(wrq_state)
  528. ST_IDLE: begin
  529. if(param_ready && cmd_data[7:4] == 4'h9) begin
  530. mcu_wrq_r <= 1'b1;
  531. wrq_state <= ST_RQ;
  532. end else
  533. wrq_state <= ST_IDLE;
  534. end
  535. ST_RQ: begin
  536. mcu_wrq_r <= 1'b0;
  537. wrq_state <= ST_IDLE;
  538. end
  539. endcase
  540. end
  541. // trigger for nextaddr
  542. assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
  543. assign mcu_rrq = mcu_rrq_r;
  544. assign mcu_wrq = mcu_wrq_r;
  545. assign mcu_write = SD_DMA_STATUS
  546. ?(SD_DMA_TGTr == 2'b00
  547. ?SD_DMA_SRAM_WE
  548. :1'b1
  549. )
  550. : 1'b1;
  551. assign addr_out = ADDR_OUT_BUF;
  552. assign dac_addr_out = DAC_ADDR_OUT_BUF;
  553. assign msu_addr_out = MSU_ADDR_OUT_BUF;
  554. assign dac_play_out = DAC_PLAY_OUT_BUF;
  555. assign dac_reset_out = DAC_RESET_OUT_BUF;
  556. assign msu_status_reset_we = msu_status_reset_we_buf;
  557. assign msu_status_reset_out = msu_status_reset_out_buf;
  558. assign msu_status_set_out = msu_status_set_out_buf;
  559. assign msu_reset_out = MSU_RESET_OUT_BUF;
  560. assign msu_ptr_out = MSU_PTR_OUT_BUF;
  561. assign bsx_regs_reset_we = bsx_regs_reset_we_buf;
  562. assign bsx_regs_reset_out = bsx_regs_reset_out_buf;
  563. assign bsx_regs_set_out = bsx_regs_set_out_buf;
  564. assign rtc_data_out = rtc_data_out_buf;
  565. assign rtc_pgm_we = rtc_pgm_we_buf;
  566. assign srtc_reset = srtc_reset_buf;
  567. assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
  568. assign mcu_mapper = MAPPER_BUF;
  569. assign rom_mask_out = ROM_MASK;
  570. assign saveram_mask_out = SAVERAM_MASK;
  571. endmodule