clk_test.v 3.4 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 22:40:46 12/20/2010
  7. // Design Name:
  8. // Module Name: clk_test
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module clk_test(
  22. input clk,
  23. input sysclk,
  24. input read,
  25. input write,
  26. input pawr,
  27. input pard,
  28. input refresh,
  29. input cpuclk,
  30. input romsel,
  31. output reg [31:0] snes_sysclk_freq,
  32. output reg [31:0] snes_read_freq,
  33. output reg [31:0] snes_write_freq,
  34. output reg [31:0] snes_pawr_freq,
  35. output reg [31:0] snes_pard_freq,
  36. output reg [31:0] snes_refresh_freq,
  37. output reg [31:0] snes_cpuclk_freq,
  38. output reg [31:0] snes_romsel_freq
  39. );
  40. reg [31:0] sysclk_counter;
  41. reg [31:0] sysclk_value;
  42. reg [31:0] read_value;
  43. reg [31:0] write_value;
  44. reg [31:0] pard_value;
  45. reg [31:0] pawr_value;
  46. reg [31:0] refresh_value;
  47. reg [31:0] cpuclk_value;
  48. reg [31:0] romsel_value;
  49. initial snes_sysclk_freq = 32'hFFFFFFFF;
  50. initial sysclk_counter = 0;
  51. initial sysclk_value = 0;
  52. initial read_value = 0;
  53. initial write_value = 0;
  54. initial pard_value = 0;
  55. initial pawr_value = 0;
  56. initial refresh_value = 0;
  57. initial cpuclk_value = 0;
  58. initial romsel_value = 0;
  59. reg [1:0] sysclk_sreg;
  60. reg [1:0] read_sreg;
  61. reg [1:0] write_sreg;
  62. reg [1:0] pard_sreg;
  63. reg [1:0] pawr_sreg;
  64. reg [1:0] refresh_sreg;
  65. reg [1:0] cpuclk_sreg;
  66. reg [1:0] romsel_sreg;
  67. always @(posedge clk) romsel_sreg <= {romsel_sreg[0], romsel};
  68. wire romsel_rising = (romsel_sreg == 2'b01);
  69. always @(posedge clk) cpuclk_sreg <= {cpuclk_sreg[0], cpuclk};
  70. wire cpuclk_rising = (cpuclk_sreg == 2'b01);
  71. always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
  72. wire sysclk_rising = (sysclk_sreg == 2'b01);
  73. always @(posedge clk) read_sreg <= {read_sreg[0], read};
  74. wire read_rising = (read_sreg == 2'b01);
  75. always @(posedge clk) write_sreg <= {write_sreg[0], write};
  76. wire write_rising = (write_sreg == 2'b01);
  77. always @(posedge clk) pard_sreg <= {pard_sreg[0], pard};
  78. wire pard_rising = (pard_sreg == 2'b01);
  79. always @(posedge clk) pawr_sreg <= {pawr_sreg[0], pawr};
  80. wire pawr_rising = (pawr_sreg == 2'b01);
  81. always @(posedge clk) refresh_sreg <= {refresh_sreg[0], refresh};
  82. wire refresh_rising = (refresh_sreg == 2'b01);
  83. always @(posedge clk) begin
  84. if(sysclk_counter < 96000000) begin
  85. sysclk_counter <= sysclk_counter + 1;
  86. if(sysclk_rising) sysclk_value <= sysclk_value + 1;
  87. if(read_rising) read_value <= read_value + 1;
  88. if(write_rising) write_value <= write_value + 1;
  89. if(pard_rising) pard_value <= pard_value + 1;
  90. if(pawr_rising) pawr_value <= pawr_value + 1;
  91. if(refresh_rising) refresh_value <= refresh_value + 1;
  92. if(cpuclk_rising) cpuclk_value <= cpuclk_value + 1;
  93. if(romsel_rising) romsel_value <= romsel_value + 1;
  94. end else begin
  95. snes_sysclk_freq <= sysclk_value;
  96. snes_read_freq <= read_value;
  97. snes_write_freq <= write_value;
  98. snes_pard_freq <= pard_value;
  99. snes_pawr_freq <= pawr_value;
  100. snes_refresh_freq <= refresh_value;
  101. snes_cpuclk_freq <= cpuclk_value;
  102. snes_romsel_freq <= romsel_value;
  103. sysclk_counter <= 0;
  104. sysclk_value <= 0;
  105. read_value <= 0;
  106. write_value <= 0;
  107. pard_value <= 0;
  108. pawr_value <= 0;
  109. refresh_value <= 0;
  110. cpuclk_value <= 0;
  111. romsel_value <= 0;
  112. end
  113. end
  114. endmodule