address.v 2.1 KB

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  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: address
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Address logic w/ SaveRAM masking
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Additional Comments:
  18. //
  19. //////////////////////////////////////////////////////////////////////////////////
  20. module address(
  21. input CLK,
  22. input [23:0] SNES_ADDR, // requested address from SNES
  23. output [23:0] ram0_addr,
  24. output [18:0] ram1_addr,
  25. output [7:0] PA_addr,
  26. output [12:0] bram_addr,
  27. input [7:0] ram0_bank,
  28. input ram0_linear,
  29. output ram0_enable,
  30. output ram1_enable,
  31. output PA_enable,
  32. output bram_enable,
  33. output irq_enable,
  34. output bank_enable,
  35. output linear_enable
  36. );
  37. wire [23:0] SRAM_SNES_ADDR;
  38. assign ram0bank0_enable = (SNES_ADDR[23:15] == 9'h001) | (SNES_ADDR[23:16] == 8'hC0);
  39. assign ram0bankx_enable = (SNES_ADDR[23:16] == 8'hC8);
  40. assign ram0linear_enable = ram0_linear & (SNES_ADDR[22] | SNES_ADDR[15]);
  41. assign ram0_enable = ram0linear_enable | ram0bank0_enable | ram0bankx_enable;
  42. assign ram1_enable = ~ram0_enable & (SNES_ADDR[23:20] == 4'hD);
  43. assign PA_enable = ~ram0_enable & (SNES_ADDR[23:20] == 4'hE);
  44. assign bram_enable = ~ram0_enable & (SNES_ADDR[23:20] == 4'hF);
  45. wire bank_enable_ = (SNES_ADDR == 24'h0055AA);
  46. wire irq_enable_ = (SNES_ADDR == 24'h002222);
  47. wire linear_enable_ = (SNES_ADDR == 24'h003333);
  48. reg [2:0] bank_enable_r;
  49. reg [2:0] irq_enable_r;
  50. reg [2:0] linear_enable_r;
  51. always @(posedge CLK) begin
  52. bank_enable_r <= {bank_enable_r[1:0], bank_enable_};
  53. irq_enable_r <= {irq_enable_r[1:0], irq_enable_};
  54. linear_enable_r <= {linear_enable_r[1:0], linear_enable_};
  55. end
  56. assign bank_enable = bank_enable_r[2];
  57. assign irq_enable = irq_enable_r[2];
  58. assign linear_enable = linear_enable_r[2];
  59. assign ram0_addr = ram0_linear ? SNES_ADDR
  60. : {2'b00,SNES_ADDR[21:0]};
  61. assign ram1_addr = SNES_ADDR[18:0];
  62. assign PA_addr = SNES_ADDR[7:0];
  63. assign bram_addr = SNES_ADDR[12:0];
  64. endmodule