fpga.h 2.2 KB

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  1. /* sd2snes - SD card based universal cartridge for the SNES
  2. Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
  3. AVR firmware portion
  4. Inspired by and based on code from sd2iec, written by Ingo Korb et al.
  5. See sdcard.c|h, config.h.
  6. FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
  7. see ff.c|h.
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; version 2 of the License only.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. fpga.h: FPGA (re)configuration
  19. */
  20. #ifndef FPGA_H
  21. #define FPGA_H
  22. #include <arm/NXP/LPC17xx/LPC17xx.h>
  23. #include "bits.h"
  24. void fpga_set_prog_b(uint8_t val);
  25. void fpga_set_cclk(uint8_t val);
  26. int fpga_get_initb(void);
  27. void fpga_init(void);
  28. void fpga_postinit(void);
  29. void fpga_pgm(uint8_t* filename);
  30. uint8_t SPI_OFFLOAD;
  31. #define CCLKREG LPC_GPIO0
  32. #define PROGBREG LPC_GPIO1
  33. #define INITBREG LPC_GPIO2
  34. #define DINREG LPC_GPIO2
  35. #define DONEREG LPC_GPIO0
  36. #define CCLKBIT (11)
  37. #define PROGBBIT (15)
  38. #define INITBBIT (9)
  39. #define DINBIT (8)
  40. #define DONEBIT (22)
  41. #define FPGA_TEST_TOKEN (0xa5)
  42. // some macros for bulk transfers (faster)
  43. #define FPGA_SEND_BYTE_SERIAL(data) do {SET_FPGA_DIN(data>>7); CCLK();\
  44. SET_FPGA_DIN(data>>6); CCLK(); SET_FPGA_DIN(data>>5); CCLK();\
  45. SET_FPGA_DIN(data>>4); CCLK(); SET_FPGA_DIN(data>>3); CCLK();\
  46. SET_FPGA_DIN(data>>2); CCLK(); SET_FPGA_DIN(data>>1); CCLK();\
  47. SET_FPGA_DIN(data); CCLK();} while (0)
  48. #define SET_CCLK() do {BITBAND(LPC_GPIO0->FIOSET, 11) = 1;} while (0)
  49. #define CLR_CCLK() do {BITBAND(LPC_GPIO0->FIOCLR, 11) = 1;} while (0)
  50. #define CCLK() do {SET_CCLK(); CLR_CCLK();} while (0)
  51. #define SET_FPGA_DIN(data) do {LPC_GPIO2->FIOPIN1 = data;} while (0)
  52. #endif