sd2snes.sch 2.2 KB

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  1. EESchema Schematic File Version 2 date Thu 16 Jun 2011 09:32:02 PM CEST
  2. LIBS:power
  3. LIBS:device
  4. LIBS:transistors
  5. LIBS:conn
  6. LIBS:linear
  7. LIBS:regul
  8. LIBS:74xx
  9. LIBS:cmos4000
  10. LIBS:adc-dac
  11. LIBS:memory
  12. LIBS:xilinx
  13. LIBS:special
  14. LIBS:microcontrollers
  15. LIBS:dsp
  16. LIBS:microchip
  17. LIBS:analog_switches
  18. LIBS:motorola
  19. LIBS:texas
  20. LIBS:intel
  21. LIBS:audio
  22. LIBS:interface
  23. LIBS:digital-audio
  24. LIBS:philips
  25. LIBS:display
  26. LIBS:cypress
  27. LIBS:siliconi
  28. LIBS:opto
  29. LIBS:atmel
  30. LIBS:contrib
  31. LIBS:valves
  32. LIBS:snescart
  33. LIBS:misc-74
  34. LIBS:vreg
  35. LIBS:lpc1754
  36. LIBS:sd_card
  37. LIBS:cy62148ev30
  38. LIBS:mt45w8mw16
  39. LIBS:cs4344
  40. LIBS:double_sch_kcom
  41. LIBS:usb_minib
  42. LIBS:mic23250
  43. LIBS:sd2snes-cache
  44. EELAYER 25 0
  45. EELAYER END
  46. $Descr A4 11700 8267
  47. Sheet 1 6
  48. Title "sd2snes Mark II"
  49. Date "16 jun 2011"
  50. Rev "C"
  51. Comp "Maximilian Rehkopf"
  52. Comment1 ""
  53. Comment2 ""
  54. Comment3 ""
  55. Comment4 ""
  56. $EndDescr
  57. Wire Notes Line
  58. 3650 4200 6150 4200
  59. Text Notes 3300 3250 0 100 ~ 0
  60. Changes from Rev.A / TODO:\n [x] remove FPGA from JTAG chain\n [x] remove SNES IRQ_DIR+IRQ, replace with IRQ_OE. IRQ is unidirectional cart -> console\n (replace 1gate w/ transistor)\n [x] disconnect P2.10 from FPGA, using a different GPIO for IRQ / INIT_B\n [x] add pullup to P2.10\n [ ] add JTAG pullups\n [x] add series resistor for CPU_CLK\n [x] add a jumper in PIC MCLR line to MCU\n [x] change PIC to DIP8 type for easier preprogramming\n [x] change "P1" to "P401" in pin description in silk screen\n [x] filter CIC data lines\n [x] rearrange SD card interface/LEDs on MCU\n [x] RAs for SNES signals?\n [x] reroute/add decoupling capacitors\n [x] filter SNES control signals (RD, WR, PARD, PAWR, CPU_CLK, IRQ)\n [x] replace 4Mbit SRAM with much cheaper TSOP-II type\n [x] add inverse polarity protection\n [x] separate GND plane for DAC\n [ ] separate JTAG pads for FPGA
  61. $Sheet
  62. S 1250 1250 1700 1250
  63. U 4B6E16F2
  64. F0 "SNES Slot" 60
  65. F1 "snesslot.sch" 60
  66. $EndSheet
  67. Text Notes 750 7700 0 500 ~ 100
  68. sd2snes Mark II
  69. $Sheet
  70. S 1250 3300 1600 1150
  71. U 4BAA6ABD
  72. F0 "Memory" 60
  73. F1 "memory.sch" 60
  74. $EndSheet
  75. $Sheet
  76. S 8050 1250 1600 1250
  77. U 4B6ED75B
  78. F0 "MCU" 60
  79. F1 "mcu.sch" 60
  80. $EndSheet
  81. $Sheet
  82. S 5900 1250 1600 1250
  83. U 4B6EC9C3
  84. F0 "Power Supply / Misc." 60
  85. F1 "pwr_misc.sch" 60
  86. $EndSheet
  87. $Sheet
  88. S 3650 1250 1650 1250
  89. U 4B6E18FC
  90. F0 "FPGA" 60
  91. F1 "fpga.sch" 60
  92. $EndSheet
  93. $EndSCHEMATC