memory.c 7.5 KB

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  1. /* sd2snes - SD card based universal cartridge for the SNES
  2. Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
  3. AVR firmware portion
  4. Inspired by and based on code from sd2iec, written by Ingo Korb et al.
  5. See sdcard.c|h, config.h.
  6. FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
  7. see ff.c|h.
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; version 2 of the License only.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. memory.c: RAM operations
  19. */
  20. #include <stdint.h>
  21. #include <avr/pgmspace.h>
  22. #include <util/delay.h>
  23. #include "config.h"
  24. #include "uart.h"
  25. #include "fpga.h"
  26. #include "crc16.h"
  27. #include "ff.h"
  28. #include "fileops.h"
  29. #include "spi.h"
  30. #include "fpga_spi.h"
  31. #include "avrcompat.h"
  32. #include "led.h"
  33. #include "smc.h"
  34. #include "fpga_spi.h"
  35. #include "memory.h"
  36. #include "snes.h"
  37. char* hex = "0123456789ABCDEF";
  38. void sram_hexdump(uint32_t addr, uint32_t len) {
  39. static uint8_t buf[16];
  40. uint32_t ptr;
  41. for(ptr=0; ptr < len; ptr += 16) {
  42. sram_readblock((void*)buf, ptr+addr, 16);
  43. uart_trace(buf, 0, 16);
  44. }
  45. }
  46. void sram_writebyte(uint8_t val, uint32_t addr) {
  47. set_avr_addr(addr);
  48. spi_fpga();
  49. spiTransferByte(0x91); // WRITE
  50. spiTransferByte(val);
  51. spiTransferByte(0x00); // dummy
  52. spi_none();
  53. }
  54. uint8_t sram_readbyte(uint32_t addr) {
  55. set_avr_addr(addr);
  56. spi_fpga();
  57. spiTransferByte(0x81); // READ
  58. spiTransferByte(0x00); // dummy
  59. uint8_t val = spiTransferByte(0x00);
  60. spi_none();
  61. return val;
  62. }
  63. void sram_writeshort(uint16_t val, uint32_t addr) {
  64. set_avr_addr(addr);
  65. spi_fpga();
  66. spiTransferByte(0x91); // WRITE
  67. spiTransferByte(val&0xff); // 7-0
  68. spiTransferByte((val>>8)&0xff); // 15-8
  69. spiTransferByte(0x00); // dummy
  70. spi_none();
  71. }
  72. void sram_writelong(uint32_t val, uint32_t addr) {
  73. set_avr_addr(addr);
  74. spi_fpga();
  75. spiTransferByte(0x91); // WRITE
  76. spiTransferByte(val&0xff); // 7-0
  77. spiTransferByte((val>>8)&0xff); // 15-8
  78. spiTransferByte((val>>16)&0xff); // 23-15
  79. spiTransferByte((val>>24)&0xff); // 31-24
  80. spiTransferByte(0x00); // dummy
  81. spi_none();
  82. }
  83. uint16_t sram_readshort(uint32_t addr) {
  84. set_avr_addr(addr);
  85. spi_fpga();
  86. spiTransferByte(0x81);
  87. spiTransferByte(0x00);
  88. uint32_t val = spiTransferByte(0x00);
  89. val |= ((uint32_t)spiTransferByte(0x00)<<8);
  90. spi_none();
  91. return val;
  92. }
  93. uint32_t sram_readlong(uint32_t addr) {
  94. set_avr_addr(addr);
  95. spi_fpga();
  96. spiTransferByte(0x81);
  97. spiTransferByte(0x00);
  98. uint32_t count=0;
  99. uint32_t val = spiTransferByte(count & 0xff);
  100. count++;
  101. val |= ((uint32_t)spiTransferByte(count & val)<<8);
  102. count++;
  103. val |= ((uint32_t)spiTransferByte(count & val)<<16);
  104. count++;
  105. val |= ((uint32_t)spiTransferByte(count & val)<<24);
  106. count++;
  107. spi_none();
  108. return val;
  109. }
  110. void sram_readblock(void* buf, uint32_t addr, uint16_t size) {
  111. uint16_t count=size;
  112. uint8_t* tgt = buf;
  113. set_avr_addr(addr);
  114. spi_fpga();
  115. spiTransferByte(0x81); // READ
  116. spiTransferByte(0x00); // dummy
  117. while(count--) {
  118. *(tgt++) = spiTransferByte(0x00);
  119. }
  120. spi_none();
  121. }
  122. void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
  123. uint16_t count=size;
  124. uint8_t* src = buf;
  125. set_avr_addr(addr);
  126. spi_fpga();
  127. spiTransferByte(0x91); // WRITE
  128. while(count--) {
  129. spiTransferByte(*src++);
  130. }
  131. spiTransferByte(0x00); // dummy
  132. spi_none();
  133. }
  134. uint32_t load_rom(uint8_t* filename, uint32_t base_addr) {
  135. // uint8_t dummy;
  136. UINT bytes_read;
  137. DWORD filesize;
  138. UINT count=0;
  139. file_open(filename, FA_READ);
  140. filesize = file_handle.fsize;
  141. smc_id(&romprops);
  142. set_avr_addr(base_addr);
  143. dprintf("no nervous breakdown beyond this point! or else!\n");
  144. if(file_res) {
  145. uart_putc('?');
  146. uart_putc(0x30+file_res);
  147. return 0;
  148. }
  149. f_lseek(&file_handle, romprops.offset);
  150. spi_none();
  151. for(;;) {
  152. SPI_OFFLOAD=1;
  153. spi_none();
  154. bytes_read = file_read();
  155. if (file_res || !bytes_read) break;
  156. if(!(count++ % 8)) {
  157. // toggle_busy_led();
  158. bounce_busy_led();
  159. uart_putc('.');
  160. }
  161. /* spi_fpga();
  162. spiTransferByte(0x91); // write w/ increment
  163. if(!(count++ % 8)) {
  164. // toggle_busy_led();
  165. bounce_busy_led();
  166. uart_putc('.');
  167. }
  168. for(int j=0; j<bytes_read; j++) {
  169. // spiTransferByte(file_buf[j]);
  170. SPDR = file_buf[j];
  171. loop_until_bit_is_set(SPSR, SPIF);
  172. dummy = SPDR;
  173. }
  174. spiTransferByte(0x00); // dummy tx for increment+write pulse */
  175. }
  176. file_close();
  177. spi_none();
  178. set_avr_mapper(romprops.mapper_id);
  179. uart_puthex(romprops.header.map);
  180. uart_putc(0x30+romprops.mapper_id);
  181. uint32_t rammask;
  182. uint32_t rommask;
  183. if(filesize > (romprops.romsize_bytes + romprops.offset)) {
  184. romprops.romsize_bytes <<= 1;
  185. }
  186. if(romprops.header.ramsize == 0) {
  187. rammask = 0;
  188. } else {
  189. rammask = romprops.ramsize_bytes - 1;
  190. }
  191. rommask = romprops.romsize_bytes - 1;
  192. uart_putc(' ');
  193. uart_puthex(romprops.header.ramsize);
  194. uart_putc('-');
  195. uart_puthexlong(rammask);
  196. uart_putc(' ');
  197. uart_puthex(romprops.header.romsize);
  198. uart_putc('-');
  199. uart_puthexlong(rommask);
  200. set_saveram_mask(rammask);
  201. set_rom_mask(rommask);
  202. return (uint32_t)filesize;
  203. }
  204. uint32_t load_sram(uint8_t* filename, uint32_t base_addr) {
  205. set_avr_addr(base_addr);
  206. UINT bytes_read;
  207. DWORD filesize;
  208. file_open(filename, FA_READ);
  209. filesize = file_handle.fsize;
  210. if(file_res) return 0;
  211. for(;;) {
  212. // FPGA_SS_HIGH();
  213. // SPI_SS_LOW();
  214. SPI_OFFLOAD=1;
  215. bytes_read = file_read();
  216. // SPI_SS_HIGH();
  217. if (file_res || !bytes_read) break;
  218. // FPGA_SS_LOW();
  219. /* spiTransferByte(0x91);
  220. for(int j=0; j<bytes_read; j++) {
  221. spiTransferByte(file_buf[j]);
  222. }
  223. spiTransferByte(0x00); // dummy tx
  224. FPGA_SS_HIGH(); // */
  225. }
  226. file_close();
  227. return (uint32_t)filesize;
  228. }
  229. void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
  230. uint32_t count = 0;
  231. uint32_t num = 0;
  232. spi_none();
  233. file_open(filename, FA_CREATE_ALWAYS | FA_WRITE);
  234. if(file_res) {
  235. uart_putc(0x30+file_res);
  236. }
  237. while(count<sram_size) {
  238. set_avr_addr(base_addr+count);
  239. spi_fpga();
  240. spiTransferByte(0x81); // read
  241. spiTransferByte(0); // dummy
  242. for(int j=0; j<sizeof(file_buf); j++) {
  243. file_buf[j] = spiTransferByte(0x00);
  244. count++;
  245. }
  246. spi_none();
  247. num = file_write();
  248. if(file_res) {
  249. uart_putc(0x30+file_res);
  250. }
  251. }
  252. file_close();
  253. }
  254. uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size) {
  255. uint8_t data;
  256. uint32_t count;
  257. uint16_t crc;
  258. crc=0;
  259. crc_valid=1;
  260. set_avr_addr(base_addr);
  261. spi_fpga();
  262. spiTransferByte(0x81);
  263. spiTransferByte(0x00);
  264. for(count=0; count<size; count++) {
  265. data = spiTransferByte(0);
  266. if(get_snes_reset()) {
  267. crc_valid = 0;
  268. break;
  269. }
  270. crc += crc16_update(crc, &data, 1);
  271. }
  272. spi_none();
  273. return crc;
  274. }
  275. uint8_t sram_reliable() {
  276. uint16_t score=0;
  277. uint32_t val;
  278. // uint32_t val = sram_readlong(SRAM_SCRATCHPAD);
  279. uint8_t result = 0;
  280. /* while(score<SRAM_RELIABILITY_SCORE) {
  281. if(sram_readlong(SRAM_SCRATCHPAD)==val) {
  282. score++;
  283. } else {
  284. set_pwr_led(0);
  285. score=0;
  286. }
  287. }*/
  288. for(uint16_t i = 0; i < SRAM_RELIABILITY_SCORE; i++) {
  289. val=sram_readlong(SRAM_SCRATCHPAD);
  290. if(val==0x12345678) {
  291. score++;
  292. // } else {
  293. // dprintf("i=%d val=%08lX\n", i, val);
  294. }
  295. }
  296. if(score<SRAM_RELIABILITY_SCORE) {
  297. result = 0;
  298. // dprintf("score=%d\n", score);
  299. } else {
  300. result = 1;
  301. }
  302. set_pwr_led(result);
  303. return result;
  304. }