fpga.c 4.0 KB

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  1. /* sd2snes - SD card based universal cartridge for the SNES
  2. Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
  3. AVR firmware portion
  4. Inspired by and based on code from sd2iec, written by Ingo Korb et al.
  5. See sdcard.c|h, config.h.
  6. FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
  7. see ff.c|h.
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; version 2 of the License only.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. fpga.c: FPGA (re)configuration
  19. */
  20. /*
  21. FPGA pin mapping
  22. ================
  23. PROG_B PD3 OUT
  24. CCLK PD4 OUT
  25. INIT_B PD7 IN
  26. DIN PC7 OUT
  27. DONE PA3 IN
  28. */
  29. #include <avr/pgmspace.h>
  30. #include <util/delay.h>
  31. #include "fpga.h"
  32. #include "config.h"
  33. #include "uart.h"
  34. #include "sdcard.h"
  35. #include "diskio.h"
  36. #include "integer.h"
  37. #include "ff.h"
  38. #include "fileops.h"
  39. #include "fpga_spi.h"
  40. #include "spi.h"
  41. #include "avrcompat.h"
  42. #include "led.h"
  43. /*DWORD get_fattime(void) {
  44. return 0L;
  45. }*/
  46. void set_prog_b(uint8_t val) {
  47. if(val) {
  48. PORTD |= _BV(PD3);
  49. } else {
  50. PORTD &= ~_BV(PD3);
  51. }
  52. }
  53. void set_cclk(uint8_t val) {
  54. if(val) {
  55. PORTD |= _BV(PD4);
  56. } else {
  57. PORTD &= ~_BV(PD4);
  58. }
  59. }
  60. void fpga_init() {
  61. DDRD &= ~_BV(PD7); // PD7 is input
  62. DDRC = _BV(PC7); // for FPGA config, PC7 is output
  63. DDRD |= _BV(PD3) | _BV(PD4); // PD3, PD4 are outputs
  64. DDRA = ~_BV(PA3); // PA3 is input <- DONE
  65. DDRB |= _BV(PB2); // DMA_CTRL preinit
  66. PORTB |= _BV(PB2);
  67. SPI_OFFLOAD=0;
  68. set_cclk(0); // initial clk=0
  69. }
  70. int fpga_get_done(void) {
  71. return PINA & _BV(PA3);
  72. }
  73. void fpga_postinit() {
  74. DDRA |= _BV(PA0) | _BV(PA1) | _BV(PA2) | _BV(PA4) | _BV(PA5) | _BV(PA6); // MAPPER+NEXTADDR output
  75. DDRB |= _BV(PB1) | _BV(PB0); // turn PB2 into output, enable AVR_BANK
  76. DDRD |= _BV(PD7); // turn PD7 into output
  77. }
  78. void fpga_pgm(uint8_t* filename) {
  79. int MAXRETRIES = 10;
  80. int retries = MAXRETRIES;
  81. int j=0;
  82. do {
  83. set_prog_b(0);
  84. uart_putc('P');
  85. set_prog_b(1);
  86. loop_until_bit_is_set(PIND, PD7);
  87. uart_putc('p');
  88. UINT bytes_read;
  89. // open configware file
  90. file_open(filename, FA_READ);
  91. if(file_res) {
  92. uart_putc('?');
  93. uart_putc(0x30+file_res);
  94. return;
  95. }
  96. for (;;) {
  97. if(!(j++ % 8)) {
  98. toggle_pwr_led();
  99. }
  100. bytes_read = file_read();
  101. if (file_res || bytes_read == 0) break; // error or eof
  102. for(int i=0; i<bytes_read; i++) {
  103. FPGA_SEND_BYTE_SERIAL(file_buf[i]);
  104. }
  105. }
  106. file_close();
  107. _delay_ms(100);
  108. } while (!fpga_get_done() && retries--);
  109. if(!fpga_get_done()) {
  110. dprintf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
  111. _delay_ms(50);
  112. led_panic();
  113. }
  114. fpga_postinit();
  115. }
  116. void set_avr_ena(uint8_t val) {
  117. if(val) { // shared mode
  118. PORTD |= _BV(PD7);
  119. // Disable SPI double speed mode -> clock = f/4
  120. SPSR = 0;
  121. dprintf("SPI slow\n");
  122. } else { // avr only
  123. PORTD &= ~_BV(PD7);
  124. // Enable SPI double speed mode -> clock = f/2
  125. SPSR = _BV(SPI2X);
  126. dprintf("SPI fast\n");
  127. }
  128. }
  129. void set_avr_mapper(uint8_t val) {
  130. SPI_SS_HIGH();
  131. FPGA_SS_LOW();
  132. spiTransferByte(0x30 | (val & 0x0f));
  133. FPGA_SS_HIGH();
  134. SPI_SS_LOW();
  135. }
  136. void set_avr_bank(uint8_t val) {
  137. SPI_SS_HIGH();
  138. FPGA_SS_LOW();
  139. spiTransferByte(0x00); // SET ADDRESS
  140. spiTransferByte(val * 0x20); // select chip
  141. spiTransferByte(0x00); // select chip
  142. spiTransferByte(0x00); // select chip
  143. FPGA_SS_HIGH();
  144. SPI_SS_LOW();
  145. }
  146. uint8_t fpga_test() {
  147. spi_fpga();
  148. spiTransferByte(0xF0); // TEST
  149. spiTransferByte(0x00); // dummy
  150. uint8_t result = spiTransferByte(0x00);
  151. spi_none();
  152. return result;
  153. }