config.h 2.7 KB

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  1. #ifndef _CONFIG_H
  2. #define _CONFIG_H
  3. #include "autoconf.h"
  4. // #define DEBUG_FS
  5. // #define DEBUG_SD
  6. // #define DEBUG_IRQ
  7. // #define DEBUG_MSU1
  8. #define IN_AHBRAM __attribute__ ((section(".ahbram")))
  9. #define SD_DT_INT_SETUP() do {\
  10. BITBAND(LPC_GPIOINT->IO2IntEnR, SD_DT_BIT) = 1;\
  11. BITBAND(LPC_GPIOINT->IO2IntEnF, SD_DT_BIT) = 1;\
  12. } while(0)
  13. #define SD_CHANGE_DETECT (BITBAND(LPC_GPIOINT->IO2IntStatR, SD_DT_BIT)\
  14. |BITBAND(LPC_GPIOINT->IO2IntStatF, SD_DT_BIT))
  15. #define SD_CHANGE_CLR() do {LPC_GPIOINT->IO2IntClr = BV(SD_DT_BIT);} while(0)
  16. #define SD_DT_REG LPC_GPIO0
  17. #define SD_DT_BIT 8
  18. #define SD_WP_REG LPC_GPIO0
  19. #define SD_WP_BIT 6
  20. #define SDCARD_DETECT (!(BITBAND(SD_DT_REG->FIOPIN, SD_DT_BIT)))
  21. #define SDCARD_WP (BITBAND(SD_WP_REG->FIOPIN, SD_WP_BIT))
  22. #define SD_SUPPLY_VOLTAGE (1L<<21) /* 3.3V - 3.4V */
  23. #define CONFIG_SD_BLOCKTRANSFER 1
  24. #define CONFIG_SD_AUTO_RETRIES 10
  25. // #define SD_CHANGE_VECT
  26. // #define CONFIG_SD_DATACRC 1
  27. #define CONFIG_UART_NUM 3
  28. // #define CONFIG_CPU_FREQUENCY 90315789
  29. #define CONFIG_CPU_FREQUENCY 88000000
  30. //#define CONFIG_CPU_FREQUENCY 46000000
  31. #define CONFIG_UART_PCLKDIV 1
  32. #define CONFIG_UART_TX_BUF_SHIFT 8
  33. //#define CONFIG_UART_BAUDRATE 921600
  34. #define CONFIG_UART_BAUDRATE 115200
  35. #define CONFIG_UART_DEADLOCKABLE
  36. #define SSP_CLK_DIVISOR 2
  37. #define SNES_RESET_REG LPC_GPIO1
  38. #define SNES_RESET_BIT 26
  39. #define SNES_CIC_D0_REG LPC_GPIO0
  40. #define SNES_CIC_D0_BIT 1
  41. #define SNES_CIC_D1_REG LPC_GPIO0
  42. #define SNES_CIC_D1_BIT 0
  43. #define SNES_CIC_STATUS_REG LPC_GPIO1
  44. #define SNES_CIC_STATUS_BIT 29
  45. #define SNES_CIC_PAIR_REG LPC_GPIO1
  46. #define SNES_CIC_PAIR_BIT 25
  47. #define FPGA_MCU_RDY_REG LPC_GPIO2
  48. #define FPGA_MCU_RDY_BIT 9
  49. #define QSORT_MAXELEM 2048
  50. #define CLTBL_SIZE 100
  51. #define DIR_FILE_MAX 16380
  52. #define SSP_REGS LPC_SSP0
  53. #define SSP_PCLKREG PCLKSEL1
  54. // 1: PCLKSEL0
  55. #define SSP_PCLKBIT 10
  56. // 1: 20
  57. #define SSP_DMAID_TX 0
  58. // 1: 2
  59. #define SSP_DMAID_RX 1
  60. // 1: 3
  61. #define SSP_DMACH LPC_GPDMACH0
  62. #define SD_CLKREG LPC_GPIO0
  63. #define SD_CMDREG LPC_GPIO0
  64. #define SD_DAT0REG LPC_GPIO2
  65. #define SD_DAT1REG LPC_GPIO2
  66. #define SD_DAT2REG LPC_GPIO2
  67. #define SD_DAT3REG LPC_GPIO2
  68. #define SD_CLKPIN (7)
  69. #define SD_CMDPIN (9)
  70. #define SD_DAT0PIN (0)
  71. #define SD_DAT1PIN (1)
  72. #define SD_DAT2PIN (2)
  73. #define SD_DAT3PIN (3)
  74. #define SD_DAT (LPC_GPIO2->FIOPIN0)
  75. #endif