spi.v 3.5 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 21:16:09 07/10/2009
  7. // Design Name:
  8. // Module Name: spi
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module spi(
  22. input clk,
  23. input SCK,
  24. input MOSI,
  25. inout MISO,
  26. input SSEL,
  27. output cmd_ready,
  28. output param_ready,
  29. output [7:0] cmd_data,
  30. output [7:0] param_data,
  31. output endmessage,
  32. output startmessage,
  33. input [7:0] input_data,
  34. output [31:0] byte_cnt,
  35. output [2:0] bit_cnt
  36. );
  37. reg [7:0] cmd_data_r;
  38. reg [7:0] param_data_r;
  39. // sync SCK to the FPGA clock using a 3-bits shift register
  40. reg [2:0] SCKr;
  41. always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
  42. wire SCK_risingedge = (SCKr[1:0]==2'b01); // now we can detect SCK rising edges
  43. wire SCK_fallingedge = (SCKr[1:0]==2'b10); // and falling edges
  44. // same thing for SSEL
  45. reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
  46. wire SSEL_active = ~SSELr[1]; // SSEL is active low
  47. wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge
  48. wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge
  49. assign endmessage = SSEL_endmessage;
  50. assign startmessage = SSEL_startmessage;
  51. // and for MOSI
  52. reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0], MOSI};
  53. wire MOSI_data = MOSIr[0];
  54. // bit count for one SPI byte + byte count for the message
  55. reg [2:0] bitcnt;
  56. reg [31:0] byte_cnt_r;
  57. reg byte_received; // high when a byte has been received
  58. reg [7:0] byte_data_received;
  59. assign bit_cnt = bitcnt;
  60. always @(posedge clk)
  61. begin
  62. if(~SSEL_active) begin
  63. bitcnt <= 3'b000;
  64. end
  65. else if(SCK_risingedge) begin
  66. bitcnt <= bitcnt + 3'b001;
  67. // shift received data into the register
  68. byte_data_received <= {byte_data_received[6:0], MOSI_data};
  69. end
  70. end
  71. always @(posedge clk)
  72. byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);
  73. always @(posedge clk) begin
  74. if(~SSEL_active)
  75. byte_cnt_r <= 16'h0000;
  76. else if(byte_received) begin
  77. byte_cnt_r <= byte_cnt_r + 16'h0001;
  78. end
  79. end
  80. reg [7:0] byte_data_sent;
  81. always @(posedge clk) begin
  82. if(SSEL_active) begin
  83. if(SSEL_startmessage)
  84. byte_data_sent <= 8'h5A; // dummy byte
  85. else
  86. if(SCK_fallingedge) begin
  87. if(bitcnt==3'b000)
  88. byte_data_sent <= input_data; // after that, we send whatever we get
  89. else
  90. byte_data_sent <= {byte_data_sent[6:0], 1'b0};
  91. end
  92. end
  93. end
  94. assign MISO = SSEL_active ? byte_data_sent[7] : 1'bZ; // send MSB first
  95. reg cmd_ready_r;
  96. reg param_ready_r;
  97. reg cmd_ready_r2;
  98. reg param_ready_r2;
  99. assign cmd_ready = cmd_ready_r;
  100. assign param_ready = param_ready_r;
  101. assign cmd_data = cmd_data_r;
  102. assign param_data = param_data_r;
  103. assign byte_cnt = byte_cnt_r;
  104. always @(posedge clk) cmd_ready_r2 = byte_received && byte_cnt_r == 32'h0;
  105. always @(posedge clk) param_ready_r2 = byte_received && byte_cnt_r > 32'h0;
  106. // fill registers
  107. always @(posedge clk) begin
  108. if (SSEL_startmessage)
  109. cmd_data_r <= 8'h00;
  110. else if(cmd_ready_r2)
  111. cmd_data_r <= byte_data_received;
  112. else if(param_ready_r2)
  113. param_data_r <= byte_data_received;
  114. end
  115. // delay ready signals by one clock (why did I do this again...)
  116. always @(posedge clk) begin
  117. cmd_ready_r <= cmd_ready_r2;
  118. param_ready_r <= param_ready_r2;
  119. end
  120. endmodule