main.v 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653
  1. `timescale 1 ns / 1 ns
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: Rehkopf
  4. // Engineer: Rehkopf
  5. //
  6. // Create Date: 01:13:46 05/09/2009
  7. // Design Name:
  8. // Module Name: main
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description: Master Control FSM
  13. //
  14. // Dependencies: address
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module main(
  22. /* input clock */
  23. input CLKIN,
  24. /* SNES signals */
  25. input [23:0] SNES_ADDR,
  26. input SNES_READ,
  27. input SNES_WRITE,
  28. input SNES_CS,
  29. inout [7:0] SNES_DATA,
  30. input SNES_CPU_CLK,
  31. input SNES_REFRESH,
  32. inout SNES_IRQ,
  33. output SNES_DATABUS_OE,
  34. output SNES_DATABUS_DIR,
  35. output IRQ_DIR,
  36. input SNES_SYSCLK,
  37. /* SRAM signals */
  38. /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
  39. inout [15:0] ROM_DATA,
  40. output [22:0] ROM_ADDR,
  41. output ROM_CE,
  42. output ROM_OE,
  43. output ROM_WE,
  44. output ROM_BHE,
  45. output ROM_BLE,
  46. /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
  47. inout [7:0] RAM_DATA,
  48. output [18:0] RAM_ADDR,
  49. output RAM_CE,
  50. output RAM_OE,
  51. output RAM_WE,
  52. /* MCU signals */
  53. input SPI_MOSI,
  54. inout SPI_MISO,
  55. input SPI_SS,
  56. inout SPI_SCK,
  57. input MCU_OVR,
  58. output DAC_MCLK,
  59. output DAC_LRCK,
  60. output DAC_SDOUT,
  61. /* SD signals */
  62. input [3:0] SD_DAT,
  63. inout SD_CMD,
  64. inout SD_CLK
  65. /* debug */
  66. ,
  67. output p113_out
  68. );
  69. wire dspx_dp_enable;
  70. assign p113_out = dspx_dp_enable;
  71. wire [7:0] spi_cmd_data;
  72. wire [7:0] spi_param_data;
  73. wire [7:0] spi_input_data;
  74. wire [31:0] spi_byte_cnt;
  75. wire [2:0] spi_bit_cnt;
  76. wire [23:0] MCU_ADDR;
  77. wire [7:0] mcu_data_in;
  78. wire [7:0] mcu_data_out;
  79. wire [7:0] MCU_IN_DATA;
  80. wire [7:0] MCU_OUT_DATA;
  81. wire [3:0] MAPPER;
  82. wire [23:0] SAVERAM_MASK;
  83. wire [23:0] ROM_MASK;
  84. wire [7:0] SD_DMA_SRAM_DATA;
  85. wire [1:0] SD_DMA_TGT;
  86. wire [10:0] SD_DMA_PARTIAL_START;
  87. wire [10:0] SD_DMA_PARTIAL_END;
  88. wire [10:0] dac_addr;
  89. //wire [7:0] dac_volume;
  90. wire [7:0] msu_volumerq_out;
  91. wire [6:0] msu_status_out;
  92. wire [31:0] msu_addressrq_out;
  93. wire [15:0] msu_trackrq_out;
  94. wire [13:0] msu_write_addr;
  95. wire [13:0] msu_ptr_addr;
  96. wire [7:0] MSU_SNES_DATA_IN;
  97. wire [7:0] MSU_SNES_DATA_OUT;
  98. wire [5:0] msu_status_reset_bits;
  99. wire [5:0] msu_status_set_bits;
  100. wire [14:0] bsx_regs;
  101. wire [14:0] bsx_regs_in;
  102. wire [7:0] BSX_SNES_DATA_IN;
  103. wire [7:0] BSX_SNES_DATA_OUT;
  104. wire [7:0] bsx_regs_reset_bits;
  105. wire [7:0] bsx_regs_set_bits;
  106. wire [59:0] rtc_data;
  107. wire [59:0] rtc_data_in;
  108. wire [59:0] srtc_rtc_data_out;
  109. wire [7:0] SRTC_SNES_DATA_IN;
  110. wire [7:0] SRTC_SNES_DATA_OUT;
  111. wire [7:0] DSPX_SNES_DATA_IN;
  112. wire [7:0] DSPX_SNES_DATA_OUT;
  113. wire [23:0] dspx_pgm_data;
  114. wire [10:0] dspx_pgm_addr;
  115. wire dspx_pgm_we;
  116. wire [15:0] dspx_dat_data;
  117. wire [10:0] dspx_dat_addr;
  118. wire dspx_dat_we;
  119. wire [7:0] featurebits;
  120. //wire SD_DMA_EN; //SPI_DMA_CTRL;
  121. sd_dma snes_sd_dma(
  122. .CLK(CLK2),
  123. .SD_DAT(SD_DAT),
  124. .SD_CLK(SD_CLK),
  125. .SD_DMA_EN(SD_DMA_EN),
  126. .SD_DMA_STATUS(SD_DMA_STATUS),
  127. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  128. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  129. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  130. .SD_DMA_TGT(SD_DMA_TGT),
  131. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  132. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  133. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
  134. );
  135. dac snes_dac(
  136. .clkin(CLK2),
  137. .sysclk(SNES_SYSCLK),
  138. .mclk(DAC_MCLK),
  139. .lrck(DAC_LRCK),
  140. .sdout(DAC_SDOUT),
  141. .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
  142. .pgm_address(dac_addr),
  143. .pgm_data(SD_DMA_SRAM_DATA),
  144. .DAC_STATUS(DAC_STATUS),
  145. .volume(msu_volumerq_out),
  146. .vol_latch(msu_volume_latch_out),
  147. .play(dac_play),
  148. .reset(dac_reset)
  149. );
  150. srtc snes_srtc (
  151. .clkin(CLK2),
  152. /*XXX*/.reg_addr(srtc_reg_addr),
  153. .addr_in(SNES_ADDR[0]),
  154. .data_in(SRTC_SNES_DATA_IN),
  155. .data_out(SRTC_SNES_DATA_OUT),
  156. .rtc_data_in(rtc_data),
  157. .reg_we(SNES_WRITE),
  158. .reg_oe(SNES_READ),
  159. .enable(srtc_enable),
  160. .rtc_data_out(srtc_rtc_data_out),
  161. .rtc_we(srtc_rtc_we),
  162. .reset(srtc_reset)
  163. );
  164. rtc snes_rtc (
  165. .clkin(CLKIN),
  166. .rtc_data(rtc_data),
  167. .rtc_data_in(rtc_data_in),
  168. .pgm_we(rtc_pgm_we),
  169. .rtc_data_in1(srtc_rtc_data_out),
  170. .we1(srtc_rtc_we)
  171. );
  172. msu snes_msu (
  173. .clkin(CLK2),
  174. .enable(msu_enable),
  175. .pgm_address(msu_write_addr),
  176. .pgm_data(SD_DMA_SRAM_DATA),
  177. .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
  178. .reg_addr(SNES_ADDR),
  179. .reg_data_in(MSU_SNES_DATA_IN),
  180. .reg_data_out(MSU_SNES_DATA_OUT),
  181. .reg_oe(SNES_READ),
  182. .reg_we(SNES_WRITE),
  183. .status_out(msu_status_out),
  184. .volume_out(msu_volumerq_out),
  185. .volume_latch_out(msu_volume_latch_out),
  186. .addr_out(msu_addressrq_out),
  187. .track_out(msu_trackrq_out),
  188. .status_reset_bits(msu_status_reset_bits),
  189. .status_set_bits(msu_status_set_bits),
  190. .status_reset_we(msu_status_reset_we),
  191. .msu_address_ext(msu_ptr_addr),
  192. .msu_address_ext_write(msu_addr_reset)
  193. );
  194. bsx snes_bsx(
  195. .clkin(CLK2),
  196. .use_bsx(use_bsx),
  197. .pgm_we(bsx_regs_reset_we),
  198. .snes_addr(SNES_ADDR),
  199. .reg_data_in(BSX_SNES_DATA_IN),
  200. .reg_data_out(BSX_SNES_DATA_OUT),
  201. .reg_oe(SNES_READ),
  202. .reg_we(SNES_WRITE),
  203. .regs_out(bsx_regs),
  204. .reg_reset_bits(bsx_regs_reset_bits),
  205. .reg_set_bits(bsx_regs_set_bits),
  206. .data_ovr(bsx_data_ovr),
  207. .flash_writable(IS_FLASHWR),
  208. .rtc_data(rtc_data)
  209. );
  210. spi snes_spi(
  211. .clk(CLK2),
  212. .MOSI(SPI_MOSI),
  213. .MISO(SPI_MISO),
  214. .SSEL(SPI_SS),
  215. .SCK(SPI_SCK),
  216. .cmd_ready(spi_cmd_ready),
  217. .param_ready(spi_param_ready),
  218. .cmd_data(spi_cmd_data),
  219. .param_data(spi_param_data),
  220. .endmessage(spi_endmessage),
  221. .startmessage(spi_startmessage),
  222. .input_data(spi_input_data),
  223. .byte_cnt(spi_byte_cnt),
  224. .bit_cnt(spi_bit_cnt)
  225. );
  226. upd77c25 snes_dspx (
  227. .DI(DSPX_SNES_DATA_IN),
  228. .DO(DSPX_SNES_DATA_OUT),
  229. .A0(DSPX_A0),
  230. .nCS(~dspx_enable),
  231. .nRD(SNES_READ),
  232. .nWR(SNES_WRITE),
  233. .RST(~dspx_reset),
  234. .CLK(CLK2),
  235. .PGM_WR(dspx_pgm_we),
  236. .PGM_DI(dspx_pgm_data),
  237. .PGM_WR_ADDR(dspx_pgm_addr),
  238. .DAT_WR(dspx_dat_we),
  239. .DAT_DI(dspx_dat_data),
  240. .DAT_WR_ADDR(dspx_dat_addr),
  241. .DP_nCS(~dspx_dp_enable),
  242. .DP_ADDR(SNES_ADDR[10:0])
  243. );
  244. mcu_cmd snes_mcu_cmd(
  245. .clk(CLK2),
  246. .snes_sysclk(SNES_SYSCLK),
  247. .cmd_ready(spi_cmd_ready),
  248. .param_ready(spi_param_ready),
  249. .cmd_data(spi_cmd_data),
  250. .param_data(spi_param_data),
  251. .mcu_mapper(MAPPER),
  252. .mcu_sram_size(SRAM_SIZE),
  253. .mcu_read(MCU_READ),
  254. .mcu_write(MCU_WRITE),
  255. .mcu_data_in(MCU_OUT_DATA),
  256. .mcu_data_out(MCU_IN_DATA),
  257. .spi_byte_cnt(spi_byte_cnt),
  258. .spi_bit_cnt(spi_bit_cnt),
  259. .spi_data_out(spi_input_data),
  260. .addr_out(MCU_ADDR),
  261. .endmessage(spi_endmessage),
  262. .startmessage(spi_startmessage),
  263. .saveram_mask_out(SAVERAM_MASK),
  264. .rom_mask_out(ROM_MASK),
  265. .SD_DMA_EN(SD_DMA_EN),
  266. .SD_DMA_STATUS(SD_DMA_STATUS),
  267. .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
  268. .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
  269. .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
  270. .SD_DMA_TGT(SD_DMA_TGT),
  271. .SD_DMA_PARTIAL(SD_DMA_PARTIAL),
  272. .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
  273. .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
  274. .dac_addr_out(dac_addr),
  275. .DAC_STATUS(DAC_STATUS),
  276. // .dac_volume_out(dac_volume),
  277. // .dac_volume_latch_out(dac_vol_latch),
  278. .dac_play_out(dac_play),
  279. .dac_reset_out(dac_reset),
  280. .msu_addr_out(msu_write_addr),
  281. .MSU_STATUS(msu_status_out),
  282. .msu_status_reset_out(msu_status_reset_bits),
  283. .msu_status_set_out(msu_status_set_bits),
  284. .msu_status_reset_we(msu_status_reset_we),
  285. .msu_volumerq(msu_volumerq_out),
  286. .msu_addressrq(msu_addressrq_out),
  287. .msu_trackrq(msu_trackrq_out),
  288. .msu_ptr_out(msu_ptr_addr),
  289. .msu_reset_out(msu_addr_reset),
  290. .bsx_regs_set_out(bsx_regs_set_bits),
  291. .bsx_regs_reset_out(bsx_regs_reset_bits),
  292. .bsx_regs_reset_we(bsx_regs_reset_we),
  293. .rtc_data_out(rtc_data_in),
  294. .rtc_pgm_we(rtc_pgm_we),
  295. .srtc_reset(srtc_reset),
  296. .dspx_pgm_data_out(dspx_pgm_data),
  297. .dspx_pgm_addr_out(dspx_pgm_addr),
  298. .dspx_pgm_we_out(dspx_pgm_we),
  299. .dspx_dat_data_out(dspx_dat_data),
  300. .dspx_dat_addr_out(dspx_dat_addr),
  301. .dspx_dat_we_out(dspx_dat_we),
  302. .dspx_reset_out(dspx_reset),
  303. .featurebits_out(featurebits)
  304. );
  305. // dcm1: dfs 4x
  306. my_dcm snes_dcm(
  307. .CLKIN(CLKIN),
  308. .CLKFX(CLK2),
  309. .LOCKED(DCM_LOCKED),
  310. .RST(DCM_RST),
  311. .STATUS(DCM_STATUS)
  312. );
  313. assign DCM_RST=0;
  314. wire SNES_RW;
  315. reg [1:0] SNES_READr;
  316. reg [1:0] SNES_WRITEr;
  317. reg [1:0] SNES_CSr;
  318. reg [5:0] SNES_CPU_CLKr;
  319. reg [5:0] SNES_RWr;
  320. reg [23:0] SNES_ADDRr;
  321. reg [23:0] SNES_ADDR_PREVr;
  322. reg [3:0] SNES_ADDRCHGr;
  323. wire SNES_READs = (SNES_READr == 2'b11);
  324. wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
  325. wire SNES_CSs = (SNES_CSr == 2'b11);
  326. wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
  327. wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
  328. wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000011);
  329. wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
  330. wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
  331. assign SNES_RW = (SNES_READ & SNES_WRITE);
  332. always @(posedge CLK2) begin
  333. SNES_READr <= {SNES_READr[0], SNES_READ};
  334. SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
  335. SNES_CSr <= {SNES_CSr[0], SNES_CS};
  336. SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
  337. SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
  338. end
  339. reg ADDR_WRITE;
  340. wire ROM_SEL;
  341. address snes_addr(
  342. .CLK(CLK2),
  343. .MAPPER(MAPPER),
  344. .featurebits(featurebits),
  345. .SNES_ADDR(SNES_ADDR), // requested address from SNES
  346. .SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
  347. .ROM_ADDR(ROM_ADDR), // Address to request from SRAM (active low)
  348. .ROM_SEL(ROM_SEL), // which SRAM unit to access
  349. .MCU_OVR(MCU_OVR), // enable MCU mode (active low)
  350. .MODE(MODE), // MCU(1) or SNES(0) ("bus phase")
  351. .IS_SAVERAM(IS_SAVERAM),
  352. .IS_ROM(IS_ROM),
  353. .IS_WRITABLE(IS_WRITABLE),
  354. .MCU_ADDR(MCU_ADDR),
  355. .ROM_ADDR0(ROM_ADDR0),
  356. .SAVERAM_MASK(SAVERAM_MASK),
  357. .ROM_MASK(ROM_MASK),
  358. //MSU-1
  359. .use_msu(use_msu),
  360. .msu_enable(msu_enable),
  361. //BS-X
  362. .use_bsx(use_bsx),
  363. .bsx_regs(bsx_regs),
  364. //SRTC
  365. .srtc_enable(srtc_enable),
  366. //uPD77C25
  367. .dspx_enable(dspx_enable),
  368. .dspx_dp_enable(dspx_dp_enable),
  369. .dspx_a0(DSPX_A0)
  370. );
  371. wire SNES_READ_CYCLEw;
  372. wire SNES_WRITE_CYCLEw;
  373. wire MCU_READ_CYCLEw;
  374. wire MCU_WRITE_CYCLEw;
  375. data snes_data(
  376. .CLK(CLK2),
  377. .SNES_READ(SNES_READ),
  378. .SNES_WRITE(SNES_WRITE),
  379. .MCU_READ(MCU_READ),
  380. .MCU_WRITE(MCU_WRITE),
  381. .SNES_DATA(SNES_DATA),
  382. .ROM_DATA(ROM_DATA),
  383. .MODE(MODE),
  384. .SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
  385. .MCU_DATA_TO_MEM(MCU_DATA_TO_MEM),
  386. .ROM_DATA_TO_SNES_MEM(ROM_DATA_TO_SNES_MEM),
  387. .ROM_DATA_TO_MCU_MEM(ROM_DATA_TO_MCU_MEM),
  388. .MCU_OVR(MCU_OVR),
  389. .MCU_IN_DATA(MCU_IN_DATA),
  390. .MCU_OUT_DATA(MCU_OUT_DATA),
  391. .ROM_ADDR0(ROM_ADDR0),
  392. .MSU_DATA_IN(MSU_SNES_DATA_IN),
  393. .MSU_DATA_OUT(MSU_SNES_DATA_OUT),
  394. .BSX_DATA_IN(BSX_SNES_DATA_IN),
  395. .BSX_DATA_OUT(BSX_SNES_DATA_OUT),
  396. .SRTC_DATA_IN(SRTC_SNES_DATA_IN),
  397. .SRTC_DATA_OUT(SRTC_SNES_DATA_OUT),
  398. .DSPX_DATA_IN(DSPX_SNES_DATA_IN),
  399. .DSPX_DATA_OUT(DSPX_SNES_DATA_OUT),
  400. .msu_enable(msu_enable),
  401. .bsx_data_ovr(bsx_data_ovr),
  402. .srtc_enable(srtc_enable),
  403. .dspx_enable(dspx_enable),
  404. .dspx_dp_enable(dspx_dp_enable)
  405. );
  406. parameter MODE_SNES = 1'b0;
  407. parameter MODE_MCU = 1'b1;
  408. parameter STATE_0 = 14'b00000000000001;
  409. parameter STATE_1 = 14'b00000000000010;
  410. parameter STATE_2 = 14'b00000000000100;
  411. parameter STATE_3 = 14'b00000000001000;
  412. parameter STATE_4 = 14'b00000000010000;
  413. parameter STATE_5 = 14'b00000000100000;
  414. parameter STATE_6 = 14'b00000001000000;
  415. parameter STATE_7 = 14'b00000010000000;
  416. parameter STATE_8 = 14'b00000100000000;
  417. parameter STATE_9 = 14'b00001000000000;
  418. parameter STATE_10 = 14'b00010000000000;
  419. parameter STATE_11 = 14'b00100000000000;
  420. parameter STATE_12 = 14'b01000000000000;
  421. parameter STATE_IDLE = 14'b10000000000000;
  422. reg [13:0] STATE;
  423. reg [3:0] STATEIDX;
  424. reg [1:0] CYCLE_RESET;
  425. reg ROM_WE_MASK;
  426. reg ROM_OE_MASK;
  427. reg [13:0] ROM_WE_ARRAY [3:0];
  428. reg [13:0] ROM_OE_ARRAY [3:0];
  429. reg [13:0] SNES_DATA_TO_MEM_ARRAY[1:0];
  430. reg [13:0] MCU_DATA_TO_MEM_ARRAY[1:0];
  431. reg [13:0] ROM_DATA_TO_SNES_MEM_ARRAY[1:0];
  432. reg [13:0] ROM_DATA_TO_MCU_MEM_ARRAY[1:0];
  433. reg [13:0] MODE_ARRAY;
  434. reg SNES_READ_CYCLE;
  435. reg SNES_WRITE_CYCLE;
  436. reg MCU_READ_CYCLE;
  437. reg MCU_WRITE_CYCLE;
  438. reg MCU_SPI_WRITEONCE;
  439. reg MCU_SPI_READONCE;
  440. reg MCU_SPI_WRITE;
  441. reg MCU_SPI_READ;
  442. reg MCU_SPI_ADDR_INCREMENT;
  443. reg [7:0] MCU_DATA_IN;
  444. reg [3:0] MAPPER_BUF;
  445. reg SNES_DATABUS_OE_BUF;
  446. reg SNES_DATABUS_DIR_BUF;
  447. assign MODE = !MCU_OVR ? MODE_MCU : MODE_ARRAY[STATEIDX];
  448. initial begin
  449. CYCLE_RESET = 2'b0;
  450. STATE = STATE_IDLE;
  451. STATEIDX = 13;
  452. ROM_WE_MASK = 1'b1;
  453. ROM_OE_MASK = 1'b1;
  454. SNES_READ_CYCLE = 1'b1;
  455. SNES_WRITE_CYCLE = 1'b1;
  456. MCU_READ_CYCLE = 1'b1;
  457. MCU_WRITE_CYCLE = 1'b1;
  458. MODE_ARRAY = 14'b0_000000_1111111;
  459. ROM_WE_ARRAY[2'b00] = 14'b1_000000_0000000;
  460. ROM_WE_ARRAY[2'b01] = 14'b1_000000_1111111;
  461. ROM_WE_ARRAY[2'b10] = 14'b1_111111_0000000;
  462. ROM_WE_ARRAY[2'b11] = 14'b1_111111_1111111;
  463. ROM_OE_ARRAY[2'b00] = 14'b1_111111_1111111;
  464. ROM_OE_ARRAY[2'b01] = 14'b1_111111_0000000;
  465. ROM_OE_ARRAY[2'b10] = 14'b0_000000_1111111;
  466. ROM_OE_ARRAY[2'b11] = 14'b0_000000_0000000;
  467. SNES_DATA_TO_MEM_ARRAY[1'b0] = 14'b0_000100_0000000; // SNES write
  468. SNES_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // SNES read
  469. MCU_DATA_TO_MEM_ARRAY[1'b0] = 14'b1_111111_1111111; // MCU write
  470. MCU_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // MCU read
  471. ROM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // SNES write
  472. ROM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 14'b0_000010_0000000; // SNES read
  473. ROM_DATA_TO_MCU_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // MCU write
  474. ROM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 14'b0_000000_0000001; // MCU read
  475. end
  476. // falling edge of SNES /RD or /WR marks the beginning of a new cycle
  477. // SNES READ or WRITE always starts @posedge CLK !!
  478. // CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy
  479. // the minimum of 6 SNES cycles to get everything done.
  480. // we have 24 internal cycles to work with. (CLKIN * 4)
  481. always @(posedge CLK2) begin
  482. CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start};
  483. end
  484. reg[7:0] STATECNT;
  485. initial STATECNT = 0;
  486. always @(posedge CLK2) begin
  487. MCU_READ_CYCLE <= MCU_READ;
  488. MCU_WRITE_CYCLE <= MCU_WRITE;
  489. if (SNES_cycle_start) begin
  490. SNES_READ_CYCLE <= SNES_READ;
  491. SNES_WRITE_CYCLE <= SNES_WRITE;
  492. STATE <= STATE_0;
  493. STATEIDX <= 12;
  494. STATECNT <= 0;
  495. end else begin
  496. STATECNT <= STATECNT + 1;
  497. case (STATE)
  498. STATE_0: begin
  499. SNES_WRITE_CYCLE <= SNES_WRITE;
  500. STATE <= STATE_1; STATEIDX <= 11;
  501. end
  502. STATE_1: begin
  503. STATE <= STATE_2; STATEIDX <= 10;
  504. end
  505. STATE_2: begin
  506. STATE <= STATE_3; STATEIDX <= 9;
  507. end
  508. STATE_3: begin
  509. STATE <= STATE_4; STATEIDX <= 8;
  510. end
  511. STATE_4: begin
  512. STATE <= STATE_5; STATEIDX <= 7;
  513. end
  514. STATE_5: begin
  515. STATE <= STATE_6; STATEIDX <= 6;
  516. end
  517. STATE_6: begin
  518. STATE <= STATE_7; STATEIDX <= 5;
  519. end
  520. STATE_7: begin
  521. STATE <= STATE_8; STATEIDX <= 4;
  522. end
  523. STATE_8: begin
  524. STATE <= STATE_9; STATEIDX <= 3;
  525. end
  526. STATE_9: begin
  527. STATE <= STATE_10; STATEIDX <= 2;
  528. end
  529. STATE_10: begin
  530. STATE <= STATE_11; STATEIDX <= 1;
  531. end
  532. STATE_11: begin
  533. STATE <= STATE_12; STATEIDX <= 0;
  534. end
  535. STATE_12: begin
  536. STATE <= STATE_IDLE; STATEIDX <= 13;
  537. end
  538. STATE_IDLE: begin
  539. STATE <= STATE_IDLE; STATEIDX <= 13;
  540. end
  541. default: begin
  542. STATE <= STATE_IDLE; STATEIDX <= 13;
  543. end
  544. endcase
  545. end
  546. end
  547. // When in MCU mode, enable SRAM_WE according to MCU programming
  548. // else enable SRAM_WE according to state&cycle
  549. assign ROM_WE = !MCU_OVR
  550. ?MCU_WRITE
  551. :((!IS_FLASHWR & !IS_WRITABLE & !MODE)
  552. | ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]);
  553. // When in MCU mode, enable SRAM_OE whenever not writing
  554. // else enable SRAM_OE according to state&cycle
  555. assign ROM_OE = !MCU_OVR
  556. ?MCU_READ
  557. :ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX];
  558. assign ROM_CE = 1'b0; // !MCU_OVR ? (MCU_READ & MCU_WRITE) : ROM_SEL;
  559. assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
  560. assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
  561. //assign SRAM_BHE = SRAM_ADDR0;
  562. //assign SRAM_BLE = ~SRAM_ADDR0;
  563. // dumb version
  564. //assign SRAM_OE = !MCU_ENA ? MCU_READ : SNES_READs;
  565. //assign SRAM_WE = !MCU_ENA ? MCU_WRITE : 1'b1;
  566. //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
  567. assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
  568. msu_enable ? 1'b0 :
  569. bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
  570. srtc_enable ? (SNES_READ & SNES_WRITE) :
  571. ((IS_ROM & SNES_CS)
  572. |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
  573. |(SNES_READ & SNES_WRITE)
  574. );
  575. assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
  576. assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
  577. assign MCU_DATA_TO_MEM = MCU_DATA_TO_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX];
  578. assign ROM_DATA_TO_SNES_MEM = ROM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
  579. assign ROM_DATA_TO_MCU_MEM = ROM_DATA_TO_MCU_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX];
  580. assign SNES_READ_CYCLEw = SNES_READ_CYCLE;
  581. assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
  582. assign IRQ_DIR = 1'b0;
  583. assign SNES_IRQ = 1'bZ;
  584. endmodule