data.v 2.9 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 23:03:06 05/13/2009
  7. // Design Name:
  8. // Module Name: data
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module data(
  22. input CLK,
  23. input SNES_READ,
  24. input SNES_WRITE,
  25. input MCU_READ,
  26. input MCU_WRITE,
  27. inout [7:0] SNES_DATA,
  28. inout [15:0] ROM_DATA,
  29. input [7:0] MCU_IN_DATA,
  30. output [7:0] MCU_OUT_DATA,
  31. input MODE,
  32. input SNES_DATA_TO_MEM,
  33. input MCU_DATA_TO_MEM,
  34. input ROM_DATA_TO_SNES_MEM,
  35. input ROM_DATA_TO_MCU_MEM,
  36. input MCU_OVR,
  37. input ROM_ADDR0,
  38. output [7:0] MSU_DATA_IN,
  39. input [7:0] MSU_DATA_OUT,
  40. output [7:0] BSX_DATA_IN,
  41. input [7:0] BSX_DATA_OUT,
  42. output [7:0] SRTC_DATA_IN,
  43. input [7:0] SRTC_DATA_OUT,
  44. output [7:0] DSPX_DATA_IN,
  45. input [7:0] DSPX_DATA_OUT,
  46. input msu_enable,
  47. input bsx_data_ovr,
  48. input srtc_enable,
  49. input dspx_enable,
  50. input dspx_dp_enable
  51. );
  52. reg [7:0] SNES_IN_MEM;
  53. reg [7:0] SNES_OUT_MEM;
  54. reg [7:0] MCU_IN_MEM;
  55. reg [7:0] MCU_OUT_MEM;
  56. wire [7:0] FROM_ROM_BYTE;
  57. assign MSU_DATA_IN = SNES_DATA;
  58. assign BSX_DATA_IN = SNES_DATA;
  59. assign SRTC_DATA_IN = SNES_DATA;
  60. assign DSPX_DATA_IN = SNES_DATA;
  61. assign SNES_DATA = SNES_READ ? 8'bZ
  62. :(!MCU_OVR ? 8'h00
  63. :(msu_enable ? MSU_DATA_OUT
  64. : bsx_data_ovr ? BSX_DATA_OUT
  65. : srtc_enable ? SRTC_DATA_OUT
  66. : dspx_enable ? DSPX_DATA_OUT
  67. : dspx_dp_enable ? DSPX_DATA_OUT
  68. : SNES_OUT_MEM)
  69. );
  70. assign FROM_ROM_BYTE = (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
  71. assign MCU_OUT_DATA = !MCU_OVR ? (FROM_ROM_BYTE)
  72. :(MCU_OUT_MEM);
  73. assign ROM_DATA[7:0] = ROM_ADDR0
  74. ?(!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
  75. : (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
  76. : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)
  77. )
  78. )
  79. :8'bZ;
  80. assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
  81. :(!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
  82. : (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
  83. : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)
  84. )
  85. );
  86. always @(posedge CLK) begin
  87. if(SNES_DATA_TO_MEM)
  88. SNES_IN_MEM <= SNES_DATA;
  89. if(MCU_DATA_TO_MEM)
  90. MCU_IN_MEM <= MCU_IN_DATA;
  91. if(ROM_DATA_TO_SNES_MEM)
  92. SNES_OUT_MEM <= FROM_ROM_BYTE;
  93. if(ROM_DATA_TO_MCU_MEM)
  94. MCU_OUT_MEM <= FROM_ROM_BYTE;
  95. end
  96. endmodule