spi.c 6.1 KB

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  1. /* Sd2iec - SD/MMC to Commodore serial bus interface/controller
  2. Copyright (C) 2007-2010 Ingo Korb <ingo@akana.de>
  3. Inspiration and low-level SD/MMC access based on code from MMC2IEC
  4. by Lars Pontoppidan et al., see sdcard.c|h and config.h.
  5. FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; version 2 of the License only.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. spi.c: Low-level SPI routines
  17. */
  18. #include <arm/NXP/LPC17xx/LPC17xx.h>
  19. #include "bits.h"
  20. #include "config.h"
  21. #include "spi.h"
  22. #include "uart.h"
  23. #define SSP_TFE 0 // Transmit FIFO empty
  24. #define SSP_TNF 1 // Transmit FIFO not full
  25. #define SSP_RNE 2 // Receive FIFO not empty
  26. #define SSP_RFF 3 // Receive FIFO full
  27. #define SSP_BSY 4 // Busy
  28. void spi_preinit() {
  29. /* Set clock prescaler to 1:1 */
  30. BITBAND(LPC_SC->SSP_PCLKREG, SSP_PCLKBIT) = 1;
  31. }
  32. void spi_init(spi_speed_t speed) {
  33. /* configure data format - 8 bits, SPI, CPOL=0, CPHA=0, 1 clock per bit */
  34. SSP_REGS->CR0 = (8-1);
  35. /* set clock prescaler */
  36. if (speed == SPI_SPEED_FAST) {
  37. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
  38. } else if (speed == SPI_SPEED_SLOW) {
  39. SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
  40. } else if (speed == SPI_SPEED_FPGA_FAST) {
  41. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST;
  42. } else {
  43. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW;
  44. }
  45. /* Enable SSP */
  46. SSP_REGS->CR1 = BV(1);
  47. /* Enable DMA controller, little-endian mode */
  48. BITBAND(LPC_SC->PCONP, 29) = 1;
  49. LPC_GPDMA->DMACConfig = 1;
  50. }
  51. void spi_tx_sync() {
  52. /* Wait until TX fifo is flushed */
  53. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  54. }
  55. void spi_tx_byte(uint8_t data) {
  56. /* Wait until TX fifo can accept data */
  57. while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ;
  58. /* Send byte */
  59. SSP_REGS->DR = data;
  60. }
  61. uint8_t spi_txrx_byte(uint8_t data) {
  62. /* Wait until SSP is not busy */
  63. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  64. /* Clear RX fifo */
  65. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  66. (void) SSP_REGS->DR;
  67. /* Transmit a single dummy byte */
  68. SSP_REGS->DR = data;
  69. /* Wait until answer has been received */
  70. while (!BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  71. return SSP_REGS->DR;
  72. }
  73. uint8_t spi_rx_byte() {
  74. /* Wait until SSP is not busy */
  75. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  76. /* Clear RX fifo */
  77. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  78. (void) SSP_REGS->DR;
  79. /* Transmit a single dummy byte */
  80. SSP_REGS->DR = 0xff;
  81. /* Wait until answer has been received */
  82. while (!BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  83. return SSP_REGS->DR;
  84. }
  85. void spi_tx_block(const void *ptr, unsigned int length) {
  86. const uint8_t *data = (const uint8_t *)ptr;
  87. while (length--) {
  88. /* Wait until TX fifo can accept data */
  89. while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ;
  90. SSP_REGS->DR = *data++;
  91. }
  92. }
  93. void spi_rx_block(void *ptr, unsigned int length) {
  94. uint8_t *data = (uint8_t *)ptr;
  95. unsigned int txlen = length;
  96. /* Wait until SSP is not busy */
  97. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  98. /* Clear RX fifo */
  99. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  100. (void) SSP_REGS->DR;
  101. if ((length & 3) != 0 || ((uint32_t)ptr & 3) != 0) {
  102. /* Odd length or unaligned buffer */
  103. while (length > 0) {
  104. /* Wait until TX or RX FIFO are ready */
  105. while (txlen > 0 && !BITBAND(SSP_REGS->SR, SSP_TNF) &&
  106. !BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  107. /* Try to receive data */
  108. while (length > 0 && BITBAND(SSP_REGS->SR, SSP_RNE)) {
  109. *data++ = SSP_REGS->DR;
  110. length--;
  111. }
  112. /* Send dummy data until TX full or RX ready */
  113. while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF) && !BITBAND(SSP_REGS->SR, SSP_RNE)) {
  114. txlen--;
  115. SSP_REGS->DR = 0xff;
  116. }
  117. }
  118. } else {
  119. /* Clear interrupt flags of DMA channels 0 */
  120. LPC_GPDMA->DMACIntTCClear = BV(0);
  121. LPC_GPDMA->DMACIntErrClr = BV(0);
  122. /* Set up RX DMA channel */
  123. SSP_DMACH->DMACCSrcAddr = (uint32_t)&SSP_REGS->DR;
  124. SSP_DMACH->DMACCDestAddr = (uint32_t)ptr;
  125. SSP_DMACH->DMACCLLI = 0; // no linked list
  126. SSP_DMACH->DMACCControl = length
  127. | (0 << 12) // source burst size 1 (FIXME: Check if larger possible/useful)
  128. | (0 << 15) // destination burst size 1
  129. | (0 << 18) // source transfer width 1 byte
  130. | (2 << 21) // destination transfer width 4 bytes
  131. | (0 << 26) // source address not incremented
  132. | (1 << 27) // destination address incremented
  133. ;
  134. SSP_DMACH->DMACCConfig = 1 // enable channel
  135. | (SSP_DMAID_RX << 1) // data source SSP RX
  136. | (2 << 11) // transfer from peripheral to memory
  137. ;
  138. /* Enable RX FIFO DMA */
  139. SSP_REGS->DMACR = 1;
  140. /* Write <length> bytes into TX FIFO */
  141. // FIXME: Any value in doing this using DMA too?
  142. while (txlen > 0) {
  143. while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF)) {
  144. txlen--;
  145. SSP_REGS->DR = 0xff;
  146. }
  147. }
  148. /* Wait until DMA channel disables itself */
  149. while (SSP_DMACH->DMACCConfig & 1) ;
  150. /* Disable RX FIFO DMA */
  151. SSP_REGS->DMACR = 0;
  152. }
  153. }
  154. void spi_set_speed(spi_speed_t speed) {
  155. /* Wait until TX fifo is empty */
  156. while (!BITBAND(SSP_REGS->SR, 0)) ;
  157. /* Disable SSP (FIXME: Is this required?) */
  158. SSP_REGS->CR1 = 0;
  159. /* Change clock divisor */
  160. if (speed == SPI_SPEED_FAST) {
  161. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
  162. } else if (speed == SPI_SPEED_SLOW) {
  163. SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
  164. } else if (speed == SPI_SPEED_FPGA_FAST) {
  165. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST;
  166. } else {
  167. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW;
  168. }
  169. /* Enable SSP */
  170. SSP_REGS->CR1 = BV(1);
  171. }