fpga_spi.c 10 KB

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  1. /* sd2snes - SD card based universal cartridge for the SNES
  2. Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
  3. AVR firmware portion
  4. Inspired by and based on code from sd2iec, written by Ingo Korb et al.
  5. See sdcard.c|h, config.h.
  6. FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
  7. see ff.c|h.
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; version 2 of the License only.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. fpga_spi.h: functions for SPI ctrl, SRAM interfacing and feature configuration
  19. */
  20. /*
  21. SPI commands
  22. cmd param function
  23. =============================================
  24. 0t bbhhll set address to 0xbbhhll
  25. t = target
  26. target: 0 = RAM
  27. 1 = MSU Audio buffer
  28. 2 = MSU Data buffer
  29. targets 1 & 2 only require 2 address bytes to
  30. be written.
  31. 10 bbhhll set SNES input address mask to 0xbbhhll
  32. 20 bbhhll set SRAM address mask to 0xbbhhll
  33. 3m - set mapper to m
  34. 0=HiROM, 1=LoROM, 2=ExHiROM, 6=SF96, 7=Menu
  35. 4s - trigger SD DMA (512b from SD to memory)
  36. s: Bit 2 = partial, Bit 1:0 = target
  37. target: see above
  38. 60 sssseeee set SD DMA partial transfer start+end
  39. ssss = start offset (msb first)
  40. eeee = end offset (msb first)
  41. 8p - read (RAM only)
  42. p: 0 = no increment after read
  43. 8 = increment after read
  44. 9p {xx}* write xx
  45. p: i-tt
  46. tt = target (see above)
  47. i = increment (see above)
  48. E0 ssrr set MSU-1 status register (=FPGA status [7:0])
  49. ss = bits to set in status register (1=set)
  50. rr = bits to reset in status register (1=reset)
  51. E1 - pause DAC
  52. E2 - resume/play DAC
  53. E3 - reset DAC playback pointer (0)
  54. E4 hhll set MSU read pointer
  55. E5 tt{7} set RTC (SPC7110 format + 1000s of year,
  56. nibbles packed)
  57. eg 0x20111210094816 is 2011-12-10, 9:48:16
  58. E6 ssrr set/reset BS-X status register [7:0]
  59. E7 - reset SRTC state
  60. E8 - reset DSP program and data ROM write pointers
  61. E9 hhmmllxxxx write+incr. DSP program ROM (xxxx=dummy writes)
  62. EA hhllxxxx write+incr. DSP data ROM (xxxx=dummy writes)
  63. EB - put DSP into reset
  64. EC - release DSP from reset
  65. ED - set feature enable bits (see below)
  66. F0 - receive test token (to see if FPGA is alive)
  67. F1 - receive status (16bit, MSB first), see below
  68. F2 - get MSU data address (32bit, MSB first)
  69. F3 - get MSU audio track no. (16bit, MSB first)
  70. F4 - get MSU volume (8bit)
  71. FE - get SNES master clock frequency (32bit, MSB first)
  72. measured 1x/sec
  73. FF {xx}* echo (returns the sent data in the next byte)
  74. FPGA status word:
  75. bit function
  76. ==========================================================================
  77. 15 SD DMA busy (0=idle, 1=busy)
  78. 14 DAC read pointer MSB
  79. 13 MSU read pointer MSB
  80. 12 [TODO SD DMA CRC status (0=ok, 1=error); valid after bit 15 -> 0]
  81. 11 reserved (0)
  82. 10 reserved (0)
  83. 9 reserved (0)
  84. 8 reserved (0)
  85. 7 reserved (0)
  86. 6 reserved (0)
  87. 5 MSU1 Audio request from SNES
  88. 4 MSU1 Data request from SNES
  89. 3 reserved (0)
  90. 2 MSU1 Audio control status: 0=no repeat, 1=repeat
  91. 1 MSU1 Audio control status: 0=pause, 1=play
  92. 0 MSU1 Audio control request
  93. FPGA feature enable bits:
  94. bit function
  95. ==========================================================================
  96. 7 -
  97. 6 -
  98. 5 -
  99. 4 -
  100. 3 enable MSU1 registers
  101. 2 enable SRTC registers
  102. 1 enable ST0010 mapping
  103. 0 enable DSPx mapping
  104. */
  105. #include <arm/NXP/LPC17xx/LPC17xx.h>
  106. #include "bits.h"
  107. #include "fpga.h"
  108. #include "config.h"
  109. #include "uart.h"
  110. #include "spi.h"
  111. #include "fpga_spi.h"
  112. #include "timer.h"
  113. void fpga_spi_init(void) {
  114. spi_init(SPI_SPEED_FPGA_FAST);
  115. }
  116. void set_msu_addr(uint16_t address) {
  117. FPGA_SELECT();
  118. FPGA_TX_BYTE(0x02);
  119. FPGA_TX_BYTE((address>>8)&0xff);
  120. FPGA_TX_BYTE((address)&0xff);
  121. FPGA_DESELECT();
  122. }
  123. void set_dac_addr(uint16_t address) {
  124. FPGA_SELECT();
  125. FPGA_TX_BYTE(0x01);
  126. FPGA_TX_BYTE((address>>8)&0xff);
  127. FPGA_TX_BYTE((address)&0xff);
  128. FPGA_DESELECT();
  129. }
  130. void set_mcu_addr(uint32_t address) {
  131. FPGA_SELECT();
  132. FPGA_TX_BYTE(0x00);
  133. FPGA_TX_BYTE((address>>16)&0xff);
  134. FPGA_TX_BYTE((address>>8)&0xff);
  135. FPGA_TX_BYTE((address)&0xff);
  136. FPGA_DESELECT();
  137. }
  138. void set_saveram_mask(uint32_t mask) {
  139. FPGA_SELECT();
  140. FPGA_TX_BYTE(0x20);
  141. FPGA_TX_BYTE((mask>>16)&0xff);
  142. FPGA_TX_BYTE((mask>>8)&0xff);
  143. FPGA_TX_BYTE((mask)&0xff);
  144. FPGA_DESELECT();
  145. }
  146. void set_rom_mask(uint32_t mask) {
  147. FPGA_SELECT();
  148. FPGA_TX_BYTE(0x10);
  149. FPGA_TX_BYTE((mask>>16)&0xff);
  150. FPGA_TX_BYTE((mask>>8)&0xff);
  151. FPGA_TX_BYTE((mask)&0xff);
  152. FPGA_DESELECT();
  153. }
  154. void set_mapper(uint8_t val) {
  155. FPGA_SELECT();
  156. FPGA_TX_BYTE(0x30 | (val & 0x0f));
  157. FPGA_DESELECT();
  158. }
  159. uint8_t fpga_test() {
  160. FPGA_SELECT();
  161. FPGA_TX_BYTE(0xF0); /* TEST */
  162. FPGA_TX_BYTE(0x00); /* dummy */
  163. uint8_t result = FPGA_RX_BYTE();
  164. FPGA_DESELECT();
  165. return result;
  166. }
  167. uint16_t fpga_status() {
  168. FPGA_SELECT();
  169. FPGA_TX_BYTE(0xF1); /* STATUS */
  170. FPGA_TX_BYTE(0x00); /* dummy */
  171. uint16_t result = (FPGA_RX_BYTE()) << 8;
  172. result |= FPGA_RX_BYTE();
  173. FPGA_DESELECT();
  174. return result;
  175. }
  176. void fpga_set_sddma_range(uint16_t start, uint16_t end) {
  177. FPGA_SELECT();
  178. FPGA_TX_BYTE(0x60); /* DMA_RANGE */
  179. FPGA_TX_BYTE(start>>8);
  180. FPGA_TX_BYTE(start&0xff);
  181. FPGA_TX_BYTE(end>>8);
  182. FPGA_TX_BYTE(end&0xff);
  183. //if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
  184. FPGA_DESELECT();
  185. }
  186. void fpga_sddma(uint8_t tgt, uint8_t partial) {
  187. uint32_t test = 0;
  188. uint8_t status = 0;
  189. BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 0;
  190. FPGA_SELECT();
  191. FPGA_TX_BYTE(0x40 | (tgt & 0x3) | ((partial & 1) << 2) ); /* DO DMA */
  192. FPGA_TX_BYTE(0x00); /* dummy for falling DMA_EN edge */
  193. //if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
  194. FPGA_DESELECT();
  195. FPGA_SELECT();
  196. FPGA_TX_BYTE(0xF1); /* STATUS */
  197. FPGA_TX_BYTE(0x00); /* dummy */
  198. while((status=FPGA_RX_BYTE()) & 0x80) {
  199. FPGA_RX_BYTE(); /* eat the 2nd status byte */
  200. test++;
  201. }
  202. FPGA_DESELECT();
  203. if(test<5)printf("loopy: %ld %02x\n", test, status);
  204. BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
  205. }
  206. void set_dac_vol(uint8_t volume) {
  207. FPGA_SELECT();
  208. FPGA_TX_BYTE(0x50);
  209. FPGA_TX_BYTE(volume);
  210. FPGA_TX_BYTE(0x00); /* latch rise */
  211. FPGA_TX_BYTE(0x00); /* latch fall */
  212. FPGA_DESELECT();
  213. }
  214. void dac_play() {
  215. FPGA_SELECT();
  216. FPGA_TX_BYTE(0xe2);
  217. FPGA_TX_BYTE(0x00); /* latch reset */
  218. FPGA_DESELECT();
  219. }
  220. void dac_pause() {
  221. FPGA_SELECT();
  222. FPGA_TX_BYTE(0xe1);
  223. FPGA_TX_BYTE(0x00); /* latch reset */
  224. FPGA_DESELECT();
  225. }
  226. void dac_reset() {
  227. FPGA_SELECT();
  228. FPGA_TX_BYTE(0xe3);
  229. FPGA_TX_BYTE(0x00); /* latch reset */
  230. FPGA_TX_BYTE(0x00); /* latch reset */
  231. FPGA_DESELECT();
  232. }
  233. void msu_reset(uint16_t address) {
  234. FPGA_SELECT();
  235. FPGA_TX_BYTE(0xe4);
  236. FPGA_TX_BYTE((address>>8) & 0xff); /* address hi */
  237. FPGA_TX_BYTE(address & 0xff); /* address lo */
  238. FPGA_TX_BYTE(0x00); /* latch reset */
  239. FPGA_TX_BYTE(0x00); /* latch reset */
  240. FPGA_DESELECT();
  241. }
  242. void set_msu_status(uint8_t set, uint8_t reset) {
  243. FPGA_SELECT();
  244. FPGA_TX_BYTE(0xe0);
  245. FPGA_TX_BYTE(set);
  246. FPGA_TX_BYTE(reset);
  247. FPGA_TX_BYTE(0x00); /* latch reset */
  248. FPGA_DESELECT();
  249. }
  250. uint8_t get_msu_volume() {
  251. FPGA_SELECT();
  252. FPGA_TX_BYTE(0xF4); /* MSU_VOLUME */
  253. FPGA_TX_BYTE(0x00); /* dummy */
  254. uint8_t result = FPGA_RX_BYTE();
  255. FPGA_DESELECT();
  256. return result;
  257. }
  258. uint16_t get_msu_track() {
  259. FPGA_SELECT();
  260. FPGA_TX_BYTE(0xF3); /* MSU_TRACK */
  261. FPGA_TX_BYTE(0x00); /* dummy */
  262. uint16_t result = (FPGA_RX_BYTE()) << 8;
  263. result |= FPGA_RX_BYTE();
  264. FPGA_DESELECT();
  265. return result;
  266. }
  267. uint32_t get_msu_offset() {
  268. FPGA_SELECT();
  269. FPGA_TX_BYTE(0xF2); /* MSU_OFFSET */
  270. FPGA_TX_BYTE(0x00); /* dummy */
  271. uint32_t result = (FPGA_RX_BYTE()) << 24;
  272. result |= (FPGA_RX_BYTE()) << 16;
  273. result |= (FPGA_RX_BYTE()) << 8;
  274. result |= (FPGA_RX_BYTE());
  275. FPGA_DESELECT();
  276. return result;
  277. }
  278. uint32_t get_snes_sysclk() {
  279. FPGA_SELECT();
  280. FPGA_TX_BYTE(0xFE); /* GET_SYSCLK */
  281. FPGA_TX_BYTE(0x00); /* dummy */
  282. FPGA_TX_BYTE(0x00); /* dummy */
  283. uint32_t result = (FPGA_RX_BYTE()) << 24;
  284. result |= (FPGA_RX_BYTE()) << 16;
  285. result |= (FPGA_RX_BYTE()) << 8;
  286. result |= (FPGA_RX_BYTE());
  287. FPGA_DESELECT();
  288. return result;
  289. }
  290. void set_bsx_regs(uint8_t set, uint8_t reset) {
  291. FPGA_SELECT();
  292. FPGA_TX_BYTE(0xe6);
  293. FPGA_TX_BYTE(set);
  294. FPGA_TX_BYTE(reset);
  295. FPGA_TX_BYTE(0x00); /* latch reset */
  296. FPGA_DESELECT();
  297. }
  298. void set_fpga_time(uint64_t time) {
  299. FPGA_SELECT();
  300. FPGA_TX_BYTE(0xe5);
  301. FPGA_TX_BYTE((time >> 48) & 0xff);
  302. FPGA_TX_BYTE((time >> 40) & 0xff);
  303. FPGA_TX_BYTE((time >> 32) & 0xff);
  304. FPGA_TX_BYTE((time >> 24) & 0xff);
  305. FPGA_TX_BYTE((time >> 16) & 0xff);
  306. FPGA_TX_BYTE((time >> 8) & 0xff);
  307. FPGA_TX_BYTE(time & 0xff);
  308. FPGA_TX_BYTE(0x00);
  309. FPGA_DESELECT();
  310. }
  311. void fpga_reset_srtc_state() {
  312. FPGA_SELECT();
  313. FPGA_TX_BYTE(0xe7);
  314. FPGA_TX_BYTE(0x00);
  315. FPGA_TX_BYTE(0x00);
  316. FPGA_DESELECT();
  317. }
  318. void fpga_reset_dspx_addr() {
  319. FPGA_SELECT();
  320. FPGA_TX_BYTE(0xe8);
  321. FPGA_TX_BYTE(0x00);
  322. FPGA_TX_BYTE(0x00);
  323. FPGA_DESELECT();
  324. }
  325. void fpga_write_dspx_pgm(uint32_t data) {
  326. FPGA_SELECT();
  327. FPGA_TX_BYTE(0xe9);
  328. FPGA_TX_BYTE((data>>16)&0xff);
  329. FPGA_TX_BYTE((data>>8)&0xff);
  330. FPGA_TX_BYTE((data)&0xff);
  331. FPGA_TX_BYTE(0x00);
  332. FPGA_TX_BYTE(0x00);
  333. FPGA_DESELECT();
  334. }
  335. void fpga_write_dspx_dat(uint16_t data) {
  336. FPGA_SELECT();
  337. FPGA_TX_BYTE(0xea);
  338. FPGA_TX_BYTE((data>>8)&0xff);
  339. FPGA_TX_BYTE((data)&0xff);
  340. FPGA_TX_BYTE(0x00);
  341. FPGA_TX_BYTE(0x00);
  342. FPGA_DESELECT();
  343. }
  344. void fpga_dspx_reset(uint8_t reset) {
  345. FPGA_SELECT();
  346. FPGA_TX_BYTE(reset ? 0xeb : 0xec);
  347. FPGA_TX_BYTE(0x00);
  348. FPGA_DESELECT();
  349. }
  350. void fpga_set_features(uint8_t feat) {
  351. printf("set features: %02x\n", feat);
  352. FPGA_SELECT();
  353. FPGA_TX_BYTE(0xed);
  354. FPGA_TX_BYTE(feat);
  355. FPGA_DESELECT();
  356. }