fpga.c 4.8 KB

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  1. /* sd2snes - SD card based universal cartridge for the SNES
  2. Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
  3. AVR firmware portion
  4. Inspired by and based on code from sd2iec, written by Ingo Korb et al.
  5. See sdcard.c|h, config.h.
  6. FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
  7. see ff.c|h.
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; version 2 of the License only.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. fpga.c: FPGA (re)configuration
  19. */
  20. /*
  21. FPGA pin mapping
  22. ================
  23. CCLK P0.11 out
  24. PROG_B P1.10 out
  25. INIT_B P2.9 in
  26. DIN P2.8 out
  27. DONE P0.22 in
  28. */
  29. #include <arm/NXP/LPC17xx/LPC17xx.h>
  30. #include "bits.h"
  31. #include "fpga.h"
  32. #include "fpga_spi.h"
  33. #include "config.h"
  34. #include "uart.h"
  35. #include "sdcard.h"
  36. #include "diskio.h"
  37. #include "integer.h"
  38. #include "ff.h"
  39. #include "fileops.h"
  40. // XXX #include "fpga_spi.h"
  41. #include "spi.h"
  42. #include "led.h"
  43. #include "timer.h"
  44. #include "rle.h"
  45. #include "cfgware.h"
  46. void fpga_set_prog_b(uint8_t val) {
  47. if(val)
  48. BITBAND(PROGBREG->FIOSET, PROGBBIT) = 1;
  49. else
  50. BITBAND(PROGBREG->FIOCLR, PROGBBIT) = 1;
  51. }
  52. void fpga_set_cclk(uint8_t val) {
  53. if(val)
  54. BITBAND(CCLKREG->FIOSET, CCLKBIT) = 1;
  55. else
  56. BITBAND(CCLKREG->FIOCLR, CCLKBIT) = 1;
  57. }
  58. int fpga_get_initb() {
  59. return BITBAND(INITBREG->FIOPIN, INITBBIT);
  60. }
  61. void fpga_init() {
  62. /* mainly GPIO directions */
  63. BITBAND(CCLKREG->FIODIR, CCLKBIT) = 1; /* CCLK */
  64. BITBAND(DONEREG->FIODIR, DONEBIT) = 0; /* DONE */
  65. BITBAND(PROGBREG->FIODIR, PROGBBIT) = 1; /* PROG_B */
  66. BITBAND(DINREG->FIODIR, DINBIT) = 1; /* DIN */
  67. BITBAND(INITBREG->FIODIR, INITBBIT) = 0; /* INIT_B */
  68. LPC_GPIO2->FIOMASK1 = 0;
  69. SPI_OFFLOAD=0;
  70. fpga_set_cclk(0); /* initial clk=0 */
  71. }
  72. int fpga_get_done(void) {
  73. return BITBAND(LPC_GPIO0->FIOPIN, 22);
  74. }
  75. void fpga_postinit() {
  76. LPC_GPIO2->FIOMASK1 = 0;
  77. }
  78. void fpga_pgm(uint8_t* filename) {
  79. int MAXRETRIES = 10;
  80. int retries = MAXRETRIES;
  81. uint8_t data;
  82. int i;
  83. tick_t timeout;
  84. // UINT bytes_read;
  85. // uint16_t j;
  86. do {
  87. i=0;
  88. timeout = getticks() + 100;
  89. fpga_set_prog_b(0);
  90. uart_putc('P');
  91. fpga_set_prog_b(1);
  92. while(!fpga_get_initb()){
  93. if(getticks() > timeout) {
  94. printf("no response from FPGA trying to initiate configuration!\n");
  95. led_panic();
  96. }
  97. };
  98. LPC_GPIO2->FIOMASK1 = ~(BV(0));
  99. uart_putc('p');
  100. /* open configware file */
  101. file_open(filename, FA_READ);
  102. if(file_res) {
  103. uart_putc('?');
  104. uart_putc(0x30+file_res);
  105. return;
  106. }
  107. uart_putc('C');
  108. for (;;) {
  109. data = rle_file_getc();
  110. i++;
  111. if (file_status || file_res) break; /* error or eof */
  112. FPGA_SEND_BYTE_SERIAL(data);
  113. }
  114. uart_putc('c');
  115. file_close();
  116. printf("fpga_pgm: %d bytes programmed\n", i);
  117. delay_ms(1);
  118. } while (!fpga_get_done() && retries--);
  119. if(!fpga_get_done()) {
  120. printf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
  121. led_panic();
  122. }
  123. printf("FPGA configured\n");
  124. fpga_postinit();
  125. }
  126. void fpga_rompgm() {
  127. int MAXRETRIES = 10;
  128. int retries = MAXRETRIES;
  129. uint8_t data;
  130. int i;
  131. tick_t timeout;
  132. // UINT bytes_read;
  133. // uint16_t j;
  134. do {
  135. i=0;
  136. timeout = getticks() + 100;
  137. fpga_set_prog_b(0);
  138. uart_putc('P');
  139. fpga_set_prog_b(1);
  140. while(!fpga_get_initb()){
  141. if(getticks() > timeout) {
  142. printf("no response from FPGA trying to initiate configuration!\n");
  143. led_panic();
  144. }
  145. };
  146. LPC_GPIO2->FIOMASK1 = ~(BV(0));
  147. uart_putc('p');
  148. /* open configware file */
  149. rle_mem_init(cfgware, sizeof(cfgware));
  150. printf("sizeof(cfgware) = %d\n", sizeof(cfgware));
  151. for (;;) {
  152. data = rle_mem_getc();
  153. if(rle_state) break;
  154. i++;
  155. FPGA_SEND_BYTE_SERIAL(data);
  156. }
  157. uart_putc('c');
  158. printf("fpga_pgm: %d bytes programmed\n", i);
  159. delay_ms(1);
  160. } while (!fpga_get_done() && retries--);
  161. if(!fpga_get_done()) {
  162. printf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
  163. led_panic();
  164. }
  165. printf("FPGA configured\n");
  166. fpga_postinit();
  167. }
  168. void set_mcu_ovr(uint8_t val) {
  169. if(!val) {
  170. /* shared mode */
  171. FPGA_SPI_SLOW();
  172. SET_MCU_OVR();
  173. printf("SPI slow\n");
  174. } else {
  175. /* mcu exclusive mode */
  176. FPGA_SPI_FAST();
  177. CLR_MCU_OVR();
  178. printf("SPI fast\n");
  179. }
  180. }