upd77c25_datram.v 5.6 KB

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  25. * (c) Copyright 1995-2012 Xilinx, Inc. *
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  28. // You must compile the wrapper file upd77c25_datram.v when simulating
  29. // the core, upd77c25_datram. When compiling the wrapper file, be sure to
  30. // reference the XilinxCoreLib Verilog simulation library. For detailed
  31. // instructions, please refer to the "CORE Generator Help".
  32. // The synthesis directives "translate_off/translate_on" specified below are
  33. // supported by Xilinx, Mentor Graphics and Synplicity synthesis
  34. // tools. Ensure they are correct for your synthesis tool(s).
  35. `timescale 1ns/1ps
  36. module upd77c25_datram(
  37. clka,
  38. wea,
  39. addra,
  40. dina,
  41. douta,
  42. clkb,
  43. web,
  44. addrb,
  45. dinb,
  46. doutb
  47. );
  48. input clka;
  49. input [0 : 0] wea;
  50. input [9 : 0] addra;
  51. input [15 : 0] dina;
  52. output [15 : 0] douta;
  53. input clkb;
  54. input [0 : 0] web;
  55. input [10 : 0] addrb;
  56. input [7 : 0] dinb;
  57. output [7 : 0] doutb;
  58. // synthesis translate_off
  59. BLK_MEM_GEN_V6_3 #(
  60. .C_ADDRA_WIDTH(10),
  61. .C_ADDRB_WIDTH(11),
  62. .C_ALGORITHM(1),
  63. .C_AXI_ID_WIDTH(4),
  64. .C_AXI_SLAVE_TYPE(0),
  65. .C_AXI_TYPE(1),
  66. .C_BYTE_SIZE(9),
  67. .C_COMMON_CLK(1),
  68. .C_DEFAULT_DATA("0"),
  69. .C_DISABLE_WARN_BHV_COLL(0),
  70. .C_DISABLE_WARN_BHV_RANGE(0),
  71. .C_ENABLE_32BIT_ADDRESS(0),
  72. .C_FAMILY("spartan3"),
  73. .C_HAS_AXI_ID(0),
  74. .C_HAS_ENA(0),
  75. .C_HAS_ENB(0),
  76. .C_HAS_INJECTERR(0),
  77. .C_HAS_MEM_OUTPUT_REGS_A(0),
  78. .C_HAS_MEM_OUTPUT_REGS_B(0),
  79. .C_HAS_MUX_OUTPUT_REGS_A(0),
  80. .C_HAS_MUX_OUTPUT_REGS_B(0),
  81. .C_HAS_REGCEA(0),
  82. .C_HAS_REGCEB(0),
  83. .C_HAS_RSTA(0),
  84. .C_HAS_RSTB(0),
  85. .C_HAS_SOFTECC_INPUT_REGS_A(0),
  86. .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
  87. .C_INIT_FILE_NAME("no_coe_file_loaded"),
  88. .C_INITA_VAL("0"),
  89. .C_INITB_VAL("0"),
  90. .C_INTERFACE_TYPE(0),
  91. .C_LOAD_INIT_FILE(0),
  92. .C_MEM_TYPE(2),
  93. .C_MUX_PIPELINE_STAGES(0),
  94. .C_PRIM_TYPE(1),
  95. .C_READ_DEPTH_A(1024),
  96. .C_READ_DEPTH_B(2048),
  97. .C_READ_WIDTH_A(16),
  98. .C_READ_WIDTH_B(8),
  99. .C_RST_PRIORITY_A("CE"),
  100. .C_RST_PRIORITY_B("CE"),
  101. .C_RST_TYPE("SYNC"),
  102. .C_RSTRAM_A(0),
  103. .C_RSTRAM_B(0),
  104. .C_SIM_COLLISION_CHECK("ALL"),
  105. .C_USE_BYTE_WEA(0),
  106. .C_USE_BYTE_WEB(0),
  107. .C_USE_DEFAULT_DATA(0),
  108. .C_USE_ECC(0),
  109. .C_USE_SOFTECC(0),
  110. .C_WEA_WIDTH(1),
  111. .C_WEB_WIDTH(1),
  112. .C_WRITE_DEPTH_A(1024),
  113. .C_WRITE_DEPTH_B(2048),
  114. .C_WRITE_MODE_A("WRITE_FIRST"),
  115. .C_WRITE_MODE_B("WRITE_FIRST"),
  116. .C_WRITE_WIDTH_A(16),
  117. .C_WRITE_WIDTH_B(8),
  118. .C_XDEVICEFAMILY("spartan3")
  119. )
  120. inst (
  121. .CLKA(clka),
  122. .WEA(wea),
  123. .ADDRA(addra),
  124. .DINA(dina),
  125. .DOUTA(douta),
  126. .CLKB(clkb),
  127. .WEB(web),
  128. .ADDRB(addrb),
  129. .DINB(dinb),
  130. .DOUTB(doutb),
  131. .RSTA(),
  132. .ENA(),
  133. .REGCEA(),
  134. .RSTB(),
  135. .ENB(),
  136. .REGCEB(),
  137. .INJECTSBITERR(),
  138. .INJECTDBITERR(),
  139. .SBITERR(),
  140. .DBITERR(),
  141. .RDADDRECC(),
  142. .S_ACLK(),
  143. .S_ARESETN(),
  144. .S_AXI_AWID(),
  145. .S_AXI_AWADDR(),
  146. .S_AXI_AWLEN(),
  147. .S_AXI_AWSIZE(),
  148. .S_AXI_AWBURST(),
  149. .S_AXI_AWVALID(),
  150. .S_AXI_AWREADY(),
  151. .S_AXI_WDATA(),
  152. .S_AXI_WSTRB(),
  153. .S_AXI_WLAST(),
  154. .S_AXI_WVALID(),
  155. .S_AXI_WREADY(),
  156. .S_AXI_BID(),
  157. .S_AXI_BRESP(),
  158. .S_AXI_BVALID(),
  159. .S_AXI_BREADY(),
  160. .S_AXI_ARID(),
  161. .S_AXI_ARADDR(),
  162. .S_AXI_ARLEN(),
  163. .S_AXI_ARSIZE(),
  164. .S_AXI_ARBURST(),
  165. .S_AXI_ARVALID(),
  166. .S_AXI_ARREADY(),
  167. .S_AXI_RID(),
  168. .S_AXI_RDATA(),
  169. .S_AXI_RRESP(),
  170. .S_AXI_RLAST(),
  171. .S_AXI_RVALID(),
  172. .S_AXI_RREADY(),
  173. .S_AXI_INJECTSBITERR(),
  174. .S_AXI_INJECTDBITERR(),
  175. .S_AXI_SBITERR(),
  176. .S_AXI_DBITERR(),
  177. .S_AXI_RDADDRECC()
  178. );
  179. // synthesis translate_on
  180. endmodule