dac_buf.v 5.5 KB

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  28. // You must compile the wrapper file dac_buf.v when simulating
  29. // the core, dac_buf. When compiling the wrapper file, be sure to
  30. // reference the XilinxCoreLib Verilog simulation library. For detailed
  31. // instructions, please refer to the "CORE Generator Help".
  32. // The synthesis directives "translate_off/translate_on" specified below are
  33. // supported by Xilinx, Mentor Graphics and Synplicity synthesis
  34. // tools. Ensure they are correct for your synthesis tool(s).
  35. `timescale 1ns/1ps
  36. module dac_buf(
  37. clka,
  38. wea,
  39. addra,
  40. dina,
  41. clkb,
  42. addrb,
  43. doutb
  44. );
  45. input clka;
  46. input [0 : 0] wea;
  47. input [10 : 0] addra;
  48. input [7 : 0] dina;
  49. input clkb;
  50. input [8 : 0] addrb;
  51. output [31 : 0] doutb;
  52. // synthesis translate_off
  53. BLK_MEM_GEN_V6_3 #(
  54. .C_ADDRA_WIDTH(11),
  55. .C_ADDRB_WIDTH(9),
  56. .C_ALGORITHM(1),
  57. .C_AXI_ID_WIDTH(4),
  58. .C_AXI_SLAVE_TYPE(0),
  59. .C_AXI_TYPE(1),
  60. .C_BYTE_SIZE(9),
  61. .C_COMMON_CLK(1),
  62. .C_DEFAULT_DATA("0"),
  63. .C_DISABLE_WARN_BHV_COLL(0),
  64. .C_DISABLE_WARN_BHV_RANGE(0),
  65. .C_ENABLE_32BIT_ADDRESS(0),
  66. .C_FAMILY("spartan3"),
  67. .C_HAS_AXI_ID(0),
  68. .C_HAS_ENA(0),
  69. .C_HAS_ENB(0),
  70. .C_HAS_INJECTERR(0),
  71. .C_HAS_MEM_OUTPUT_REGS_A(0),
  72. .C_HAS_MEM_OUTPUT_REGS_B(0),
  73. .C_HAS_MUX_OUTPUT_REGS_A(0),
  74. .C_HAS_MUX_OUTPUT_REGS_B(0),
  75. .C_HAS_REGCEA(0),
  76. .C_HAS_REGCEB(0),
  77. .C_HAS_RSTA(0),
  78. .C_HAS_RSTB(0),
  79. .C_HAS_SOFTECC_INPUT_REGS_A(0),
  80. .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
  81. .C_INIT_FILE_NAME("no_coe_file_loaded"),
  82. .C_INITA_VAL("0"),
  83. .C_INITB_VAL("0"),
  84. .C_INTERFACE_TYPE(0),
  85. .C_LOAD_INIT_FILE(0),
  86. .C_MEM_TYPE(1),
  87. .C_MUX_PIPELINE_STAGES(0),
  88. .C_PRIM_TYPE(1),
  89. .C_READ_DEPTH_A(2048),
  90. .C_READ_DEPTH_B(512),
  91. .C_READ_WIDTH_A(8),
  92. .C_READ_WIDTH_B(32),
  93. .C_RST_PRIORITY_A("CE"),
  94. .C_RST_PRIORITY_B("CE"),
  95. .C_RST_TYPE("SYNC"),
  96. .C_RSTRAM_A(0),
  97. .C_RSTRAM_B(0),
  98. .C_SIM_COLLISION_CHECK("ALL"),
  99. .C_USE_BYTE_WEA(0),
  100. .C_USE_BYTE_WEB(0),
  101. .C_USE_DEFAULT_DATA(0),
  102. .C_USE_ECC(0),
  103. .C_USE_SOFTECC(0),
  104. .C_WEA_WIDTH(1),
  105. .C_WEB_WIDTH(1),
  106. .C_WRITE_DEPTH_A(2048),
  107. .C_WRITE_DEPTH_B(512),
  108. .C_WRITE_MODE_A("WRITE_FIRST"),
  109. .C_WRITE_MODE_B("WRITE_FIRST"),
  110. .C_WRITE_WIDTH_A(8),
  111. .C_WRITE_WIDTH_B(32),
  112. .C_XDEVICEFAMILY("spartan3")
  113. )
  114. inst (
  115. .CLKA(clka),
  116. .WEA(wea),
  117. .ADDRA(addra),
  118. .DINA(dina),
  119. .CLKB(clkb),
  120. .ADDRB(addrb),
  121. .DOUTB(doutb),
  122. .RSTA(),
  123. .ENA(),
  124. .REGCEA(),
  125. .DOUTA(),
  126. .RSTB(),
  127. .ENB(),
  128. .REGCEB(),
  129. .WEB(),
  130. .DINB(),
  131. .INJECTSBITERR(),
  132. .INJECTDBITERR(),
  133. .SBITERR(),
  134. .DBITERR(),
  135. .RDADDRECC(),
  136. .S_ACLK(),
  137. .S_ARESETN(),
  138. .S_AXI_AWID(),
  139. .S_AXI_AWADDR(),
  140. .S_AXI_AWLEN(),
  141. .S_AXI_AWSIZE(),
  142. .S_AXI_AWBURST(),
  143. .S_AXI_AWVALID(),
  144. .S_AXI_AWREADY(),
  145. .S_AXI_WDATA(),
  146. .S_AXI_WSTRB(),
  147. .S_AXI_WLAST(),
  148. .S_AXI_WVALID(),
  149. .S_AXI_WREADY(),
  150. .S_AXI_BID(),
  151. .S_AXI_BRESP(),
  152. .S_AXI_BVALID(),
  153. .S_AXI_BREADY(),
  154. .S_AXI_ARID(),
  155. .S_AXI_ARADDR(),
  156. .S_AXI_ARLEN(),
  157. .S_AXI_ARSIZE(),
  158. .S_AXI_ARBURST(),
  159. .S_AXI_ARVALID(),
  160. .S_AXI_ARREADY(),
  161. .S_AXI_RID(),
  162. .S_AXI_RDATA(),
  163. .S_AXI_RRESP(),
  164. .S_AXI_RLAST(),
  165. .S_AXI_RVALID(),
  166. .S_AXI_RREADY(),
  167. .S_AXI_INJECTSBITERR(),
  168. .S_AXI_INJECTDBITERR(),
  169. .S_AXI_SBITERR(),
  170. .S_AXI_DBITERR(),
  171. .S_AXI_RDADDRECC()
  172. );
  173. // synthesis translate_on
  174. endmodule