spi.c 5.8 KB

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  1. /* Sd2iec - SD/MMC to Commodore serial bus interface/controller
  2. Copyright (C) 2007-2010 Ingo Korb <ingo@akana.de>
  3. Inspiration and low-level SD/MMC access based on code from MMC2IEC
  4. by Lars Pontoppidan et al., see sdcard.c|h and config.h.
  5. FAT filesystem access based on code from ChaN and Jim Brain, see ff.c|h.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; version 2 of the License only.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. spi.c: Low-level SPI routines
  17. */
  18. #include <arm/NXP/LPC17xx/LPC17xx.h>
  19. #include "bits.h"
  20. #include "config.h"
  21. #include "spi.h"
  22. #include "uart.h"
  23. void spi_preinit() {
  24. /* Set clock prescaler to 1:1 */
  25. BITBAND(LPC_SC->SSP_PCLKREG, SSP_PCLKBIT) = 1;
  26. }
  27. void spi_init(spi_speed_t speed) {
  28. /* configure data format - 8 bits, SPI, CPOL=0, CPHA=0, 1 clock per bit */
  29. SSP_REGS->CR0 = (8-1);
  30. /* set clock prescaler */
  31. if (speed == SPI_SPEED_FAST) {
  32. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
  33. } else if (speed == SPI_SPEED_SLOW) {
  34. SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
  35. } else if (speed == SPI_SPEED_FPGA_FAST) {
  36. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST;
  37. } else {
  38. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW;
  39. }
  40. /* Enable SSP */
  41. SSP_REGS->CR1 = BV(1);
  42. /* Enable DMA controller, little-endian mode */
  43. BITBAND(LPC_SC->PCONP, 29) = 1;
  44. LPC_GPDMA->DMACConfig = 1;
  45. }
  46. void spi_tx_sync() {
  47. /* Wait until TX fifo is flushed */
  48. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  49. }
  50. void spi_tx_byte(uint8_t data) {
  51. /* Wait until TX fifo can accept data */
  52. while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ;
  53. /* Send byte */
  54. SSP_REGS->DR = data;
  55. }
  56. uint8_t spi_txrx_byte(uint8_t data) {
  57. /* Wait until SSP is not busy */
  58. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  59. /* Clear RX fifo */
  60. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  61. (void) SSP_REGS->DR;
  62. /* Transmit a single byte */
  63. SSP_REGS->DR = data;
  64. /* Wait until answer has been received */
  65. while (!BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  66. return SSP_REGS->DR;
  67. }
  68. uint8_t spi_rx_byte() {
  69. /* Wait until SSP is not busy */
  70. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  71. /* Clear RX fifo */
  72. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  73. (void) SSP_REGS->DR;
  74. /* Transmit a single dummy byte */
  75. SSP_REGS->DR = 0xff;
  76. /* Wait until answer has been received */
  77. while (!BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  78. return SSP_REGS->DR;
  79. }
  80. void spi_tx_block(const void *ptr, unsigned int length) {
  81. const uint8_t *data = (const uint8_t *)ptr;
  82. while (length--) {
  83. /* Wait until TX fifo can accept data */
  84. while (!BITBAND(SSP_REGS->SR, SSP_TNF)) ;
  85. SSP_REGS->DR = *data++;
  86. }
  87. }
  88. void spi_rx_block(void *ptr, unsigned int length) {
  89. uint8_t *data = (uint8_t *)ptr;
  90. unsigned int txlen = length;
  91. /* Wait until SSP is not busy */
  92. while (BITBAND(SSP_REGS->SR, SSP_BSY)) ;
  93. /* Clear RX fifo */
  94. while (BITBAND(SSP_REGS->SR, SSP_RNE))
  95. (void) SSP_REGS->DR;
  96. if ((length & 3) != 0 || ((uint32_t)ptr & 3) != 0) {
  97. /* Odd length or unaligned buffer */
  98. while (length > 0) {
  99. /* Wait until TX or RX FIFO are ready */
  100. while (txlen > 0 && !BITBAND(SSP_REGS->SR, SSP_TNF) &&
  101. !BITBAND(SSP_REGS->SR, SSP_RNE)) ;
  102. /* Try to receive data */
  103. while (length > 0 && BITBAND(SSP_REGS->SR, SSP_RNE)) {
  104. *data++ = SSP_REGS->DR;
  105. length--;
  106. }
  107. /* Send dummy data until TX full or RX ready */
  108. while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF) && !BITBAND(SSP_REGS->SR, SSP_RNE)) {
  109. txlen--;
  110. SSP_REGS->DR = 0xff;
  111. }
  112. }
  113. } else {
  114. /* Clear interrupt flags of DMA channels 0 */
  115. LPC_GPDMA->DMACIntTCClear = BV(0);
  116. LPC_GPDMA->DMACIntErrClr = BV(0);
  117. /* Set up RX DMA channel */
  118. SSP_DMACH->DMACCSrcAddr = (uint32_t)&SSP_REGS->DR;
  119. SSP_DMACH->DMACCDestAddr = (uint32_t)ptr;
  120. SSP_DMACH->DMACCLLI = 0; // no linked list
  121. SSP_DMACH->DMACCControl = length
  122. | (0 << 12) // source burst size 1 (FIXME: Check if larger possible/useful)
  123. | (0 << 15) // destination burst size 1
  124. | (0 << 18) // source transfer width 1 byte
  125. | (2 << 21) // destination transfer width 4 bytes
  126. | (0 << 26) // source address not incremented
  127. | (1 << 27) // destination address incremented
  128. ;
  129. SSP_DMACH->DMACCConfig = 1 // enable channel
  130. | (SSP_DMAID_RX << 1) // data source SSP RX
  131. | (2 << 11) // transfer from peripheral to memory
  132. ;
  133. /* Enable RX FIFO DMA */
  134. SSP_REGS->DMACR = 1;
  135. /* Write <length> bytes into TX FIFO */
  136. // FIXME: Any value in doing this using DMA too?
  137. while (txlen > 0) {
  138. while (txlen > 0 && BITBAND(SSP_REGS->SR, SSP_TNF)) {
  139. txlen--;
  140. SSP_REGS->DR = 0xff;
  141. }
  142. }
  143. /* Wait until DMA channel disables itself */
  144. while (SSP_DMACH->DMACCConfig & 1) ;
  145. /* Disable RX FIFO DMA */
  146. SSP_REGS->DMACR = 0;
  147. }
  148. }
  149. void spi_set_speed(spi_speed_t speed) {
  150. /* Wait until TX fifo is empty */
  151. while (!BITBAND(SSP_REGS->SR, 0)) ;
  152. /* Disable SSP (FIXME: Is this required?) */
  153. SSP_REGS->CR1 = 0;
  154. /* Change clock divisor */
  155. if (speed == SPI_SPEED_FAST) {
  156. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
  157. } else if (speed == SPI_SPEED_SLOW) {
  158. SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
  159. } else if (speed == SPI_SPEED_FPGA_FAST) {
  160. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST;
  161. } else {
  162. SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW;
  163. }
  164. /* Enable SSP */
  165. SSP_REGS->CR1 = BV(1);
  166. }