main.c 5.4 KB

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  1. #include <arm/NXP/LPC17xx/LPC17xx.h>
  2. #include <string.h>
  3. #include "config.h"
  4. #include "obj/autoconf.h"
  5. #include "clock.h"
  6. #include "uart.h"
  7. #include "bits.h"
  8. #include "power.h"
  9. #include "timer.h"
  10. #include "ff.h"
  11. #include "diskio.h"
  12. #include "spi.h"
  13. #include "fileops.h"
  14. #include "fpga.h"
  15. #include "fpga_spi.h"
  16. #include "filetypes.h"
  17. #include "memory.h"
  18. #include "snes.h"
  19. #include "led.h"
  20. #include "sort.h"
  21. #include "cic.h"
  22. #include "tests.h"
  23. #include "cli.h"
  24. #include "sdnative.h"
  25. #include "crc.h"
  26. #include "smc.h"
  27. #include "msu1.h"
  28. #include "rtc.h"
  29. #include "tests.h"
  30. #define EMC0TOGGLE (3<<4)
  31. #define MR0R (1<<1)
  32. int i;
  33. int sd_offload = 0, ff_sd_offload = 0, sd_offload_tgt = 0;
  34. int sd_offload_partial = 0;
  35. uint16_t sd_offload_partial_start = 0;
  36. uint16_t sd_offload_partial_end = 0;
  37. volatile enum diskstates disk_state;
  38. extern volatile tick_t ticks;
  39. extern snes_romprops_t romprops;
  40. extern volatile int reset_changed;
  41. enum system_states {
  42. SYS_RTC_STATUS = 0
  43. };
  44. int main(void) {
  45. LPC_GPIO2->FIODIR = BV(4) | BV(5);
  46. LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
  47. BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
  48. LPC_GPIO0->FIODIR = BV(16);
  49. /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */
  50. LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */
  51. | BV(3) | BV(5); /* SSP0 (FPGA) except SS */
  52. LPC_PINCON->PINSEL0 = BV(31); /* SSP0 */
  53. /* | BV(13) | BV(15) | BV(17) | BV(19) SSP1 (SD) */
  54. /* pull-down CIC data lines */
  55. LPC_PINCON->PINMODE0 = BV(0) | BV(1) | BV(2) | BV(3);
  56. clock_disconnect();
  57. snes_init();
  58. snes_reset(1);
  59. power_init();
  60. timer_init();
  61. uart_init();
  62. fpga_spi_init();
  63. spi_preinit();
  64. led_init();
  65. /* do this last because the peripheral init()s change PCLK dividers */
  66. clock_init();
  67. LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */
  68. led_pwm();
  69. sdn_init();
  70. printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
  71. printf("PCONP=%lx\n", LPC_SC->PCONP);
  72. file_init();
  73. cic_init(0);
  74. /* setup timer (fpga clk) */
  75. LPC_TIM3->CTCR=0;
  76. LPC_TIM3->EMR=EMC0TOGGLE;
  77. LPC_TIM3->MCR=MR0R;
  78. LPC_TIM3->MR0=1;
  79. LPC_TIM3->TCR=1;
  80. fpga_init();
  81. char *testnames[11] = { "SD ", "USB ", "RTC ", "CIC ",
  82. "FPGA ", "RAM ", "CLK ", "DAC ",
  83. "SNES IRQ", "SNES RAM", "SNES PA "};
  84. char *teststate_names [3] = { "no run", "\x1b[32;1mPassed\x1b[m", "\x1b[31;1mFAILED\x1b[m" };
  85. int testresults[11] = { NO_RUN, NO_RUN, NO_RUN, NO_RUN, NO_RUN,
  86. NO_RUN, NO_RUN, NO_RUN, NO_RUN, NO_RUN,
  87. NO_RUN };
  88. testresults[TEST_SD] = test_sd();
  89. //testresults[TEST_USB] = test_usb();
  90. //testresults[TEST_RTC] = test_rtc();
  91. delay_ms(209);
  92. // testresults[TEST_CIC] = test_cic();
  93. testresults[TEST_FPGA] = test_fpga();
  94. testresults[TEST_RAM] = test_mem();
  95. printf("Loading SNES test ROM\n=====================\n");
  96. load_rom((uint8_t*)"/sd2snes/test.bin", 0, LOADROM_WITH_RESET);
  97. printf("\n\n\n");
  98. delay_ms(1000);
  99. testresults[TEST_CLK] = test_clk();
  100. fpga_set_bram_addr(0x1fff);
  101. fpga_write_bram_data(0x01); // tell SNES test program to continue
  102. uint8_t snestest_irq_state, snestest_pa_state, snestest_mem_state, snestest_mem_bank;
  103. uint8_t snestest_irq_done = 0, snestest_pa_done = 0, snestest_mem_done = 0;
  104. uint8_t last_irq_state = 0x77, last_pa_state = 0x77, last_mem_state = 0x77, last_mem_bank = 0x77;
  105. uint32_t failed_addr = 0;
  106. while(!(snestest_irq_done & snestest_pa_done & snestest_mem_done)) {
  107. fpga_set_bram_addr(0);
  108. snestest_irq_state = fpga_read_bram_data();
  109. snestest_mem_state = fpga_read_bram_data();
  110. snestest_pa_state = fpga_read_bram_data();
  111. snestest_mem_bank = fpga_read_bram_data();
  112. if(snestest_irq_state != last_irq_state
  113. || snestest_mem_state != last_mem_state
  114. || snestest_pa_state != last_pa_state
  115. || snestest_mem_bank != last_mem_bank) {
  116. printf("SNES test status: IRQ: %02x PA: %02x MEM: %02x/%02x\r", snestest_irq_state, snestest_pa_state, snestest_mem_state, snestest_mem_bank);
  117. }
  118. last_irq_state = snestest_irq_state;
  119. last_mem_state = snestest_mem_state;
  120. last_pa_state = snestest_pa_state;
  121. last_mem_bank = snestest_mem_bank;
  122. if(snestest_pa_state != 0x00) snestest_pa_done = 1;
  123. if(snestest_irq_state != 0x00) snestest_irq_done = 1;
  124. if(snestest_mem_state == 0xff || snestest_mem_state == 0x5a) snestest_mem_done = 1;
  125. cli_entrycheck();
  126. }
  127. printf("\n");
  128. if(snestest_pa_state == 0xff) testresults[TEST_SNES_PA] = FAILED;
  129. else testresults[TEST_SNES_PA] = PASSED;
  130. if(snestest_irq_state == 0xff) testresults[TEST_SNES_IRQ] = FAILED;
  131. else testresults[TEST_SNES_IRQ] = PASSED;
  132. if(snestest_mem_state == 0xff) {
  133. testresults[TEST_SNES_RAM] = FAILED;
  134. fpga_set_bram_addr(4);
  135. failed_addr = fpga_read_bram_data();
  136. failed_addr |= fpga_read_bram_data() << 8;
  137. failed_addr |= fpga_read_bram_data() << 16;
  138. printf("SNES MEM test FAILED (failed address: %06lx)\n", failed_addr);
  139. }
  140. else testresults[TEST_SNES_RAM] = PASSED;
  141. printf("\n\nTEST SUMMARY\n============\n\n");
  142. printf("Test Result\n----------------\n");
  143. int testcount;
  144. for(testcount=0; testcount < 11; testcount++) {
  145. printf("%s %s\n", testnames[testcount], teststate_names[testresults[testcount]]);
  146. }
  147. cli_loop();
  148. while(1);
  149. }