lpc1754.cfg 2.8 KB

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  1. # NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
  2. # reset_config trst_and_srst
  3. if { [info exists CHIPNAME] } {
  4. set _CHIPNAME $CHIPNAME
  5. } else {
  6. set _CHIPNAME lpc1754
  7. }
  8. # After reset the chip is clocked by the ~4MHz internal RC oscillator.
  9. # When board-specific code (reset-init handler or device firmware)
  10. # configures another oscillator and/or PLL0, set CCLK to match; if
  11. # you don't, then flash erase and write operations may misbehave.
  12. # (The ROM code doing those updates cares about core clock speed...)
  13. #
  14. # CCLK is the core clock frequency in KHz
  15. if { [info exists CCLK ] } {
  16. set _CCLK $CCLK
  17. } else {
  18. set _CCLK 4000
  19. }
  20. if { [info exists CPUTAPID ] } {
  21. set _CPUTAPID $CPUTAPID
  22. } else {
  23. set _CPUTAPID 0x4ba00477
  24. }
  25. #delays on reset lines
  26. #if your OpenOCD version rejects "jtag_nsrst_delay" replace it with:
  27. adapter_nsrst_delay 200
  28. #jtag_nsrst_delay 200
  29. jtag_ntrst_delay 200
  30. # LPC2000 & LPC1700 -> SRST causes TRST
  31. #reset_config srst_pulls_trst
  32. reset_config trst_and_srst srst_push_pull trst_push_pull
  33. jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  34. #jtag newtap x3s tap -irlen 6 -ircapture 0x11 -irmask 0x11 -expected-id 0x0141c093
  35. set _TARGETNAME $_CHIPNAME.cpu
  36. #target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME -event reset-init 0
  37. target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME -event reset-init 0
  38. # LPC1754 has 16kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
  39. # and 16K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
  40. $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x4000
  41. $_TARGETNAME configure -work-area-phys 0x2007c000 -work-area-size 0x4000
  42. # LPC1754 has 128kB of flash memory, managed by ROM code (including a
  43. # boot loader which verifies the flash exception table's checksum).
  44. # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
  45. set _FLASHNAME $_CHIPNAME.flash
  46. flash bank $_FLASHNAME lpc2000 0x0 0x20000 0 0 $_TARGETNAME \
  47. lpc1700 $_CCLK calc_checksum
  48. # Run with *real slow* clock by default since the
  49. # boot rom could have been playing with the PLL, so
  50. # we have no idea what clock the target is running at.
  51. adapter_khz 1000
  52. $_TARGETNAME configure -event reset-init {
  53. # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
  54. # "User Flash Mode" where interrupt vectors are _not_ remapped,
  55. # and reside in flash instead).
  56. #
  57. # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
  58. # Bit Symbol Value Description Reset
  59. # value
  60. # 0 MAP Memory map control. 0
  61. # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
  62. # 1 User mode. The on-chip Flash memory is mapped to address 0.
  63. # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
  64. #
  65. # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
  66. mww 0x400FC040 0x01
  67. }