config.h 2.8 KB

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  1. #ifndef _CONFIG_H
  2. #define _CONFIG_H
  3. // #define DEBUG_BL
  4. // #define DEBUG_SD
  5. // #define DEBUG_IRQ
  6. #define DEBUG_UART
  7. #ifdef DEBUG_UART
  8. #define DBG_UART
  9. #else
  10. #define DBG_UART while(0)
  11. #endif
  12. #ifdef DEBUG_BL
  13. #define DBG_BL
  14. #else
  15. #define DBG_BL while(0)
  16. #endif
  17. #define FW_START (0x00002000L)
  18. #define FLASH_SECTORS (17)
  19. #define VER "0.0.1(NSFW)"
  20. #define IN_AHBRAM __attribute__ ((section(".ahbram")))
  21. #define SD_DT_INT_SETUP() do {\
  22. BITBANG(LPC_GPIOINT->IO2IntEnR, SD_DT_BIT) = 1;\
  23. BITBANG(LPC_GPIOINT->IO2IntEnF, SD_DT_BIT) = 1;\
  24. } while(0)
  25. #define SD_CHANGE_DETECT (BITBANG(LPC_GPIOINT->IO2IntStatR, SD_DT_BIT)\
  26. |BITBANG(LPC_GPIOINT->IO2IntStatF, SD_DT_BIT))
  27. #define SD_CHANGE_CLR() do {LPC_GPIOINT->IO2IntClr = BV(SD_DT_BIT);} while(0)
  28. #define SD_DT_REG LPC_GPIO0
  29. #define SD_DT_BIT 8
  30. #define SD_WP_REG LPC_GPIO0
  31. #define SD_WP_BIT 6
  32. #define SDCARD_DETECT (!(BITBANG(SD_DT_REG->FIOPIN, SD_DT_BIT)))
  33. #define SDCARD_WP (BITBANG(SD_WP_REG->FIOPIN, SD_WP_BIT))
  34. #define SD_SUPPLY_VOLTAGE (1L<<21) /* 3.3V - 3.4V */
  35. #define CONFIG_SD_BLOCKTRANSFER 1
  36. #define CONFIG_SD_AUTO_RETRIES 10
  37. // #define SD_CHANGE_VECT
  38. #define CONFIG_SD_DATACRC 1
  39. #define CONFIG_UART_NUM 3
  40. // #define CONFIG_CPU_FREQUENCY 90315789
  41. #define CONFIG_CPU_FREQUENCY (96000000L)
  42. //#define CONFIG_CPU_FREQUENCY 46000000
  43. #define CONFIG_UART_PCLKDIV 1
  44. #define CONFIG_UART_TX_BUF_SHIFT 8
  45. //#define CONFIG_UART_BAUDRATE 921600
  46. #define CONFIG_UART_BAUDRATE 115200
  47. #define CONFIG_UART_DEADLOCKABLE
  48. #define SSP_CLK_DIVISOR_FAST 2
  49. #define SSP_CLK_DIVISOR_SLOW 250
  50. #define SSP_CLK_DIVISOR_FPGA_FAST 6
  51. #define SSP_CLK_DIVISOR_FPGA_SLOW 20
  52. #define SNES_RESET_REG LPC_GPIO1
  53. #define SNES_RESET_BIT 26
  54. #define SNES_CIC_D0_REG LPC_GPIO0
  55. #define SNES_CIC_D0_BIT 1
  56. #define SNES_CIC_D1_REG LPC_GPIO0
  57. #define SNES_CIC_D1_BIT 0
  58. #define SNES_CIC_STATUS_REG LPC_GPIO1
  59. #define SNES_CIC_STATUS_BIT 29
  60. #define SNES_CIC_PAIR_REG LPC_GPIO1
  61. #define SNES_CIC_PAIR_BIT 25
  62. #define QSORT_MAXELEM 1024
  63. #define SSP_REGS LPC_SSP0
  64. #define SSP_PCLKREG PCLKSEL1
  65. // 1: PCLKSEL0
  66. #define SSP_PCLKBIT 10
  67. // 1: 20
  68. #define SSP_DMAID_TX 0
  69. // 1: 2
  70. #define SSP_DMAID_RX 1
  71. // 1: 3
  72. #define SSP_DMACH LPC_GPDMACH0
  73. #define SD_CLKREG LPC_GPIO0
  74. #define SD_CMDREG LPC_GPIO0
  75. #define SD_DAT0REG LPC_GPIO2
  76. #define SD_DAT1REG LPC_GPIO2
  77. #define SD_DAT2REG LPC_GPIO2
  78. #define SD_DAT3REG LPC_GPIO2
  79. #define SD_CLKPIN (7)
  80. #define SD_CMDPIN (9)
  81. #define SD_DAT0PIN (0)
  82. #define SD_DAT1PIN (1)
  83. #define SD_DAT2PIN (2)
  84. #define SD_DAT3PIN (3)
  85. #define SD_DAT (LPC_GPIO2->FIOPIN & 0xf)
  86. #endif