srtc.v 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183
  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 13:33:14 02/09/2011
  7. // Design Name:
  8. // Module Name: srtc
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module srtc(
  22. input clkin,
  23. input addr_in,
  24. input [3:0] data_in,
  25. output [7:0] data_out,
  26. input [59:0] rtc_data_in,
  27. output [59:0] rtc_data_out,
  28. input reg_we,
  29. input reg_oe,
  30. input enable,
  31. output rtc_we,
  32. input reset
  33. );
  34. reg [59:0] rtc_data_r;
  35. reg [59:0] rtc_data_out_r;
  36. assign rtc_data_out = rtc_data_out_r;
  37. reg [3:0] rtc_ptr;
  38. reg [7:0] data_out_r;
  39. reg [4:0] mode_r;
  40. reg rtc_we_r;
  41. assign rtc_we = rtc_we_r;
  42. assign data_out = data_out_r;
  43. reg [5:0] reg_oe_sreg;
  44. always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe};
  45. wire reg_oe_falling = (reg_oe_sreg[5:1] == 5'b11110);
  46. wire reg_oe_rising = (reg_oe_sreg[5:1] == 5'b00001);
  47. reg [5:0] reg_we_sreg;
  48. always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[4:0], reg_we};
  49. wire reg_we_rising = (reg_we_sreg[5:1] == 5'b00001);
  50. reg [1:0] reset_sreg;
  51. always @(posedge clkin) reset_sreg <= {reset_sreg[0], reset};
  52. wire reset_rising = (reset_sreg[1:0] == 2'b01);
  53. reg[2:0] we_countdown_r;
  54. parameter SRTC_IDLE = 5'b00001;
  55. parameter SRTC_READ = 5'b00010;
  56. parameter SRTC_COMMAND = 5'b00100;
  57. parameter SRTC_WRITE = 5'b01000;
  58. parameter SRTC_WRITE2 = 5'b10000;
  59. initial begin
  60. rtc_we_r = 0;
  61. mode_r <= SRTC_READ;
  62. rtc_ptr <= 4'hf;
  63. end
  64. always @(posedge clkin) begin
  65. if(reset_rising) begin
  66. mode_r <= SRTC_READ;
  67. rtc_ptr <= 4'hf;
  68. end else if(mode_r == SRTC_WRITE2) begin
  69. we_countdown_r <= we_countdown_r - 1;
  70. if (we_countdown_r == 3'b000) begin
  71. mode_r <= SRTC_WRITE;
  72. rtc_we_r <= 0;
  73. end
  74. end else if(reg_we_rising && enable) begin
  75. case (addr_in)
  76. // 1'b0: // data register is read only
  77. 1'b1: // control register
  78. case (data_in)
  79. 4'hd: begin
  80. mode_r <= SRTC_READ;
  81. rtc_ptr <= 4'hf;
  82. end
  83. 4'he: begin
  84. mode_r <= SRTC_COMMAND;
  85. end
  86. 4'hf: begin
  87. end
  88. default: begin
  89. if(mode_r == SRTC_COMMAND) begin
  90. case (data_in)
  91. 4'h0: begin
  92. mode_r <= SRTC_WRITE;
  93. rtc_data_out_r <= rtc_data_in;
  94. rtc_ptr <= 4'h0;
  95. end
  96. 4'h4: begin
  97. mode_r <= SRTC_IDLE;
  98. rtc_ptr <= 4'hf;
  99. end
  100. default:
  101. mode_r <= SRTC_IDLE;
  102. endcase
  103. end else if(mode_r == SRTC_WRITE) begin
  104. rtc_ptr <= rtc_ptr + 1;
  105. case(rtc_ptr)
  106. 0: rtc_data_out_r[3:0] <= data_in;
  107. 1: rtc_data_out_r[7:4] <= data_in;
  108. 2: rtc_data_out_r[11:8] <= data_in;
  109. 3: rtc_data_out_r[15:12] <= data_in;
  110. 4: rtc_data_out_r[19:16] <= data_in;
  111. 5: rtc_data_out_r[23:20] <= data_in;
  112. 6: rtc_data_out_r[27:24] <= data_in;
  113. 7: rtc_data_out_r[31:28] <= data_in;
  114. 8: begin
  115. rtc_data_out_r[35:32] <= (data_in < 10)
  116. ? data_in
  117. : data_in - 10;
  118. rtc_data_out_r[39:36] <= data_in < 10 ? 0 : 1;
  119. end
  120. 9: rtc_data_out_r[43:40] <= data_in;
  121. 10: rtc_data_out_r[47:44] <= data_in;
  122. 11: begin
  123. rtc_data_out_r[51:48] <= (data_in < 10)
  124. ? data_in
  125. : data_in - 10;
  126. rtc_data_out_r[55:52] <= data_in < 10 ? 1 : 2;
  127. end
  128. endcase
  129. mode_r <= SRTC_WRITE2;
  130. we_countdown_r <= 5;
  131. rtc_we_r <= 1;
  132. end
  133. end
  134. endcase
  135. endcase
  136. end else if(reg_oe_falling && enable) begin
  137. case (addr_in)
  138. 1'b0: // read data register
  139. if(mode_r == SRTC_READ) begin
  140. case(rtc_ptr)
  141. 0: data_out_r <= rtc_data_r[3:0];
  142. 1: data_out_r <= rtc_data_r[7:4];
  143. 2: data_out_r <= rtc_data_r[11:8];
  144. 3: data_out_r <= rtc_data_r[15:12];
  145. 4: data_out_r <= rtc_data_r[19:16];
  146. 5: data_out_r <= rtc_data_r[23:20];
  147. 6: data_out_r <= rtc_data_r[27:24];
  148. 7: data_out_r <= rtc_data_r[31:28];
  149. 8: data_out_r <= rtc_data_r[35:32]
  150. + (rtc_data_r[39:36] << 1)
  151. + (rtc_data_r[39:36] << 3);
  152. 9: data_out_r <= rtc_data_r[43:40];
  153. 10: data_out_r <= rtc_data_r[47:44];
  154. 11: data_out_r <= rtc_data_r[51:48]
  155. + (rtc_data_r[55:52] << 1)
  156. + (rtc_data_r[55:52] << 3) - 10;
  157. 12: data_out_r <= rtc_data_r[59:56];
  158. 15: begin
  159. rtc_data_r <= rtc_data_in;
  160. data_out_r <= 8'h0f;
  161. end
  162. default: data_out_r <= 8'h0f;
  163. endcase
  164. rtc_ptr <= rtc_ptr == 13 ? 15 : rtc_ptr + 1;
  165. end else begin
  166. data_out_r <= 8'h00;
  167. end
  168. // 1'b1: // control register is write only
  169. endcase
  170. end
  171. end
  172. endmodule